KR20120117843A - 다층 결정질 구조물의 제조 방법 - Google Patents

다층 결정질 구조물의 제조 방법 Download PDF

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Publication number
KR20120117843A
KR20120117843A KR1020127019987A KR20127019987A KR20120117843A KR 20120117843 A KR20120117843 A KR 20120117843A KR 1020127019987 A KR1020127019987 A KR 1020127019987A KR 20127019987 A KR20127019987 A KR 20127019987A KR 20120117843 A KR20120117843 A KR 20120117843A
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South Korea
Prior art keywords
layer
implanted
ions
bonding
soi structure
Prior art date
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KR1020127019987A
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English (en)
Korean (ko)
Inventor
데일 에이. 위테
제프리 엘. 리버트
Original Assignee
엠이엠씨 일렉트로닉 머티리얼즈, 인크.
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Application filed by 엠이엠씨 일렉트로닉 머티리얼즈, 인크. filed Critical 엠이엠씨 일렉트로닉 머티리얼즈, 인크.
Publication of KR20120117843A publication Critical patent/KR20120117843A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24174—Structurally defined web or sheet [e.g., overall dimension, etc.] including sheet or component perpendicular to plane of web or sheet

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  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Recrystallisation Techniques (AREA)
KR1020127019987A 2009-12-30 2010-12-22 다층 결정질 구조물의 제조 방법 Withdrawn KR20120117843A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US29096109P 2009-12-30 2009-12-30
US61/290,961 2009-12-30

Publications (1)

Publication Number Publication Date
KR20120117843A true KR20120117843A (ko) 2012-10-24

Family

ID=43587555

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020127019987A Withdrawn KR20120117843A (ko) 2009-12-30 2010-12-22 다층 결정질 구조물의 제조 방법

Country Status (8)

Country Link
US (2) US8367519B2 (https=)
EP (2) EP2519965B1 (https=)
JP (2) JP5591949B2 (https=)
KR (1) KR20120117843A (https=)
CN (1) CN103026460A (https=)
SG (1) SG181986A1 (https=)
TW (2) TW201330062A (https=)
WO (1) WO2011082079A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150099847A (ko) * 2012-12-28 2015-09-01 썬에디슨 세미컨덕터 리미티드 다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법

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US8853054B2 (en) 2012-03-06 2014-10-07 Sunedison Semiconductor Limited Method of manufacturing silicon-on-insulator wafers
US8796054B2 (en) * 2012-05-31 2014-08-05 Corning Incorporated Gallium nitride to silicon direct wafer bonding
JP6024400B2 (ja) 2012-11-07 2016-11-16 ソニー株式会社 半導体装置、半導体装置の製造方法、及びアンテナスイッチモジュール
TWI509681B (zh) * 2013-11-15 2015-11-21 All Ring Tech Co Ltd Method and apparatus for processing on wafers
US9496128B1 (en) 2015-10-15 2016-11-15 International Business Machines Corporation Controlled spalling utilizing vaporizable release layers
SG11202009989YA (en) 2018-04-27 2020-11-27 Globalwafers Co Ltd Light assisted platelet formation facilitating layer transfer from a semiconductor donor substrate

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US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
JPH11145438A (ja) * 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
FR2773261B1 (fr) * 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US7076042B1 (en) 2000-09-06 2006-07-11 Cisco Technology, Inc. Processing a subscriber call in a telecommunications network
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
FR2819099B1 (fr) 2000-12-28 2003-09-26 Commissariat Energie Atomique Procede de realisation d'une structure empilee
US6686630B2 (en) * 2001-02-07 2004-02-03 International Business Machines Corporation Damascene double-gate MOSFET structure and its fabrication method
JP2004537161A (ja) 2001-04-11 2004-12-09 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド 高抵抗率ｃｚシリコンにおけるサーマルドナー生成の制御
TW550681B (en) 2001-06-22 2003-09-01 Memc Electronic Materials Process for producing silicon on insulator structure having intrinsic gettering by ion implantation
JPWO2003046993A1 (ja) * 2001-11-29 2005-04-14 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US20040224482A1 (en) * 2001-12-20 2004-11-11 Kub Francis J. Method for transferring thin film layer material to a flexible substrate using a hydrogen ion splitting technique
US6833322B2 (en) 2002-10-17 2004-12-21 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film
WO2004061944A1 (en) 2003-01-07 2004-07-22 S.O.I.Tec Silicon On Insulator Technologies Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
JP4407384B2 (ja) * 2004-05-28 2010-02-03 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
FR2876841B1 (fr) * 2004-10-19 2007-04-13 Commissariat Energie Atomique Procede de realisation de multicouches sur un substrat
DE102004054564B4 (de) * 2004-11-11 2008-11-27 Siltronic Ag Halbleitersubstrat und Verfahren zu dessen Herstellung
US10374120B2 (en) * 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
US20070117350A1 (en) 2005-08-03 2007-05-24 Memc Electronic Materials, Inc. Strained silicon on insulator (ssoi) with layer transfer from oxidized donor
FR2889887B1 (fr) * 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
EP1763069B1 (en) 2005-09-07 2016-04-13 Soitec Method for forming a semiconductor heterostructure
US7608521B2 (en) * 2006-05-31 2009-10-27 Corning Incorporated Producing SOI structure using high-purity ion shower
FR2906078B1 (fr) * 2006-09-19 2009-02-13 Commissariat Energie Atomique Procede de fabrication d'une structure micro-technologique mixte et une structure ainsi obtenue
FR2913528B1 (fr) 2007-03-06 2009-07-03 Soitec Silicon On Insulator Procede de fabrication d'un substrat comportant une couche d'oxyde enterree pour la realisation de composants electroniques ou analogues.
FR2917235B1 (fr) * 2007-06-06 2010-09-03 Soitec Silicon On Insulator Procede de realisation de composants hybrides.
JP5386856B2 (ja) * 2008-06-03 2014-01-15 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
SG159484A1 (en) * 2008-09-05 2010-03-30 Semiconductor Energy Lab Method of manufacturing soi substrate
JP5364345B2 (ja) * 2008-11-12 2013-12-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8679942B2 (en) * 2008-11-26 2014-03-25 Soitec Strain engineered composite semiconductor substrates and methods of forming same
US20100216295A1 (en) * 2009-02-24 2010-08-26 Alex Usenko Semiconductor on insulator made using improved defect healing process
US8198172B2 (en) * 2009-02-25 2012-06-12 Micron Technology, Inc. Methods of forming integrated circuits using donor and acceptor substrates

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150099847A (ko) * 2012-12-28 2015-09-01 썬에디슨 세미컨덕터 리미티드 다층 반도체 디바이스들의 제조에서의 저온 층 전이를 위한 방법

Also Published As

Publication number Publication date
CN103026460A (zh) 2013-04-03
US20130137241A1 (en) 2013-05-30
JP2013516767A (ja) 2013-05-13
JP5591949B2 (ja) 2014-09-17
TW201330062A (zh) 2013-07-16
SG181986A1 (en) 2012-08-30
WO2011082079A1 (en) 2011-07-07
JP2013175787A (ja) 2013-09-05
US20110159665A1 (en) 2011-06-30
TWI430339B (zh) 2014-03-11
US8367519B2 (en) 2013-02-05
EP2733735A2 (en) 2014-05-21
TW201140662A (en) 2011-11-16
EP2733735A3 (en) 2014-07-23
EP2519965A1 (en) 2012-11-07
EP2519965B1 (en) 2014-10-01

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