CN102971795A - 使用单个缓冲区同时读取多个存储器装置的方法和设备 - Google Patents

使用单个缓冲区同时读取多个存储器装置的方法和设备 Download PDF

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Publication number
CN102971795A
CN102971795A CN2011800335300A CN201180033530A CN102971795A CN 102971795 A CN102971795 A CN 102971795A CN 2011800335300 A CN2011800335300 A CN 2011800335300A CN 201180033530 A CN201180033530 A CN 201180033530A CN 102971795 A CN102971795 A CN 102971795A
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CN
China
Prior art keywords
data
page buffer
page
buffer zone
source
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Pending
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CN2011800335300A
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English (en)
Chinese (zh)
Inventor
R·舒茨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nova Chip Canada Co
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Mosaid Technologies Inc
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Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of CN102971795A publication Critical patent/CN102971795A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
CN2011800335300A 2010-05-07 2011-05-06 使用单个缓冲区同时读取多个存储器装置的方法和设备 Pending CN102971795A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US33223210P 2010-05-07 2010-05-07
US61/332,232 2010-05-07
PCT/CA2011/050281 WO2011137541A1 (en) 2010-05-07 2011-05-06 Method and apparatus for concurrently reading a plurality of memory devices using a single buffer

Publications (1)

Publication Number Publication Date
CN102971795A true CN102971795A (zh) 2013-03-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011800335300A Pending CN102971795A (zh) 2010-05-07 2011-05-06 使用单个缓冲区同时读取多个存储器装置的方法和设备

Country Status (8)

Country Link
US (1) US20110276775A1 (https=)
EP (1) EP2567379A4 (https=)
JP (1) JP5665974B2 (https=)
KR (1) KR20130071436A (https=)
CN (1) CN102971795A (https=)
CA (1) CA2798868A1 (https=)
TW (1) TW201209820A (https=)
WO (1) WO2011137541A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107025069A (zh) * 2016-01-13 2017-08-08 桑迪士克科技有限责任公司 非易失性存储器的数据路径控制
CN107025926A (zh) * 2015-11-04 2017-08-08 三星电子株式会社 存储装置和操作存储装置的方法
TWI743736B (zh) * 2020-04-08 2021-10-21 瑞昱半導體股份有限公司 資料傳輸系統、電路與方法

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8565092B2 (en) 2010-11-18 2013-10-22 Cisco Technology, Inc. Dynamic flow redistribution for head of line blocking avoidance
US20120307641A1 (en) * 2011-05-31 2012-12-06 Cisco Technology, Inc. Dynamic Flow Segregation for Optimal Load Balancing Among Ports in an Etherchannel Group
US8462561B2 (en) 2011-08-03 2013-06-11 Hamilton Sundstrand Corporation System and method for interfacing burst mode devices and page mode devices
US20130326090A1 (en) * 2012-05-29 2013-12-05 Mosaid Technologies Incorporated Ring topology status indication
US9336112B2 (en) * 2012-06-19 2016-05-10 Apple Inc. Parallel status polling of multiple memory devices
US9471484B2 (en) 2012-09-19 2016-10-18 Novachips Canada Inc. Flash memory controller having dual mode pin-out
US20140293705A1 (en) * 2013-03-26 2014-10-02 Conversant Intellecual Property Management Inc. Asynchronous bridge chip
KR102074329B1 (ko) * 2013-09-06 2020-02-06 삼성전자주식회사 데이터 저장 장치 및 그것의 데이터 처리 방법
US9400745B2 (en) 2013-11-06 2016-07-26 International Business Machines Corporation Physical address management in solid state memory
KR20170086345A (ko) * 2016-01-18 2017-07-26 에스케이하이닉스 주식회사 메모리 칩 및 메모리 컨트롤러를 포함하는 메모리 시스템
US10592114B2 (en) 2016-03-03 2020-03-17 Samsung Electronics Co., Ltd. Coordinated in-module RAS features for synchronous DDR compatible memory
US9830086B2 (en) * 2016-03-03 2017-11-28 Samsung Electronics Co., Ltd. Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group
KR101867219B1 (ko) * 2017-02-22 2018-06-12 연세대학교 산학협력단 동적 메모리 인터페이스에 기반하여 서로 다른 메모리 연산들을 처리하기 위한 장치 및 방법
US9853805B1 (en) * 2017-02-24 2017-12-26 Dewesoft D.O.O. Buffered equidistant data acquisition for control applications
US10140222B1 (en) 2017-07-06 2018-11-27 Micron Technology, Inc. Interface components
US10802750B2 (en) * 2019-02-28 2020-10-13 Silicon Motion Inc. Universal flash storage memory module, controller and electronic device with advanced turbo write buffer and method for operating the memory module
US11232047B2 (en) * 2019-05-28 2022-01-25 Rambus Inc. Dedicated cache-related block transfer in a memory system
CN115004146B (zh) * 2020-02-14 2025-09-19 华为技术有限公司 固态存储硬盘和固态存储硬盘的控制方法
JP2022049553A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置および方法
US12050773B2 (en) * 2021-08-12 2024-07-30 Micron Technology, Inc. Completion flag for memory operations
JP2023140124A (ja) 2022-03-22 2023-10-04 キオクシア株式会社 半導体装置、コントローラ、及びホスト装置
US12481434B2 (en) * 2023-09-07 2025-11-25 SK hynix NAND Product Solutions Corporation Systems, methods, and media for reducing power consumption of multi-plane non-volatile memory solid-state drives

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4442504A (en) * 1981-03-09 1984-04-10 Allen-Bradley Company Modular programmable controller
US20090021992A1 (en) * 2007-07-18 2009-01-22 Hakjune Oh Memory with data control
CN101568903A (zh) * 2006-12-21 2009-10-28 英特尔公司 Nand闪存的基于命令的控制
WO2010027983A1 (en) * 2008-09-03 2010-03-11 Marvell World Trade Ltd. Progamming data into a multi-plane flash memory
US20100091536A1 (en) * 2008-10-14 2010-04-15 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10009A (en) * 1853-09-13 Cutting boots and shoes
US3742456A (en) * 1972-04-05 1973-06-26 Pitney Bowes Inc Apparatus for selectively formatting serial data bits into separate data characters
US3748650A (en) * 1972-08-21 1973-07-24 Ibm Input/output hardware trace monitor
US4124889A (en) * 1975-12-24 1978-11-07 Computer Automation, Inc. Distributed input/output controller system
US4133030A (en) * 1977-01-19 1979-01-02 Honeywell Information Systems Inc. Control system providing for the transfer of data in a communications processing system employing channel dedicated control blocks
US4275440A (en) * 1978-10-02 1981-06-23 International Business Machines Corporation I/O Interrupt sequencing for real time and burst mode devices
US4456983A (en) * 1979-10-12 1984-06-26 Dresser Industries, Inc. System and method for visual display of well logging data
JPH07334372A (ja) * 1993-12-24 1995-12-22 Seiko Epson Corp エミュレートシステム及びエミュレート方法
JP2731768B2 (ja) * 1995-10-20 1998-03-25 甲府日本電気株式会社 メモリ制御装置
US5751638A (en) * 1997-01-17 1998-05-12 Integrated Device Technology, Inc. Mail-box design for non-blocking communication across ports of a multi-port device
US6988154B2 (en) * 2000-03-10 2006-01-17 Arc International Memory interface and method of interfacing between functional entities
US7302503B2 (en) * 2002-04-01 2007-11-27 Broadcom Corporation Memory access engine having multi-level command structure
DE602004019990D1 (de) * 2004-08-30 2009-04-23 Magima Digital Information Co Verfahren und system zum datentransfer
WO2006059284A1 (en) * 2004-12-01 2006-06-08 Koninklijke Philips Electronics N.V. Data processing system and method for converting and synchronising data traffic
US7243173B2 (en) * 2004-12-14 2007-07-10 Rockwell Automation Technologies, Inc. Low protocol, high speed serial transfer for intra-board or inter-board data communication
US20070005834A1 (en) * 2005-06-30 2007-01-04 Intel Corporation Memory chips with buffer circuitry
JP2007026021A (ja) * 2005-07-15 2007-02-01 Nec Electronics Corp バス制御システム及びバス制御方法
EP1932158A4 (en) 2005-09-30 2008-10-15 Mosaid Technologies Inc MEMORY WITH OUTPUT CONTROL
US7652922B2 (en) * 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US20070130374A1 (en) * 2005-11-15 2007-06-07 Intel Corporation Multiported memory with configurable ports
US7562163B2 (en) * 2006-08-18 2009-07-14 International Business Machines Corporation Apparatus and method to locate a storage device disposed in a data storage system
EP2487794A3 (en) * 2006-08-22 2013-02-13 Mosaid Technologies Incorporated Modular command structure for memory and memory system
JP4674865B2 (ja) * 2006-10-30 2011-04-20 株式会社日立製作所 半導体集積回路
US7768297B2 (en) * 2007-01-31 2010-08-03 Rambus, Inc. Multi-drop bus system
US8086785B2 (en) * 2007-02-22 2011-12-27 Mosaid Technologies Incorporated System and method of page buffer operation for memory devices
US8291248B2 (en) * 2007-12-21 2012-10-16 Mosaid Technologies Incorporated Non-volatile semiconductor memory device with power saving feature
US20100115172A1 (en) * 2008-11-04 2010-05-06 Mosaid Technologies Incorporated Bridge device having a virtual page buffer
US8037235B2 (en) * 2008-12-18 2011-10-11 Mosaid Technologies Incorporated Device and method for transferring data to a non-volatile memory device
US20110258366A1 (en) * 2010-04-19 2011-10-20 Mosaid Technologies Incorporated Status indication in a system having a plurality of memory devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4442504A (en) * 1981-03-09 1984-04-10 Allen-Bradley Company Modular programmable controller
CN101568903A (zh) * 2006-12-21 2009-10-28 英特尔公司 Nand闪存的基于命令的控制
US20090021992A1 (en) * 2007-07-18 2009-01-22 Hakjune Oh Memory with data control
WO2010027983A1 (en) * 2008-09-03 2010-03-11 Marvell World Trade Ltd. Progamming data into a multi-plane flash memory
US20100091536A1 (en) * 2008-10-14 2010-04-15 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107025926A (zh) * 2015-11-04 2017-08-08 三星电子株式会社 存储装置和操作存储装置的方法
CN107025926B (zh) * 2015-11-04 2021-05-04 三星电子株式会社 存储装置和操作存储装置的方法
CN107025069A (zh) * 2016-01-13 2017-08-08 桑迪士克科技有限责任公司 非易失性存储器的数据路径控制
CN107025069B (zh) * 2016-01-13 2021-09-28 桑迪士克科技有限责任公司 非易失性存储器的数据路径控制
TWI743736B (zh) * 2020-04-08 2021-10-21 瑞昱半導體股份有限公司 資料傳輸系統、電路與方法

Also Published As

Publication number Publication date
EP2567379A4 (en) 2014-01-22
JP5665974B2 (ja) 2015-02-04
WO2011137541A1 (en) 2011-11-10
EP2567379A1 (en) 2013-03-13
KR20130071436A (ko) 2013-06-28
CA2798868A1 (en) 2011-11-10
TW201209820A (en) 2012-03-01
US20110276775A1 (en) 2011-11-10
JP2013525924A (ja) 2013-06-20

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C06 Publication
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C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C53 Correction of patent of invention or patent application
CB02 Change of applicant information

Address after: Ontario, Canada

Applicant after: Examine Vincent Zhi Cai management company

Address before: Ontario, Canada

Applicant before: Mosaid Technologies Inc.

COR Change of bibliographic data

Free format text: CORRECT: APPLICANT; FROM: MOSAID TECHNOLOGIES INC. TO: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

ASS Succession or assignment of patent right

Owner name: NOVA CHIP CANANA COMPANY

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Effective date: 20150505

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Address after: Ontario, Canada

Applicant after: Nova chip Canada Company

Address before: Ontario, Canada

Applicant before: Examine Vincent Zhi Cai management company

C05 Deemed withdrawal (patent law before 1993)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130313