JP2021125228A5 - - Google Patents

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Publication number
JP2021125228A5
JP2021125228A5 JP2020192804A JP2020192804A JP2021125228A5 JP 2021125228 A5 JP2021125228 A5 JP 2021125228A5 JP 2020192804 A JP2020192804 A JP 2020192804A JP 2020192804 A JP2020192804 A JP 2020192804A JP 2021125228 A5 JP2021125228 A5 JP 2021125228A5
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JP
Japan
Prior art keywords
write
delay
memory
memory device
mode
Prior art date
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Pending
Application number
JP2020192804A
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English (en)
Japanese (ja)
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JP2021125228A (ja
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Publication date
Priority claimed from US16/780,632 external-priority patent/US11188264B2/en
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Publication of JP2021125228A publication Critical patent/JP2021125228A/ja
Publication of JP2021125228A5 publication Critical patent/JP2021125228A5/ja
Pending legal-status Critical Current

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JP2020192804A 2020-02-03 2020-11-19 不揮発性メモリにおける構成可能な書込みコマンド遅延 Pending JP2021125228A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/780,632 US11188264B2 (en) 2020-02-03 2020-02-03 Configurable write command delay in nonvolatile memory
US16/780,632 2020-02-03

Publications (2)

Publication Number Publication Date
JP2021125228A JP2021125228A (ja) 2021-08-30
JP2021125228A5 true JP2021125228A5 (https=) 2025-01-14

Family

ID=70849136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020192804A Pending JP2021125228A (ja) 2020-02-03 2020-11-19 不揮発性メモリにおける構成可能な書込みコマンド遅延

Country Status (4)

Country Link
US (1) US11188264B2 (https=)
EP (1) EP3859539A1 (https=)
JP (1) JP2021125228A (https=)
KR (1) KR20210098831A (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017058494A1 (en) * 2015-10-01 2017-04-06 Rambus Inc. Memory system with cached memory module operations
TWI784120B (zh) * 2019-01-17 2022-11-21 韓商愛思開海力士有限公司 用於儲存裝置之記憶體控制器、儲存裝置、儲存裝置之控制方法以及記錄媒體
US11379393B2 (en) * 2020-02-28 2022-07-05 Innogrit Technologies Co., Ltd. Multi-frequency memory interface and methods for configurating the same
US12086455B2 (en) * 2020-10-08 2024-09-10 Seagate Technology Llc Data storage system with workload-based asymmetry compensation
US11914532B2 (en) 2021-08-31 2024-02-27 Apple Inc. Memory device bandwidth optimization
CN114201113B (zh) * 2021-12-13 2023-06-02 建信金融科技有限责任公司 多对象存储桶的选择方法、装置及处理器
KR20240020596A (ko) * 2022-08-08 2024-02-15 삼성전자주식회사 입출력 호환성을 제공하는 불휘발성 메모리 장치 및 그것의 호환성 설정 방법
JP2024131386A (ja) 2023-03-16 2024-09-30 キオクシア株式会社 メモリシステム

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JPH09325909A (ja) * 1996-06-04 1997-12-16 Matsushita Electron Corp バス制御装置
US6088774A (en) * 1996-09-20 2000-07-11 Advanced Memory International, Inc. Read/write timing for maximum utilization of bidirectional read/write bus
JP2000137983A (ja) * 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
US6621496B1 (en) * 1999-02-26 2003-09-16 Micron Technology, Inc. Dual mode DDR SDRAM/SGRAM
US6788593B2 (en) * 2001-02-28 2004-09-07 Rambus, Inc. Asynchronous, high-bandwidth memory component using calibrated timing elements
US7340577B1 (en) * 2002-05-29 2008-03-04 Nvidia Corporation Method and system for efficiently executing reads after writes in a memory employing delayed write data
US7415723B2 (en) * 2002-06-11 2008-08-19 Pandya Ashish A Distributed network security system and a hardware processor therefor
US6938142B2 (en) * 2002-08-28 2005-08-30 Micron Technology, Inc. Multi-bank memory accesses using posted writes
JP2008140220A (ja) * 2006-12-04 2008-06-19 Nec Corp 半導体装置
US9665507B2 (en) * 2010-07-22 2017-05-30 Rambus Inc. Protocol including a command-specified timing reference signal
US9754648B2 (en) * 2012-10-26 2017-09-05 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9257175B2 (en) * 2013-09-26 2016-02-09 Intel Corporation Refresh of data stored in a cross-point non-volatile memory
US10381055B2 (en) * 2015-12-26 2019-08-13 Intel Corporation Flexible DLL (delay locked loop) calibration
US10090067B1 (en) * 2017-05-30 2018-10-02 Seagate Technology Llc Data storage device with rewritable in-place memory

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