JP2021125228A - 不揮発性メモリにおける構成可能な書込みコマンド遅延 - Google Patents

不揮発性メモリにおける構成可能な書込みコマンド遅延 Download PDF

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Publication number
JP2021125228A
JP2021125228A JP2020192804A JP2020192804A JP2021125228A JP 2021125228 A JP2021125228 A JP 2021125228A JP 2020192804 A JP2020192804 A JP 2020192804A JP 2020192804 A JP2020192804 A JP 2020192804A JP 2021125228 A JP2021125228 A JP 2021125228A
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Japan
Prior art keywords
memory
delay
write
memory device
mode
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JP2020192804A
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Japanese (ja)
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JP2021125228A5 (https=
Inventor
カワミ シェコウフェー
Qawami Shekoufeh
カワミ シェコウフェー
ヒリアー フィリップ
Hillier Philip
ヒリアー フィリップ
グラニエッロ ベンジャミン
Graniello Benjamin
グラニエッロ ベンジャミン
サンダラム ラジェシュ
Sundaram Rajesh
サンダラム ラジェシュ
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Intel Corp
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Intel Corp
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Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JP2021125228A publication Critical patent/JP2021125228A/ja
Publication of JP2021125228A5 publication Critical patent/JP2021125228A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
JP2020192804A 2020-02-03 2020-11-19 不揮発性メモリにおける構成可能な書込みコマンド遅延 Pending JP2021125228A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/780,632 US11188264B2 (en) 2020-02-03 2020-02-03 Configurable write command delay in nonvolatile memory
US16/780,632 2020-02-03

Publications (2)

Publication Number Publication Date
JP2021125228A true JP2021125228A (ja) 2021-08-30
JP2021125228A5 JP2021125228A5 (https=) 2025-01-14

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JP2020192804A Pending JP2021125228A (ja) 2020-02-03 2020-11-19 不揮発性メモリにおける構成可能な書込みコマンド遅延

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Country Link
US (1) US11188264B2 (https=)
EP (1) EP3859539A1 (https=)
JP (1) JP2021125228A (https=)
KR (1) KR20210098831A (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017058494A1 (en) * 2015-10-01 2017-04-06 Rambus Inc. Memory system with cached memory module operations
TWI784120B (zh) * 2019-01-17 2022-11-21 韓商愛思開海力士有限公司 用於儲存裝置之記憶體控制器、儲存裝置、儲存裝置之控制方法以及記錄媒體
US11379393B2 (en) * 2020-02-28 2022-07-05 Innogrit Technologies Co., Ltd. Multi-frequency memory interface and methods for configurating the same
US12086455B2 (en) * 2020-10-08 2024-09-10 Seagate Technology Llc Data storage system with workload-based asymmetry compensation
US11914532B2 (en) 2021-08-31 2024-02-27 Apple Inc. Memory device bandwidth optimization
CN114201113B (zh) * 2021-12-13 2023-06-02 建信金融科技有限责任公司 多对象存储桶的选择方法、装置及处理器
KR20240020596A (ko) * 2022-08-08 2024-02-15 삼성전자주식회사 입출력 호환성을 제공하는 불휘발성 메모리 장치 및 그것의 호환성 설정 방법
JP2024131386A (ja) 2023-03-16 2024-09-30 キオクシア株式会社 メモリシステム

Citations (7)

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Publication number Priority date Publication date Assignee Title
JPH09325909A (ja) * 1996-06-04 1997-12-16 Matsushita Electron Corp バス制御装置
JP2000137983A (ja) * 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
US6088774A (en) * 1996-09-20 2000-07-11 Advanced Memory International, Inc. Read/write timing for maximum utilization of bidirectional read/write bus
JP2008140220A (ja) * 2006-12-04 2008-06-19 Nec Corp 半導体装置
JP2015536503A (ja) * 2012-10-26 2015-12-21 マイクロン テクノロジー， インク． 可変レイテンシを有するメモリオペレーションのための装置及び方法
JP2016532236A (ja) * 2013-09-26 2016-10-13 インテル・コーポレーション クロスポイント不揮発性メモリに格納されたデータのリフレッシュ
JP2018206378A (ja) * 2017-05-30 2018-12-27 シーゲイト テクノロジー エルエルシーＳｅａｇａｔｅ Ｔｅｃｈｎｏｌｏｇｙ ＬＬＣ 書き換え可能なインプレースメモリを有するデータ記憶装置

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US6621496B1 (en) * 1999-02-26 2003-09-16 Micron Technology, Inc. Dual mode DDR SDRAM/SGRAM
US6788593B2 (en) * 2001-02-28 2004-09-07 Rambus, Inc. Asynchronous, high-bandwidth memory component using calibrated timing elements
US7340577B1 (en) * 2002-05-29 2008-03-04 Nvidia Corporation Method and system for efficiently executing reads after writes in a memory employing delayed write data
US7415723B2 (en) * 2002-06-11 2008-08-19 Pandya Ashish A Distributed network security system and a hardware processor therefor
US6938142B2 (en) * 2002-08-28 2005-08-30 Micron Technology, Inc. Multi-bank memory accesses using posted writes
US9665507B2 (en) * 2010-07-22 2017-05-30 Rambus Inc. Protocol including a command-specified timing reference signal
US10381055B2 (en) * 2015-12-26 2019-08-13 Intel Corporation Flexible DLL (delay locked loop) calibration

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09325909A (ja) * 1996-06-04 1997-12-16 Matsushita Electron Corp バス制御装置
US6088774A (en) * 1996-09-20 2000-07-11 Advanced Memory International, Inc. Read/write timing for maximum utilization of bidirectional read/write bus
JP2000137983A (ja) * 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
JP2008140220A (ja) * 2006-12-04 2008-06-19 Nec Corp 半導体装置
JP2015536503A (ja) * 2012-10-26 2015-12-21 マイクロン テクノロジー， インク． 可変レイテンシを有するメモリオペレーションのための装置及び方法
JP2016532236A (ja) * 2013-09-26 2016-10-13 インテル・コーポレーション クロスポイント不揮発性メモリに格納されたデータのリフレッシュ
JP2018206378A (ja) * 2017-05-30 2018-12-27 シーゲイト テクノロジー エルエルシーＳｅａｇａｔｅ Ｔｅｃｈｎｏｌｏｇｙ ＬＬＣ 書き換え可能なインプレースメモリを有するデータ記憶装置

Non-Patent Citations (1)

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Title
MOINUDDIN K. QURESHI ほか: ""Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing"", PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, JPN6025012564, pages 1 - 11, ISSN: 0005562040 *

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EP3859539A1 (en) 2021-08-04
US11188264B2 (en) 2021-11-30
US20200174705A1 (en) 2020-06-04
KR20210098831A (ko) 2021-08-11

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