KR20210098831A - 비휘발성 메모리에서의 구성가능한 기입 커맨드 지연 - Google Patents

비휘발성 메모리에서의 구성가능한 기입 커맨드 지연 Download PDF

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Publication number
KR20210098831A
KR20210098831A KR1020200164173A KR20200164173A KR20210098831A KR 20210098831 A KR20210098831 A KR 20210098831A KR 1020200164173 A KR1020200164173 A KR 1020200164173A KR 20200164173 A KR20200164173 A KR 20200164173A KR 20210098831 A KR20210098831 A KR 20210098831A
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South Korea
Prior art keywords
memory
delay
write
mode
command
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Pending
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KR1020200164173A
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English (en)
Korean (ko)
Inventor
쉬코우페흐 콰와미
필립 힐리어
벤자민 그라니엘로
라제쉬 선다람
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인텔 코포레이션
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Application filed by 인텔 코포레이션 filed Critical 인텔 코포레이션
Publication of KR20210098831A publication Critical patent/KR20210098831A/ko
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/32Timing circuits
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1689Synchronisation and timing concerns
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658Controller construction arrangements
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
KR1020200164173A 2020-02-03 2020-11-30 비휘발성 메모리에서의 구성가능한 기입 커맨드 지연 Pending KR20210098831A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/780,632 US11188264B2 (en) 2020-02-03 2020-02-03 Configurable write command delay in nonvolatile memory
US16/780,632 2020-02-03

Publications (1)

Publication Number Publication Date
KR20210098831A true KR20210098831A (ko) 2021-08-11

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KR1020200164173A Pending KR20210098831A (ko) 2020-02-03 2020-11-30 비휘발성 메모리에서의 구성가능한 기입 커맨드 지연

Country Status (4)

Country Link
US (1) US11188264B2 (https=)
EP (1) EP3859539A1 (https=)
JP (1) JP2021125228A (https=)
KR (1) KR20210098831A (https=)

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WO2017058494A1 (en) * 2015-10-01 2017-04-06 Rambus Inc. Memory system with cached memory module operations
TWI784120B (zh) * 2019-01-17 2022-11-21 韓商愛思開海力士有限公司 用於儲存裝置之記憶體控制器、儲存裝置、儲存裝置之控制方法以及記錄媒體
US11379393B2 (en) * 2020-02-28 2022-07-05 Innogrit Technologies Co., Ltd. Multi-frequency memory interface and methods for configurating the same
US12086455B2 (en) * 2020-10-08 2024-09-10 Seagate Technology Llc Data storage system with workload-based asymmetry compensation
US11914532B2 (en) 2021-08-31 2024-02-27 Apple Inc. Memory device bandwidth optimization
CN114201113B (zh) * 2021-12-13 2023-06-02 建信金融科技有限责任公司 多对象存储桶的选择方法、装置及处理器
KR20240020596A (ko) * 2022-08-08 2024-02-15 삼성전자주식회사 입출력 호환성을 제공하는 불휘발성 메모리 장치 및 그것의 호환성 설정 방법
JP2024131386A (ja) 2023-03-16 2024-09-30 キオクシア株式会社 メモリシステム

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JPH09325909A (ja) * 1996-06-04 1997-12-16 Matsushita Electron Corp バス制御装置
US6088774A (en) * 1996-09-20 2000-07-11 Advanced Memory International, Inc. Read/write timing for maximum utilization of bidirectional read/write bus
JP2000137983A (ja) * 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
US6621496B1 (en) * 1999-02-26 2003-09-16 Micron Technology, Inc. Dual mode DDR SDRAM/SGRAM
US6788593B2 (en) * 2001-02-28 2004-09-07 Rambus, Inc. Asynchronous, high-bandwidth memory component using calibrated timing elements
US7340577B1 (en) * 2002-05-29 2008-03-04 Nvidia Corporation Method and system for efficiently executing reads after writes in a memory employing delayed write data
US7415723B2 (en) * 2002-06-11 2008-08-19 Pandya Ashish A Distributed network security system and a hardware processor therefor
US6938142B2 (en) * 2002-08-28 2005-08-30 Micron Technology, Inc. Multi-bank memory accesses using posted writes
JP2008140220A (ja) * 2006-12-04 2008-06-19 Nec Corp 半導体装置
US9665507B2 (en) * 2010-07-22 2017-05-30 Rambus Inc. Protocol including a command-specified timing reference signal
US9754648B2 (en) * 2012-10-26 2017-09-05 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9257175B2 (en) * 2013-09-26 2016-02-09 Intel Corporation Refresh of data stored in a cross-point non-volatile memory
US10381055B2 (en) * 2015-12-26 2019-08-13 Intel Corporation Flexible DLL (delay locked loop) calibration
US10090067B1 (en) * 2017-05-30 2018-10-02 Seagate Technology Llc Data storage device with rewritable in-place memory

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Publication number Publication date
EP3859539A1 (en) 2021-08-04
US11188264B2 (en) 2021-11-30
US20200174705A1 (en) 2020-06-04
JP2021125228A (ja) 2021-08-30

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