WO2021159494A1 - 固态存储硬盘和固态存储硬盘的控制方法 - Google Patents

固态存储硬盘和固态存储硬盘的控制方法 Download PDF

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Publication number
WO2021159494A1
WO2021159494A1 PCT/CN2020/075345 CN2020075345W WO2021159494A1 WO 2021159494 A1 WO2021159494 A1 WO 2021159494A1 CN 2020075345 W CN2020075345 W CN 2020075345W WO 2021159494 A1 WO2021159494 A1 WO 2021159494A1
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WIPO (PCT)
Prior art keywords
selector
flash memory
nand flash
memory chips
chip
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PCT/CN2020/075345
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English (en)
French (fr)
Inventor
唐勇军
汤永科
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华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20918697.2A priority Critical patent/EP4095666A4/en
Priority to CN202080094787.6A priority patent/CN115004146A/zh
Priority to PCT/CN2020/075345 priority patent/WO2021159494A1/zh
Publication of WO2021159494A1 publication Critical patent/WO2021159494A1/zh
Priority to US17/886,720 priority patent/US20220391087A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of computer technology, in particular to a solid-state storage hard disk and a solid-state storage hard disk control method.
  • controlling the load rate of the input and output bus will reduce the capacity specification of the solid state storage hard disk; not controlling the load rate of the input and output bus will cause the interface rate of the solid state storage hard disk to be unable to increase, and the high interface of the solid state storage hard disk It is difficult to achieve both speed and high-capacity specifications at the same time.
  • the embodiment of the present application provides a solid-state storage hard disk and a method for controlling the solid-state storage hard disk, which are used to solve the technical problem that the existing solid-state storage hard disks have high interface rates and high-capacity specifications that are difficult to achieve at the same time.
  • this application provides a solid-state storage hard disk, including: a controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1, and the N NAND flash memory chips constitute an array of P NAND flash memory chips.
  • P is an integer greater than or equal to 1 and less than or equal to N;
  • the selector is respectively coupled with the controller and the N NAND flash memory chips;
  • the controller is used to output multiple strobe signals to the selector , Wherein the multiple strobe signals are used to indicate M NAND flash memory chips in the N NAND flash memory chips, and M is an integer greater than or equal to 1 and less than or equal to N; Two strobe signals to select the M NAND flash memory chips for data transmission.
  • controller Use the controller to output the strobe signal for indicating some NAND flash memory chips, and use the selector to select some NAND flash memory chips indicated by the strobe signal for data transmission, which effectively solves the problem of heavy load on the input and output bus of the solid state storage hard disk. It is helpful to increase the interface rate of solid-state storage hard disks, and at the same time, the storage capacity of solid-state storage hard disks is not limited. It has a wide range of applicability and can effectively solve the problems of large-capacity solid-state storage hard disks that the input and output buses are overloaded and the interface rate is reduced.
  • the selector includes a bus selector and a chip selector, the controller is respectively connected to the bus selector and the chip selector, and the bus selector is input and output through the P group
  • the bus is connected to the P NAND flash memory chip array, and the chip selector is connected to the N NAND flash memory chips; the bus selector is used to determine the P group of input and output buses according to each of the strobe signals
  • the chip selector is used to determine each NAND flash memory chip in the M NAND flash memory chips according to each of the strobe signals.
  • NAND flash memory chips are strobed for data transmission, which can effectively solve the problem of heavy load on the input and output bus of the solid state storage hard disk, which is beneficial to improve the performance of the solid state storage hard disk.
  • Interface speed The selection process of NAND flash memory chips does not require software participation, which can avoid increasing software complexity.
  • each strobe signal includes a first signal bit group and a second signal bit; the bus selector is used to receive the first signal bit group in each strobe signal, and According to the first signal bit group, a group of input and output buses in the P group of input and output buses is determined; the chip selector is used to receive the first signal bit group and the second signal bit group in each of the strobe signals , And determine each NAND flash memory chip in the M NAND flash memory chips according to the first signal bit group and the second signal bit group.
  • the bus selector selects the input and output bus according to the first signal bit group in the strobe signal
  • the chip selector selects the NAND flash memory chip according to the first signal bit group and the second signal bit group in the strobe signal.
  • the NAND flash memory chip connected to the input and output bus and the gated input and output bus effectively solves the problem of heavy load on the input and output bus of the large-capacity solid-state storage hard disk, which is beneficial to increase the interface rate of the large-capacity solid-state storage hard disk and increase the large capacity The data read and write speed of solid-state storage hard drives.
  • the NAND flash memory chip determined by the chip selector according to the first signal bit group and the second signal bit group of any strobe signal, and the bus selector according to the same strobe signal A group of input and output buses determined by the first signal bit group correspond to each other.
  • NAND flash memory chip selection process does not require software participation, and the software is complicated. It is low in speed and simple in implementation, and is suitable for various solid-state storage hard disks using NAND flash memory chips.
  • the bus selector includes a data selector MUX, and the chip selector includes a decoder.
  • the circuit implementation method is simple, the hardware cost is low, the applicability is wide, and it is suitable for various solid-state storage hard disks using NAND flash memory chips.
  • the selector is further used to: receive an enable signal sent by the controller; according to the enable signal, control whether the selector is enabled.
  • multiple chip selectors and multiple bus selectors may be set to complete the selection function of NAND flash memory chips.
  • the enable signal is used to control whether the selector is enabled, which is beneficial to ensure the effective selection of NAND flash memory chips. It can effectively ensure the normal operation of large-capacity solid-state storage hard drives.
  • the present application provides a controller for use in a solid-state storage hard disk.
  • the solid-state storage hard disk includes a selector and N NAND flash memory chips, where N is an integer greater than 1, and the N NAND flash memories
  • the chip constitutes an array of P NAND flash memory chips, where P is an integer greater than or equal to 1 and less than or equal to N;
  • the selector is respectively coupled with the controller and the N NAND flash memory chips;
  • the selector outputs a plurality of strobe signals for the selector to select M NAND flash memory chips for data transmission according to the plurality of strobe signals, wherein the plurality of strobe signals are used to indicate the N In the M NAND flash memory chips in the NAND flash memory chips, M is an integer greater than or equal to 1 and less than or equal to N.
  • the selector includes a bus selector and a chip selector, the controller is respectively connected to the bus selector and the chip selector, and the bus selector is input and output through the P group
  • the bus is connected to the P NAND flash memory chip array, and the chip selector is connected to the N NAND flash memory chips;
  • the controller is used to output a plurality of strobe signals to the bus selector for the bus
  • the selector determines a group of input and output buses in the P group of input and output buses according to each of the plurality of strobe signals; the controller is also used to output to the chip selector A plurality of strobe signals for the chip selector to determine each NAND flash memory chip of the M NAND flash memory chips according to each of the plurality of strobe signals.
  • each of the strobe signals includes a first signal bit group and a second signal bit group; the controller is used to output each of a plurality of strobe signals to the bus selector.
  • the first signal bit group of the pass signal is used for the bus selector to determine a group of input and output buses in the P group of input and output buses according to the first signal bit group of each strobe signal; the controller also
  • the first signal bit group and the second signal bit group of each of the multiple strobe signals are used to output to the chip selector for the chip selector according to the first signal bit group of each strobe signal.
  • the signal bit group and the second signal bit group determine each NAND flash memory chip in the M NAND flash memory chips.
  • the controller is also used to send an enable signal to the selector, and according to the enable signal, control whether the selector is enabled
  • the present application provides a method for controlling a solid-state storage hard disk.
  • the method is applied to a solid-state storage hard disk.
  • the solid-state storage hard disk includes a controller, a selector, and N NAND flash memory chips, where N is a positive value greater than 1.
  • the N NAND flash memory chips constitute P NAND flash memory chip arrays, and P is an integer greater than or equal to 1 and less than or equal to N;
  • the selector is coupled with the controller and the N NAND flash memory chips;
  • the method includes: the controller outputs a plurality of strobe signals to the selector, wherein the plurality of strobe signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, and M Is a positive integer greater than or equal to 1 and less than or equal to N; the selector selects the M NAND flash memory chips for data transmission according to the multiple strobe signals.
  • the selector includes a bus selector and a chip selector
  • the controller is respectively connected to the bus selector and the chip selector, and the bus selector is input and output through the P group
  • the bus is connected to the P NAND flash memory chip array, and the chip selector is connected to the N NAND flash memory chips;
  • P is a positive integer greater than or equal to 1;
  • the method includes: the bus selector according to each The strobe signal determines a group of input and output buses in the P group of input and output buses; the chip selector determines each NAND flash memory chip in the M NAND flash memory chips according to each of the strobe signals.
  • each of the strobe signals includes a first signal bit group and a second signal bit
  • the method includes: the bus selector receives the first signal in each of the strobe signals Bit group, and according to the first signal bit group, determine a group of input and output buses in the P group of input and output buses; the chip selector receives the first signal bit group and the second signal bit group in each of the strobe signals Signal bit group, and according to the first signal bit group and the second signal bit group, each NAND flash memory chip of the M NAND flash memory chips is determined.
  • the NAND flash memory chip determined by the chip selector according to the first signal bit group and the second signal bit group of any strobe signal, and the bus selector according to the same strobe signal A group of input and output buses determined by the first signal bit group correspond to each other.
  • the bus selector includes a data selector MUX, and the chip selector includes a decoder.
  • the method further includes: the selector receives an enable signal sent by the controller; and according to the enable signal, controlling whether the selector is enabled.
  • the present application provides a terminal device including the solid-state storage hard disk according to any one of the first aspect.
  • the present application provides a control system, the control system includes a terminal device and the solid-state storage hard disk described in any one of the first aspect; or, the control system includes a network device and the first aspect Any one of the solid-state storage hard disks.
  • the present application provides a computer-readable storage medium, including instructions, which when run on a computer, cause the computer to execute the method described in any one of the second aspect.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the application
  • Figure 2 is a schematic diagram of another application scenario provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a solid-state storage hard disk provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of another solid-state storage hard disk provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of yet another solid-state storage hard disk provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of control logic of a bus selector and a chip selector provided by an embodiment of the application;
  • FIG. 7 is a flowchart of a method for controlling a solid-state storage hard disk according to an embodiment of the application.
  • FIG. 8 is a flowchart of another solid-state storage hard disk control method provided by an embodiment of the application.
  • Fig. 9 is a schematic structural diagram of a control system provided by an embodiment of the application.
  • the embodiments of this application are applied to solid-state storage hard disks, or terminal devices, or control systems, or any system that can execute the embodiments of this application.
  • the following explains some terms in this application for the convenience of those skilled in the art understand. It should be noted that when the solution of the embodiment of the present application is applied to a solid-state storage hard disk, or any system that can execute the embodiments of the present application, the names of the solid-state storage hard disk and the NAND flash memory chip may change, but this does not affect Implementation of the embodiment scheme of this application.
  • wireless local area network systems
  • GSM global system of mobile communication
  • CDMA code division multiple access
  • WCDMA wideband code division multiple access
  • general packet radio service general packet radio service, GPRS
  • LTE Long term evolution
  • FDD frequency division duplex
  • TDD time division duplex
  • UMTS universal mobile telecommunication system
  • WiMAX Worldwide Interoperability for Microwave Access
  • 5G 5th Generation mobile communication technology
  • Solid state storage hard drives solid state drivers, SSDs
  • the solid state storage hard drives can be set on the terminal or the solid state storage hard drives can be set on the server.
  • Flash memory also known as Flash flash memory, abbreviated as "Flash”, which belongs to a kind of memory device and is a non-volatile memory.
  • Nand-Flash memory It is a kind of Flash memory, which adopts non-linear macro cell mode inside, has the advantages of large capacity and fast rewriting speed, and is suitable for large-scale data storage.
  • DRAM Dynamic Random Access Memory, dynamic random access memory, a volatile memory, data exists when the power is turned on, and data is lost when the power is turned off.
  • Interface rate the nominal value of the total bit rate passing through the interface after all processing is completed.
  • Multiple means two or more than two, and other quantifiers are similar.
  • “And/or” describes the association relationship of the associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone.
  • the character “/” generally indicates that the associated objects before and after are in an "or” relationship.
  • Correspondence can refer to an association relationship or binding relationship, and the correspondence between A and B means that there is an association relationship or binding relationship between A and B.
  • the interface rate of the solid-state storage hard disk When the load rate of the input and output bus exceeds a certain threshold, the interface rate of the solid-state storage hard disk will decrease, and the data read and write delay will increase.
  • the load rate of the input and output bus exceeds a certain threshold, the interface rate of the solid-state storage hard disk will decrease, and the data read and write delay will increase.
  • solid-state storage hard disks are used for large caches and secondary caches, for example, when they are specifically used as PCIe solid-state storage accelerator cards, high-performance accelerator cards, or PCIe flash memory cards, the storage capacity of the solid-state storage hard disk is increased, and the interface rate of the solid-state storage hard disk is guaranteed. It is an important factor to improve the overall performance of solid-state storage drives; when solid-state storage drives are mixed with traditional disks to form hierarchical storage, solid-state storage drives are also required to have large-capacity storage, high read and write capabilities, and low data latency.
  • controlling the load rate of the input and output bus will reduce the capacity specification of the solid state storage hard disk; not controlling the load rate of the input and output bus will cause the interface rate of the solid state storage hard disk to be unable to increase, and the high interface of the solid state storage hard disk Speed performance and high-capacity specification performance are difficult to achieve at the same time.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the application. As shown in FIG. 1, this embodiment is applicable to a solid-state storage hard disk (SSD).
  • SSD solid-state storage hard disk
  • FIG. 2 is a schematic diagram of another application scenario provided by an embodiment of the application. As shown in FIG. 2, this embodiment is suitable for a Nand-Flash memory with a control chip installed.
  • FIG. 3 is a schematic structural diagram of a solid-state storage hard disk provided by an embodiment of the application.
  • the solid-state storage hard disk includes: a controller 301, a selector 302, and N NAND flash memory chips 303, where N is greater than 1.
  • N NAND flash memory chips constitute P NAND flash memory chip arrays, P is an integer greater than or equal to 1, and less than or equal to N;
  • the selector 302 is coupled with the controller 301 and the N NAND flash memory chips 303;
  • the controller 301 is used for Output a plurality of strobe signals to the selector 302, where the plurality of strobe signals are used to indicate M NAND flash memory chips 303 among the N NAND flash memory chips 303, and M is an integer greater than or equal to 1, and less than or equal to N;
  • select The device 302 is used for selecting M NAND flash memory chips 303 for data transmission according to a plurality of strobe signals.
  • N NAND flash memory chips 303 are provided in the solid-state storage hard disk, where N is an integer greater than 1, and N NAND flash memory chips 303 constitute P NAND flash memories.
  • Chip array, P NAND flash memory chip arrays are connected to the selector 302 of the solid-state storage hard disk through the input and output bus, and the selector 302 is connected to the controller 301 of the solid-state storage hard disk through the input and output bus.
  • the N NAND flash memory chips 303 are grouped by channels.
  • Each group corresponds to multiple NAND flash memory chips 303, and the multiple NAND flash memory chips 303 corresponding to each group pass through the same input and output bus and the selector.
  • 302 is connected, and different NAND flash memory chips 303 corresponding to different groups are connected to the selector 302 through a parallel input and output bus. That is, the N NAND flash memory chips 303 are grouped by channels to obtain P NAND flash memory chip arrays.
  • Each NAND flash memory chip array is connected to the selector 302 through the same input and output bus, and different NAND flash memory chip arrays are connected to each other through parallel input and output buses.
  • the selector 302 is connected.
  • the amount of information exchanged between the data system and the solid-state storage hard disk is increasing, and the load rate of the input and output bus of the solid-state storage hard disk continues to increase.
  • the higher the load factor the more nodes on the input and output bus, the larger the distributed capacitance of the input and output bus, the more discharge time it takes for the dominant level to return to the invisible level, and the lower the input and output bus interface rate.
  • the utilization rate of the input and output buses does not exceed a certain threshold.
  • the controller 301 is used to output a plurality of strobe signals, the M NAND flash memory chips 303 are indicated in the N NAND flash memory chips 303 through the plurality of strobe signals, and the selector 302 is then used to select the indicated M NAND flash memory chips 303. data transmission.
  • the controller 301 is used to instruct a part of the NAND flash memory chips 303 among the plurality of NAND flash memory chips 303 of the solid-state storage hard disk. Specifically, the controller 301 outputs a plurality of strobe signals to the selector 302, and the plurality of strobe signals are used in N
  • the number of NAND flash memory chips 303 indicates M number of NAND flash memory chips 303.
  • the selector 302 sequentially selects the M NAND flash memory chips 303 indicated by the controller 301 among the N NAND flash memory chips 303 for data transmission according to each of the plurality of strobe signals.
  • the design of selector 302 realizes that part of the NAND flash memory chip 303 connected in the input and output bus is selected for data transmission through the hardware circuit method.
  • the interface rate of the solid-state storage hard disk guarantees the capacity specifications of the solid-state storage hard disk; on the other hand, there is no need to participate in the selection of the NAND flash memory chip 303 through software, the software complexity is low, and the implementation method is simple.
  • the solid-state storage hard disk includes: a controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1, and N NAND flash memory chips form an array of P NAND flash memory chips, and P is greater than or equal to 1, and less than An integer equal to N; the selector is respectively coupled with the controller and N NAND flash memory chips; the controller is used to output multiple strobe signals to the selector, wherein the multiple strobe signals are used to indicate the N NAND flash memory chips M NAND flash memory chips, M is an integer greater than or equal to 1 and less than or equal to N.
  • the controller is used to output a strobe signal for instructing part of the NAND flash memory chips, and the selector is used to select part of the NAND flash memory chips indicated by the controller for data transmission. Since the load rate of the input and output bus of the solid state storage hard disk is determined by the number of real-time gated NAND flash memory chips connected to the input and output bus, this solution divides the N NAND flash memory chips of the solid state storage hard disk into P NAND flash memory chip arrays , And output the strobe signal through the controller, select part of the NAND flash memory chips in the P NAND flash memory chip array for data transmission, reduce the number of real-time strobe NAND flash memory chips connected to the input and output bus, and effectively solve the large capacity
  • the problem of heavy load on the input and output bus of solid-state storage drives is conducive to effectively increasing the interface rate of large-capacity solid-state storage drives; compared to ensuring the interface rate of large-capacity solid-state storage drives, reducing the number of NAND flash memory chips loaded by the input
  • FIG. 4 is a schematic structural diagram of another solid-state storage hard disk provided by an embodiment of the application.
  • the solid-state storage hard disk includes: a controller 401, a selector, and N NAND flash memory chips 404, where N is greater than 1.
  • N NAND flash memory chips 404 constitute an array of P NAND flash memory chips; the selector is respectively coupled with the controller 401 and N NAND flash memory chips 404; the controller 401 is used to output multiple strobe signals to the selector, among which, Multiple strobe signals are used to indicate M NAND flash memory chips 404 among N NAND flash memory chips 404, M is an integer greater than or equal to 1 and less than or equal to N; the selector is used to select M NAND flash memory chips according to the multiple strobe signals
  • the flash memory chip 404 performs data transmission.
  • the selector includes a bus selector 402 and a chip selector 403.
  • the controller 401 is connected to the bus selector 402 and the chip selector 403, respectively.
  • the bus selector 402 is connected to the P group through the P input and output buses.
  • NAND flash memory chip array is connected, the chip selector 403 is connected with N NAND flash memory chips 404;
  • P is a positive integer greater than or equal to 1;
  • the bus selector 402 is used to determine the P group of input and output buses according to each strobe signal A set of input and output buses;
  • the chip selector 403 is used to determine each NAND flash memory chip 404 of the M NAND flash memory chips 404 according to each strobe signal.
  • the bus selector 402 is connected to the controller 401 through a group of input and output buses, and is connected to P NAND flash memory chip arrays through P group of input and output buses, and each NAND flash memory chip array is connected to the bus selector 402 through the same input and output bus.
  • the NAND flash memory chip array is connected to the bus selector 402 through a parallel input and output bus.
  • the bus selector 402 receives each strobe signal of the controller 401 through the input and output bus, and selects a group of input and output buses from the P group of input and output buses connected to the P NAND flash memory chip arrays according to each strobe signal, namely A NAND flash memory chip array is selected according to each strobe signal.
  • the chip selector 403 is connected to the controller 401 through a set of input and output buses. Specifically, the chip selector 403 and the bus selector 402 are connected to the controller 401 through the same set of input and output buses, and receive the controller through the same set of input and output buses. The same strobe signal of 401.
  • the chip selector 403 includes multiple output ports. Different output ports of the multiple output ports are respectively connected to different enable pins of the N NAND flash memory chips 404.
  • the chip selector 403 receives each selection of the controller 401 through the input and output bus. According to each strobe signal, one NAND flash memory chip 404 is selected from the N NAND flash memory chips 404 connected to it, and each NAND flash memory chip 404 of the M NAND flash memory chips 404 is finally determined.
  • the controller 401 is respectively connected to the bus selector 402 and the chip selector 403 through the input and output bus.
  • the controller 401 outputs a plurality of strobe signals to the bus selector 402 and the chip selector 403, and each of the plurality of strobe signals is selected.
  • the pass signal includes a first signal bit group and a second signal bit group.
  • the bus selector 402 receives the first signal bit group in each strobe signal through the input and output bus, and determines a group of input and output buses in the P group of input and output buses according to the first signal bit group in each strobe signal
  • the chip selector 403 receives the first signal bit group and the second signal bit group in each strobe signal through the input and output bus, and determines M NAND flash memory chips 404 according to the first signal bit group and the second signal bit group 404 in each NAND flash memory chip.
  • Each strobe signal output by the controller 401 through the input/output bus includes a first signal bit group and a second signal bit group, and the first signal bit group and the second signal bit group constitute a complete strobe signal.
  • the first signal bit group is 10
  • the second signal bit group is 1
  • the first signal bit group and the second signal bit group constitute a complete strobe signal 101.
  • the bus selector 402 receives the first signal bit group in each strobe signal through the input and output bus, and selects one group of input and output from the P group of input and output buses connected to the bus selector 402 according to the first signal bit group.
  • a selected group of input and output buses are correspondingly connected to a NAND flash memory chip array, and a NAND flash memory chip array may include multiple NAND flash memory chips 404.
  • the chip selector 403 receives the first signal bit group and the second signal bit group in each strobe signal through the input and output bus, and according to the first signal bit group and the second signal bit group in the N connected to the chip selector 403 Among the NAND flash memory chips 404, one of the NAND flash memory chips 404 is selected, and the chip selector 403 determines each NAND flash memory chip 404 of the M NAND flash memory chips 404 by receiving multiple strobe signals output by the controller 401.
  • the chip selector 403 Since the bus selector 402 receives a partial signal of any strobe signal, the chip selector 403 receives the complete signal of the same strobe signal. Therefore, the chip selector 403 is based on the first signal bit group of any strobe signal.
  • the NAND flash memory chip 404 determined by the second signal bit group corresponds to a group of input and output buses determined by the bus selector 402 according to the first signal bit group of the same strobe signal, that is, the chip selector 403 selects any
  • the NAND flash memory chip 404 determined by the complete signal of the communication signal is one of the NAND flash memory chip 404 in the NAND flash memory chip array connected to a group of input and output buses determined by the bus selector 402 according to the partial signal of the same strobe signal.
  • the bus selector 402 in the selector includes a data selector MUX
  • the chip selector 403 includes a decoder.
  • the data selector MUX can select any one of the data according to the needs in the process of multiplexing data transmission. It is also called a multiplexer or a multiplexer.
  • the bus selector 402 in the solid-state storage hard disk is 1:4MUX, 1:4MUX is connected to four NAND flash memory chip arrays through four sets of input and output buses, and 1:4MUX is based on the first strobe signal output by the controller 401
  • the chip selector 403 in the solid-state storage hard disk is a 3-8 decoder, and the eight output ports of the 3-8 decoder are respectively connected with
  • the enable pin of the NAND flash memory chip 404 is connected, and the 3-8 decoder decodes the first signal bit group and the second signal bit group of the received strobe signal, and outputs a low level at a certain output port,
  • the selection of the connected NAND flash memory chip 404 is realized.
  • the selector is also used to: receive the enable signal sent by the controller 401; according to the enable signal, control whether the selector is enabled.
  • the chip selector 403 and the bus selector 402 in the selector receive the same enable signal, and the enable signal can control whether the chip selector 403 and the bus selector 402 are enabled.
  • multiple chip selectors 403 and multiple bus selectors 402 may be provided to cooperate to complete the selection function of the NAND flash memory chip 404, and the enable signal can be used to control which selectors are activated to work.
  • This embodiment is also applicable to various memory components that use NAND flash memory chips to store programs and various data information, including but not limited to solid state storage hard drives SSD, Flash memory, Nand-Flash memory, mobile phones, memory boards, etc. .
  • the solid-state storage hard disk includes: a controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1, and N NAND flash memory chips constitute an array of P NAND flash memory chips, and P is greater than or equal to 1, and An integer less than or equal to N; the selector is respectively coupled with the controller and N NAND flash memory chips; the controller is used to output multiple strobe signals to the selector, wherein the multiple strobe signals are used to indicate the N NAND flash memory chips M NAND flash memory chips, M is an integer greater than or equal to 1, and less than or equal to N; the selector is used to select M NAND flash memory chips for data transmission according to multiple strobe signals, and the selector includes a bus selector and a chip selector , The controller is connected to the bus selector and the chip selector respectively, the bus selector is connected to N NAND flash memory chips through the P group of input and output buses, and the chip selector is connected to N NAND flash memory chips; P is a positive integer greater
  • the bus selector and chip selector are used to link NAND flash memory chips.
  • the NAND flash memory chip selection process does not require software participation, which can avoid increasing software complexity; NAND flash memory connected by switching the input and output bus and strobing the input and output bus.
  • the chip effectively solves the problem of the heavy load of the input and output bus of the large-capacity solid-state storage hard disk, effectively improves the interface speed of the large-capacity solid-state storage hard disk, and effectively improves the data read and write speed of the large-capacity solid-state storage hard disk;
  • the number of NAND flash memory chips in the hard disk is limited, and the storage capacity of the solid-state storage hard disk is not affected.
  • the coupling relationship between the interface speed and storage capacity of the solid-state storage hard disk is well balanced, and it can simultaneously meet the high interface speed and High storage capacity requirements; simple circuit implementation, low hardware cost, suitable for various solid-state storage hard drives using NAND flash memory chips.
  • FIG. 5 is a schematic structural diagram of another solid-state storage hard disk provided by an embodiment of the application.
  • the solid-state storage hard disk is a hard disk drive with NAND Flash semiconductor as the storage medium. Its biggest advantage is that it can provide hundreds of times higher than the mechanical hard disk HDD. Its main components include SSD controller 501, DRAM buffer, NAND Flash non-volatile storage device and power supply module.
  • SSD controller 501 In order to realize the large-capacity storage of solid-state storage hard disk SSD, a large number of NAND Flash non-volatile storage devices are usually used as the NAND flash memory chip 504 of the solid-state storage hard disk SSD.
  • the NAND flash memory chips 504 are grouped according to multiple channels to form multiple NAND flash memory chip arrays. .
  • the selector in the solid state storage hard disk SSD includes a bus selector and a chip selector.
  • the bus selector is 1:4MUX502, the chip selector is 3-8 decoder 503, and the SSD controller 501 is connected to the bus respectively.
  • the selector 1:4MUX502 is connected to the chip selector 3-8 decoder 503.
  • a channel grouping of a solid state storage hard disk SSD includes 8 NAND flash memory chips 504.
  • the enable pins of the 8 NAND flash memory chips 504 are CH0_CE0-CH0_CE7 respectively.
  • the 8 NAND flash memory chips form an array of 4 NAND flash memory chips, and the bus selector 1 : 4MUX502 is connected to 4 NAND flash memory chip arrays through 4 sets of input and output buses, and 8 output ports of chip selector 3-8 decoder 503 are respectively connected to the enable pins CH0_CE0-CH0_CE7 of 8 NAND flash memory chips 504.
  • the SSD controller 501 outputs a plurality of strobe signals to the bus selector 1:4MUX502 and the chip selector 3-8 decoder 503 through the input and output bus, and each strobe signal of the plurality of strobe signals includes the first signal bit Group CE0-CE1 and the second signal bit group CE2, the bus selector 1:4MUX502 receives the first signal bit group CE0-CE1 in each strobe signal as the channel selection signal SEL0-SEL1, where SEL0 is the same as CE0, and SEL1 is the same as CE0. CE1 is the same.
  • the chip selector 3-8 decoder 503 receives the first signal bit group CE0-CE1 and the second signal bit group CE2 in each strobe signal as the channel selection signal.
  • Bus selector 1: SEL0 and SEL1 in 4MUX502 are channel selection signals, 2-bit binary can be used to represent 4 states, and the 4 states respectively select 4 groups of input and output buses, that is, one group of input and output buses is selected through SEL0 and SEL1. .
  • the first signal bit group of each strobe signal received by the bus selector 1:4MUX502 includes 00, 01, 10, and 11, which realizes the selection of 4 groups of input and output buses by outputting 0, 1, 2, and 3.
  • CE0-CE2 are the channel selection signals (where CE0 is SEL0, CE1 is SEL1), 3-bit binary can be used to represent 8 states, and the 8 states respectively select 8 NAND flash memories
  • the enable pin of the chip 504 is to select a NAND flash memory chip 504 through CE0-CE2.
  • the first signal bit group of each strobe signal received by the chip selector 3-8 decoder 503 includes 00, 01, 10, and 11, and the second signal bit group includes 0 and 1, which pass through 8 output ports One output port outputs low level to realize the enable selection of 8 NAND flash memory chips 504.
  • FIG. 6 is a schematic diagram of the control logic of a bus selector and a chip selector provided by an embodiment of the application. Since the bus selector and the chip selector both receive the first signal bit group of each strobe signal, the input and output bus The selection is synchronized with the enable selection of the NAND flash memory chip 504.
  • the NAND flash memory chip 504 determined by the chip selector according to the first signal bit group and the second signal bit group of any strobe signal is selected according to the same selection as the bus selector.
  • the first signal bit group of the communication signal corresponds to a group of input and output buses.
  • the first signal bit group of the strobe signal is 01
  • the second signal bit group is 1
  • the bus selector 1:4MUX502 receives the first signal bit group 01 of the strobe signal, according to the first signal of the strobe signal Bit group 01 determines the input and output bus 1, that is, realizes the selection of the second input and output bus.
  • the chip selector 3-8 decoder 503 receives the first signal bit group 01 and the second signal bit group 1 of the strobe signal, and determines the output port according to the first signal bit group 01 and the second signal bit group 1 of the strobe signal 3 Output low level, corresponding to the enable pin of the NAND flash memory chip 5043 to be low level, which realizes the enable selection of the NAND flash memory chip 5043.
  • the NAND flash memory chip 5043 corresponds to the second input and output bus.
  • the SSD controller 501 is also used to control whether the selector is enabled by outputting an enable signal to the selector.
  • the enable signal MUX_EN# received by the bus selector 1:4MUX502 is used with the enable signal received by the chip selector 3-8 decoder 503.
  • the enable signal CE_EN# is the same enable signal, and the bus selector 1:4MUX502 and the chip selector 3-8 decoder 503 have the same enable state.
  • the solid-state storage hard disk SSD includes: an SSD controller, a selector, and N NAND flash memory chips, where N is an integer greater than 1; the selector is connected to the controller and the N NAND flash memory chips respectively; the controller is used to select The selector outputs multiple strobe signals, where the multiple strobe signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, and M is an integer greater than or equal to 1, and less than or equal to N; The strobe signal selects M NAND flash memory chips for data transmission.
  • the selector includes a bus selector and a chip selector. The controller is connected to the bus selector and the chip selector respectively. The bus selector is connected to N pieces of input and output buses through the P group.
  • the NAND flash memory chip is connected, and the chip selector is connected with N NAND flash memory chips; P is a positive integer greater than or equal to 1; the bus selector is used to determine a group of input and output buses in the P group of input and output buses according to each strobe signal; The chip selector is used to determine each NAND flash memory chip in the M NAND flash memory chips according to each strobe signal. The bus selector and chip selector are used to link NAND flash memory chips.
  • the gating method of NAND flash memory chips is convenient and the hardware cost is low.
  • the selection process of NAND flash memory chips does not require software participation, and the software complexity is low; through input and output Bus switching and strobing the NAND flash memory chip connected to the input and output bus effectively solves the problem of the high load rate of the input and output bus of the solid state storage hard disk SSD, effectively improves the interface rate of the solid state storage hard disk SSD, and effectively improves the solid state storage hard disk SSD
  • the data read and write speed can better balance the coupling relationship between the interface rate and storage capacity of the solid state storage hard disk SSD, and can meet the high interface rate and high storage capacity requirements of the solid state storage hard disk SSD at the same time; the circuit implementation method is simple and the hardware The cost is not high, which is conducive to controlling the hardware cost of the solid-state storage hard disk SSD.
  • FIG. 7 is a flowchart of a solid-state storage hard disk control method provided by an embodiment of the application. The method is applied to a solid-state storage hard disk.
  • the solid-state storage hard disk includes a controller, a selector, and N NAND flash memory chips, where N is a positive value greater than 1.
  • N NAND flash memory chips form an array of P NAND flash memory chips, and P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled with the controller and N NAND flash memory chips; as shown in Figure 7, this method include:
  • Step 701 The controller outputs multiple strobe signals to the selector, where the multiple strobe signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, and M is greater than or equal to 1, and less than or equal to N. Positive integer
  • Step 702 The selector selects M NAND flash memory chips for data transmission according to multiple strobe signals.
  • the method is applied to a solid-state storage hard disk.
  • the solid-state storage hard disk includes a controller, a selector, and N NAND flash memory chips, where N is a positive integer greater than 1, and N NAND flash memory chips form an array of P NAND flash memory chips.
  • P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled with the controller and N NAND flash memory chips; the method includes: the controller outputs multiple strobe signals to the selector, wherein the multiple strobe signals are used When indicating M NAND flash memory chips among the N NAND flash memory chips, M is a positive integer greater than or equal to 1 and less than or equal to N; the selector selects M NAND flash memory chips for data transmission according to a plurality of strobe signals.
  • FIG. 8 is a flowchart of another solid-state storage hard disk control method provided by an embodiment of the application.
  • the method is applied to a solid-state storage hard disk.
  • the solid-state storage hard disk includes a controller, a selector, and N NAND flash memory chips, where N is greater than 1.
  • N NAND flash memory chips constitute P NAND flash memory chip arrays, P is an integer greater than or equal to 1, and less than or equal to N;
  • the selector is coupled with the controller and N N NAND flash memory chips, and the bus selector is input through the P group
  • the output bus is connected to P NAND flash memory chip arrays, and the chip selector is connected to N NAND flash memory chips;
  • P is a positive integer greater than or equal to 1; as shown in Figure 8, the method includes:
  • Step 801 The controller outputs multiple strobe signals to the selector, where the multiple strobe signals are used to indicate M NAND flash memory chips among the N NAND flash memory chips, and M is greater than or equal to 1, and less than or equal to N. Positive integer
  • Step 802 The bus selector determines a group of input and output buses in the P group of input and output buses according to each strobe signal; the chip selector determines each of the M NAND flash memory chips according to each strobe signal.
  • each strobe signal includes a first signal bit group and a second signal bit.
  • the method further includes: the bus selector receives the first signal bit in each strobe signal According to the first signal bit group, determine a group of input and output buses in the P group of input and output buses; the chip selector receives the first signal bit group and the second signal bit group in each strobe signal, and according to the first signal bit group A signal bit group and a second signal bit group determine each NAND flash memory chip in the M NAND flash memory chips.
  • the NAND flash memory chip determined by the chip selector according to the first signal bit group and the second signal bit group of any strobe signal, and a group determined by the bus selector according to the first signal bit group of the same strobe signal Corresponding to the input and output bus.
  • the bus selector includes a data selector MUX, and the chip selector includes a decoder.
  • the method further includes: the selector receives an enable signal sent by the controller; and according to the enable signal, controlling whether the selector is activated.
  • the method is applied to a solid-state storage hard disk.
  • the solid-state storage hard disk includes a controller, a selector, and N NAND flash memory chips, where N is a positive integer greater than 1, and N NAND flash memory chips form an array of P NAND flash memory chips.
  • P is an integer greater than or equal to 1 and less than or equal to N; the selector is coupled with the controller and N NAND flash memory chips; the bus selector is connected to the P NAND flash memory chip array through the P group of input and output buses, and the chip selector is connected to N NAND flash memory chips are connected; P is a positive integer greater than or equal to 1; the method includes: the controller outputs multiple strobe signals to the selector, wherein the multiple strobe signals are used to indicate M in the N NAND flash memory chips.
  • a NAND flash memory chip M is a positive integer greater than or equal to 1, and less than or equal to N; the bus selector determines a group of input and output buses in the P group of input and output buses according to each strobe signal; the chip selector is based on each selection Through the signal, each NAND flash memory chip in the M NAND flash memory chips is determined.
  • the bus selector and chip selector are used to link NAND flash memory chips.
  • the NAND flash memory chip selection process does not require software participation, which can avoid increasing software complexity; NAND flash memory connected by switching the input and output bus and strobing the input and output bus
  • the chip effectively solves the problem of heavy load on the input and output bus of the large-capacity solid-state storage hard disk, effectively improves the interface rate of the large-capacity solid-state storage hard disk, and effectively improves the data read and write speed of the large-capacity solid-state storage hard disk;
  • the number of NAND flash memory chips in the hard disk is limited, and the storage capacity of the solid-state storage hard disk is not affected.
  • the coupling relationship between the interface speed and storage capacity of the solid-state storage hard disk is well balanced, and it can simultaneously meet the high interface speed and High storage capacity requirements; simple circuit implementation, low hardware cost, suitable for various solid-state storage hard disks that use storage media.
  • the embodiment of the present application also provides a controller, which is used in a solid-state storage hard disk.
  • the solid-state storage hard disk includes a selector and N NAND flash memory chips, where N is an integer greater than 1, and N NAND flash memory chips form an array of P NAND flash memory chips.
  • P is an integer greater than or equal to 1, and less than or equal to N;
  • the selector is respectively coupled with the controller and N NAND flash memory chips;
  • the controller is used to output multiple strobe signals to the selector for the selector to select according to multiple selections
  • the pass signal selects M NAND flash memory chips for data transmission, where multiple strobe signals are used to indicate M NAND flash memory chips in the N NAND flash memory chips, and M is an integer greater than or equal to 1 and less than or equal to N.
  • the selector includes a bus selector and a chip selector.
  • the controller is connected to the bus selector and the chip selector respectively.
  • the bus selector is connected to the P arrays of NAND flash memory chips through the P group of input and output buses.
  • the selector is connected with N NAND flash memory chips;
  • the controller is used to output multiple strobe signals to the bus selector, so that the bus selector determines a group of input and output buses in the P group of input and output buses according to each of the multiple strobe signals;
  • the controller is also used to output multiple strobe signals to the chip selector, so that the chip selector determines each NAND flash memory chip in the M NAND flash memory chips according to each of the multiple strobe signals.
  • each strobe signal includes a first signal bit group and a second signal bit group
  • the controller is used to output the first signal bit group of each of the multiple strobe signals to the bus selector, so that the bus selector determines the P group input and output according to the first signal bit group of each strobe signal A set of input and output buses in the bus;
  • the controller is also used to output the first signal bit group and the second signal bit group of each strobe signal of the plurality of strobe signals to the chip selector, so that the chip selector can respond to the first signal of each strobe signal
  • the bit group and the second signal bit group determine each NAND flash memory chip in the M NAND flash memory chips.
  • the controller is also used to send an enable signal to the selector, and according to the enable signal, control whether the selector is enabled.
  • the present application also provides a terminal device, and the terminal device includes the solid-state storage hard disk described in Embodiment 3 and Embodiment 4.
  • FIG. 9 is a schematic structural diagram of a control system provided by an embodiment of this application.
  • the control system includes a network device 901 and a solid-state storage hard disk 902.
  • the solid-state storage hard disk 902 includes the solid-state storage hard disk described in any of the previous embodiments. .
  • the present application also provides an electronic device and a readable storage medium.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data solid-state storage hard disk such as a server or data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).
  • the functions described in the embodiments of the present application may be implemented by hardware, software, firmware, or any combination thereof. When implemented by software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on the computer-readable medium.
  • the computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another.
  • the storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
  • the above-mentioned embodiments can refer to each other and learn from each other, and the same or similar steps and nouns will not be repeated one by one.

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Abstract

一种固态存储硬盘和固态存储硬盘控制方法，其中，固态存储硬盘包括控制器、选择器以及N个NAND闪存芯片，N为大于1的整数，N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；选择器分别与控制器以及N个NAND闪存芯片相耦合；控制器用于向选择器输出多个选通信号，其中，多个选通信号用于指示N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的整数（701）；选择器用于根据多个选通信号，选择M个NAND闪存芯片进行数据传输（702）。有利于提升固态存储硬盘的接口速率，同时未对固态存储硬盘的存储容量进行限制，能够同时满足固态存储硬盘的高接口速率和高存储容量的性能要求。

Description

固态存储硬盘和固态存储硬盘的控制方法 技术领域
本申请涉及计算机技术领域，尤其是一种固态存储硬盘和固态存储硬盘的控制方法。
背景技术
自全面进入互联网时代，数据数量呈现指数级爆炸性增长，这对固态存储硬盘的容量规格要求和接口速率要求越来越高。为了实现较高的容量规格，固态存储硬盘中设置有大量的NAND闪存芯片，大量的NAND闪存芯片按照多个通道分组，每个分组对应的多个NAND闪存芯片通过同一输入输出总线与固态存储硬盘的控制器连接。然而，随着同一输入输出总线连接的NAND闪存芯片的数量的增加，输入输出总线的负载率也在不断提高。输入输出总线的负载率超过一定阈值时，会导致固态存储硬盘的接口速率减小，数据读写延时增大。
相关技术中，为了提升固态存储硬盘的接口速率，降低数据读写延迟，需要减少输入输出总线连接的NAND闪存芯片的数量，控制输入输出总线的负载率。
然而，对输入输出总线的负载率加以控制，会导致固态存储硬盘的容量规格降低；不对输入输出总线的负载率加以控制，会导致固态存储硬盘的接口速率无法得以提升，固态存储硬盘的高接口速率和高容量规格难以同时实现。
发明内容
本申请实施例提供一种固态存储硬盘和固态存储硬盘的控制方法，用于解决现有固态存储硬盘存在的高接口速率和高容量规格难以同时实现的技术问题。
第一方面，本申请提供了一种固态存储硬盘，包括：控制器、选择器以及N个NAND闪存芯片，N为大于1的整数，所述N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；所述选择器分别与所述控制器以及所述N个NAND闪存芯片相耦合；所述控制器用于向所述选择器输出多个选通信号，其中，所述多个选通信号用于指示所述N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的整数；所述选择器用于根据所述多个选通信号，选择所述M个NAND闪存芯片进行数据传输。
利用控制器输出用于指示部分NAND闪存芯片的选通信号，利用选择器选择选通信号指示出的部分NAND闪存芯片进行数据传输，有效解决了固态存储硬盘的输入输出总线负载重的问题，有利于提升固态存储硬盘的接口速率，同时未对固态存储硬盘的存储容量进行限制，适用性广泛，能够有效解决大容量固态存储硬盘存在的输入输出总线负载过重、接口速率降低的问题。
在一种可能的设计中，所述选择器包括总线选择器和芯片选择器，所述控制器分别与所述总线选择器、所述芯片选择器连接，所述总线选择器通过P组输入输出总线与所述P个NAND闪存芯片阵列连接，所述芯片选择器与所述N个NAND闪存芯片连接；所述总 线选择器用于根据每一所述选通信号，确定所述P组输入输出总线中的一组输入输出总；所述芯片选择器用于根据每一所述选通信号，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
利用总线选择器和芯片选择器根据控制器输出的选通信号，选通部分NAND闪存芯片进行数据传输，能够有效解决固态存储硬盘的输入输出总线负载过重的问题，有利于提升固态存储硬盘的接口速率；NAND闪存芯片的选通过程不需要软件参与，能够避免增加软件复杂度。
在一种可能的设计中，每一所述选通信号包括第一信号位组和第二信号位；所述总线选择器用于接收每一所述选通信号中的第一信号位组，并根据第一信号位组，确定所述P组输入输出总线中的一组输入输出总线；所述芯片选择器用于接收每一所述选通信号中的第一信号位组和第二信号位组，并根据第一信号位组和第二信号位组，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
总线选择器根据选通信号中的第一信号位组进行输入输出总线的选择，芯片选择器根据选通信号中的第一信号位组和第二信号位组进行NAND闪存芯片的选择，通过切换输入输出总线和选通输入输出总线连接的NAND闪存芯片，有效解决了大容量固态存储硬盘的输入输出总线负载过重的问题，有利于提升大容量固态存储硬盘的接口速率，有利于提高大容量固态存储硬盘的数据读写速度。
在一种可能的设计中，所述芯片选择器根据任一选通信号的第一信号位组和第二信号位组确定出的NAND闪存芯片，与所述总线选择器根据同一选通信号的第一信号位组确定出的一组输入输出总线相对应。
利用总线选择器和芯片选择器联动进行NAND闪存芯片的选通，除能够有效提升固态存储硬盘的接口速率，保证固态存储硬盘的存储容量外，NAND闪存芯片选通过程不需要软件参与，软件复杂度低，实现方式简单，适用于各种采用NAND闪存芯片的固态存储硬盘。
在一种可能的设计中，所述总线选择器包括数据选择器MUX，所述芯片选择器包括译码器。
电路实现方式简单，硬件成本低，适用性广泛，适用于各种采用NAND闪存芯片的固态存储硬盘。
在一种可能的设计中，所述选择器还用于：接收所述控制器发送的使能信号；根据所述使能信号，控制所述选择器是否被启用。
在大容量固态存储硬盘中，可能设置有多个芯片选择器和多个总线选择器配合完成NAND闪存芯片的选择功能，通过使能信号控制选择器是否启用，有利于保证NAND闪存芯片的有效选通，能够有效保证大容量固态存储硬盘的正常工作。
第二方面，本申请提供了一种控制器，所述控制器用于固态存储硬盘，所述固态存储硬盘包括选择器以及N个NAND闪存芯片，N为大于1的整数，所述N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；所述选择器分别与所述控制器以及所述N个NAND闪存芯片相耦合；所述控制器用于向所述选择器输出多个选通信号，以供所述选择器根据所述多个选通信号，选择M个NAND闪存芯片进行数据传输，其中，所述多个选通信号用于指示所述N个NAND闪存芯片中的所述M个 NAND闪存芯片，M为大于等于1、且小于等于N的整数。
在一种可能的设计中，所述选择器包括总线选择器和芯片选择器，所述控制器分别与所述总线选择器、所述芯片选择器连接，所述总线选择器通过P组输入输出总线与所述P个NAND闪存芯片阵列连接，所述芯片选择器与所述N个NAND闪存芯片连接；所述控制器用于向所述总线选择器输出多个选通信号，以供所述总线选择器根据所述多个选通信号中的每一所述选通信号，确定所述P组输入输出总线中的一组输入输出总线；所述控制器还用于向所述芯片选择器输出多个选通信号，以供所述芯片选择器根据所述多个选通信号中的每一所述选通信号，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
在一种可能的设计中，每一所述选通信号包括第一信号位组和第二信号位组；所述控制器用于向所述总线选择器输出多个选通信号中的每一选通信号的第一信号位组，以供所述总线选择器根据每一选通信号的第一信号位组，确定所述P组输入输出总线中的一组输入输出总线；所述控制器还用于向所述芯片选择器输出多个选通信号中的每一选通信号的第一信号位组和第二信号位组，以供所述芯片选择器根据每一选通信号的第一信号位组和第二信号位组，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
在一种可能的设计中，所述控制器还用于向所述选择器发送使能信号，并根据所述使能信号，控制所述选择器是否被启用
第三方面，本申请提供了一种固态存储硬盘的控制方法，所述方法应用于固态存储硬盘，所述固态存储硬盘包括控制器、选择器以及N个NAND闪存芯片，N为大于1的正整数，所述N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；所述选择器与所述控制器、所述N个NAND闪存芯片相耦合；所述方法包括：所述控制器向所述选择器输出多个选通信号，其中，所述多个选通信号用于指示出所述N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的正整数；所述选择器根据所述多个选通信号，选择所述M个NAND闪存芯片进行数据传输。
在一种可能的设计中，所述选择器包括总线选择器和芯片选择器，所述控制器分别与所述总线选择器、所述芯片选择器连接，所述总线选择器通过P组输入输出总线与所述P个NAND闪存芯片阵列连接，所述芯片选择器与所述N个NAND闪存芯片连接；P为大于等于1的正整数；所述方法包括：所述总线选择器根据每一所述选通信号，确定所述P组输入输出总线中的一组输入输出总线；所述芯片选择器根据每一所述选通信号，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
在一种可能的设计中，每一所述选通信号包括第一信号位组和第二信号位，所述方法包括：所述总线选择器接收每一所述选通信号中的第一信号位组，并根据第一信号位组，确定所述P组输入输出总线中的一组输入输出总线；所述芯片选择器接收每一所述选通信号中的第一信号位组和第二信号位组，并根据第一信号位组和第二信号位组，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
在一种可能的设计中，所述芯片选择器根据任一选通信号的第一信号位组和第二信号位组确定出的NAND闪存芯片，与所述总线选择器根据同一选通信号的第一信号位组确定出的一组输入输出总线相对应。
在一种可能的设计中，所述总线选择器包括数据选择器MUX，所述芯片选择器包括译 码器。
在一种可能的设计中，所述方法还包括：所述选择器接收所述控制器发送的使能信号；并根据所述使能信号，控制所述选择器是否被启用。
第四方面，本申请提供一种终端设备，所述终端设备中包括第一方面中任一项所述的固态存储硬盘。
第五方面，本申请提供一种控制系统，所述控制系统中包括终端设备和第一方面中任一项所述的固态存储硬盘；或者，所述控制系统中包括网络设备和第一方面中任一项所述的固态存储硬盘。
第六方面，本申请提供了一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行第二方面中任一项所述的方法。
上述可选方式所具有的其他效果将在下文中结合具体实施例加以说明。
附图说明
附图用于更好地理解本方案，不构成对本申请的限定。其中：
图1为本申请实施例提供的一种应用场景示意图；
图2为本申请实施例提供的另一种应用场景示意图；
图3为本申请实施例提供的一种固态存储硬盘的结构示意图；
图4为本申请实施例提供的另一种固态存储硬盘的结构示意图；
图5为本申请实施例提供的再一种固态存储硬盘的结构示意图；
图6为本申请实施例提供的一种总线选择器与芯片选择器的控制逻辑示意图；
图7为本申请实施例提供的一种固态存储硬盘控制方法的流程图；
图8为本申请实施例提供的另一种固态存储硬盘控制方法的流程图；
图9为本申请实施例提供的一种控制系统的结构示意图。
具体实施方式
本申请实施例应用于固态存储硬盘中、或者终端设备中、或者控制系统中、或者可以执行本申请实施例的任意系统中，以下对本申请中的部分用语进行解释说明，以便于本领域技术人员理解。需要说明的是，当本申请实施例的方案应用于固态存储硬盘中、或者可以执行本申请实施例的任意系统中时，固态存储硬盘和NAND闪存芯片的名称可能发生变化，但这并不影响本申请实施例方案的实施。
应理解，本申请实施例的技术方案可以对应用于各种通信系统的固态存储硬盘进行处理，其中，通信系统例如：无线局域网通信(wireless local area network，WLAN)系统，全球移动通信(global system of mobile communication，GSM)系统、码分多址(code division multiple access，CDMA)系统、宽带码分多址(wideband code division multiple access，WCDMA)系统、通用分组无线业务(general packet radio service，GPRS)、长期演进(long term evolution，LTE)系统、LTE频分双工(frequency division duplex，FDD)系统、LTE时分双工(time division duplex，TDD)、通用移动通信系统(universal mobile telecommunication system，UMTS)、全球互联微波接入(worldwide interoperability for  microwave access，WiMAX)通信系统、以及未来的第五代移动通信技术(the 5th Generation mobile communication technology，5G)系统或未来可能出现的其他系统。
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。以下对本申请中的部分用语进行解释说明，以便于本领域技术人员理解。
1)固态存储硬盘(solid state drivers，SSD)，用于存储数据；可以将固态存储硬盘设置在终端上，也可以将固态存储硬盘设置在服务器上。
2)Flash存储器：又称Flash闪存，简称为"Flash"，属于内存器件的一种，是一种非易失性(Non-volatile)内存。
3)Nand-Flash存储器：是Flash存储器的一种，其内部采用非线性宏单元模式，具有容量较大，改写速度快等优点，适用于大规模数据的存储。
4)DRAM：Dynamic Random Access Memory，动态随机存取存储器，一种易失性存储器，电源开启时数据存在，电源关闭时数据流失。
5)接口速率：完成所有处理之后通过接口的总比特速率标称值。
6)“多个”是指两个或两个以上，其它量词与之类似。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
7)“对应”可以指的是一种关联关系或绑定关系，A与B相对应指的是A与B之间是一种关联关系或绑定关系。
需要指出的是，本申请实施例中涉及的名词或术语可以相互参考，不再赘述。
自全面进入互联网时代，数据量呈现指数级爆炸性增长，这对固态存储硬盘的容量规格要求和接口速率要求越来越高。为了实现较高的容量规格，固态存储硬盘中设置有大量的NAND闪存芯片，大量的NAND闪存芯片按照多个通道分组，每个分组对应的多个NAND闪存芯片通过同一输入输出总线与固态存储硬盘的控制器连接。然而，随着同一输入输出总线连接的NAND闪存芯片的数量的增加，输入输出总线的负载率也在不断提高。输入输出总线的负载率超过一定阈值时，会导致固态存储硬盘的接口速率减小，数据读写延时增大。相关技术中，为了提升固态存储硬盘的接口速率，降低数据读写延迟，需要减少输入输出总线连接的NAND闪存芯片的数量，控制输入输出总线的负载率。
当固态存储硬盘用于大缓存和二级缓存时，例如具体用作PCIe固态存储加速卡、高性能加速卡或PCIe闪存卡时，提高固态存储硬盘的存储容量，保证固态存储硬盘的接口速率，是提高固态存储硬盘整体性能的重要因素；当固态存储硬盘与传统盘混插构成分级存储时，同样要求固态存储硬盘具有大容量存储、高读写能力、低数据延迟的性能。然而，对输入输出总线的负载率加以控制，会导致固态存储硬盘的容量规格降低；不对输入输出总线的负载率加以控制，会导致固态存储硬盘的接口速率无法得以提升，固态存储硬盘的高接口速率性能和高容量规格性能难以同时实现。
本申请针对以上问题提出解决方案。下面将结合附图，对本申请实施例的技术方案进行描述。
图1为本申请实施例提供的一种应用场景示意图，如图1所示，本实施例适用于固态存储硬盘SSD。
图2为本申请实施例提供的另一种应用场景示意图，如图2所示，本实施例适用于安装有控制芯片的Nand-Flash存储器。
图3为本申请实施例提供的一种固态存储硬盘的结构示意图，如图3所示，该固态存储硬盘包括：控制器301、选择器302以及N个NAND闪存芯片303，N为大于1的整数，N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；选择器302与控制器301、N个NAND闪存芯片303相耦合；控制器301用于向选择器302输出多个选通信号，其中，多个选通信号用于指示N个NAND闪存芯片303中的M个NAND闪存芯片303，M为大于等于1、且小于等于N的整数；选择器302用于根据多个选通信号，选择M个NAND闪存芯片303进行数据传输。
在本实施例中，具体的，为实现固态存储硬盘的大容量存储，固态存储硬盘中设置有N个NAND闪存芯片303,N为大于1的整数，N个NAND闪存芯片303构成P个NAND闪存芯片阵列，P个NAND闪存芯片阵列通过输入输出总线连接固态存储硬盘的选择器302，选择器302通过输入输出总线连接固态存储硬盘的控制器301。根据连接的输入输出总线不同，对N个NAND闪存芯片303进行通道分组，每个分组对应多个NAND闪存芯片303，且每个分组对应的多个NAND闪存芯片303通过同一输入输出总线与选择器302连接，不同分组对应的不同NAND闪存芯片303通过并行的输入输出总线与选择器302连接。即，对N个NAND闪存芯片303进行通道分组，得到P个NAND闪存芯片阵列，每个NAND闪存芯片阵列通过同一输入输出总线与选择器302连接，不同NAND闪存芯片阵列通过并行的输入输出总线与选择器302连接。随着固态存储硬盘性能及安全等级的不断提高，数据系统与固态存储硬盘交互的信息量越来越大，固态存储硬盘输入输出总线的负载率不断提高。负载率越高，输入输出总线的节点越多，输入输出总线的分布电容越大，显性电平回到隐形电平需要的放电时间越多，输入输出总线接口速率减小。为保证数据传输延迟在可接受范围内，输入输出总线的利用率不超过一定阈值。输入输出总线负载率越低，输入输出总线的实时性越能保证，但输入输出总线的负载率过低，无法传输足够的数据。因此，利用控制器301输出多个选通信号，通过多个选通信号在N个NAND闪存芯片303中指示M个NAND闪存芯片303，然后利用选择器302选择指示的M个NAND闪存芯片303进行数据传输。
控制器301用于在固态存储硬盘的多个NAND闪存芯片303中指示部分NAND闪存芯片303，具体的，控制器301向选择器302输出多个选通信号，多个选通信号用于在N个NAND闪存芯片303中指示M个NAND闪存芯片303。选择器302依次根据多个选通信号中的每一选通信号，在N个NAND闪存芯片303中选择控制器301指示的M个NAND闪存芯片303进行数据传输。选择器302的设计实现了通过硬件电路方式，选择输入输出总线中连接的部分NAND闪存芯片303进行数据传输，一方面，有效减小了固态存储硬盘的输入输出总线的负载率，有利于在保证固态存储硬盘接口速率的同时，保证固态存储硬盘的容量规格；另一方面，不需要通过软件参与NAND闪存芯片303的选择，软件复杂度低，实现方式简单。
本实施例中，固态存储硬盘包括：控制器、选择器以及N个NAND闪存芯片，N为大于1的整数，N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；选择器分别与控制器以及N个NAND闪存芯片相耦合；控制器用于向选择器 输出多个选通信号，其中，多个选通信号用于指示N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的整数。利用控制器输出用于指示部分NAND闪存芯片的选通信号，利用选择器选择控制器指示出的部分NAND闪存芯片进行数据传输。由于固态存储硬盘的输入输出总线的负载率，由输入输出总线所连接的实时选通的NAND闪存芯片数量决定，本方案通过将固态存储硬盘的N个NAND闪存芯片划分为P个NAND闪存芯片阵列，并通过控制器输出选通信号，在P个NAND闪存芯片阵列中选择部分NAND闪存芯片进行数据传输，减小了输入输出总线所连接的实时选通的NAND闪存芯片数量，有效解决了大容量固态存储硬盘的输入输出总线负载重的问题，有利于有效提升大容量固态存储硬盘的接口速率；相比于为保证大容量固态存储硬盘的接口速率，减少输入输出总线负载的NAND闪存芯片数量的方式，本技术方案能够有效保证固态存储硬盘的容量规格；通过硬件电路方式实现NAND闪存芯片的选择，不需要利用软件参与进行NAND闪存芯片选择，能够避免增加软件复杂度，电路实现方式简单。
图4为本申请实施例提供的另一种固态存储硬盘的结构示意图，如图4所示，该固态存储硬盘包括：控制器401、选择器以及N个NAND闪存芯片404，N为大于1的整数，N个NAND闪存芯片404构成P个NAND闪存芯片阵列；选择器分别与控制器401、N个NAND闪存芯片404相耦合；控制器401用于向选择器输出多个选通信号，其中，多个选通信号用于指示N个NAND闪存芯片404中的M个NAND闪存芯片404，M为大于等于1、且小于等于N的整数；选择器用于根据多个选通信号，选择M个NAND闪存芯片404进行数据传输。
在本实施例中，具体的，选择器包括总线选择器402和芯片选择器403，控制器401分别与总线选择器402、芯片选择器403连接，总线选择器402通过P组输入输出总线与P个NAND闪存芯片阵列连接，芯片选择器403与N个NAND闪存芯片404连接；P为大于等于1的正整数；总线选择器402用于根据每一选通信号，确定P组输入输出总线中的一组输入输出总线；芯片选择器403用于根据每一选通信号，确定M个NAND闪存芯片404中每一NAND闪存芯片404。
总线选择器402通过一组输入输出总线与控制器401连接，通过P组输入输出总线与P个NAND闪存芯片阵列连接，每一NAND闪存芯片阵列通过同一输入输出总线与总线选择器402连接，不同NAND闪存芯片阵列通过并行的输入输出总线与总线选择器402连接。总线选择器402通过输入输出总线接收控制器401的每一选通信号，并根据每一选通信号在与P个NAND闪存芯片阵列连接的P组输入输出总线中选择一组输入输出总线，即根据每一选通信号选择一个NAND闪存芯片阵列。芯片选择器403通过一组输入输出总线与控制器401连接，具体的，芯片选择器403与总线选择器402通过同一组输入输出总线与控制器401连接，并通过同一组输入输出总线接收控制器401的同一选通信号。芯片选择器403包括多个输出端口，多个输出端口的不同输出端口分别与N个NAND闪存芯片404的不同使能管脚连接，芯片选择器403通过输入输出总线接收控制器401的每一选通信号，并根据每一选通信号在与其连接的N个NAND闪存芯片404中选择一个NAND闪存芯片404，最终确定出M个NAND闪存芯片404中每一NAND闪存芯片404。
控制器401通过输入输出总线分别与总线选择器402、芯片选择器403连接，控制器 401向总线选择器402和芯片选择器403输出多个选通信号，多个选通信号中的每一选通信号包括第一信号位组和第二信号位组。总线选择器402通过输入输出总线接收每一选通信号中的第一信号位组，并根据每一选通信号中的第一信号位组，确定P组输入输出总线中的一组输入输出总线；芯片选择器403通过输入输出总线接收每一选通信号中的第一信号位组和第二信号位组，并根据第一信号位组和第二信号位组，确定M个NAND闪存芯片404中每一NAND闪存芯片404。
控制器401通过输入输出总线输出的每一选通信号包括第一信号位组和第二信号位组，第一信号位组和第二信号位组构成了完整的选通信号。示例性的，第一信号位组为10，第二信号位组为1，第一信号位组和第二信号位组构成了完整的选通信号101。总线选择器402通过输入输出总线接收每一选通信号中的第一信号位组，并根据第一信号位组在与总线选择器402连接的P组输入输出总线中，选择其中一组输入输出总线，选择出的一组输入输出总线对应连接一个NAND闪存芯片阵列，一个NAND闪存芯片阵列中可能包括多个NAND闪存芯片404。芯片选择器403通过输入输出总线接收每一选通信号中的第一信号位组和第二信号位组，并根据第一信号位组和第二信号位组在与芯片选择器403连接的N个NAND闪存芯片404中，选择其中一个NAND闪存芯片404，芯片选择器403通过接收控制器401输出的多个选通信号，实现确定M个NAND闪存芯片404中每一NAND闪存芯片404。由于总线选择器402接收的是任一选通信号的部分信号，芯片选择器403接收的是同一选通信号的完整信号，因此，芯片选择器403根据任一选通信号的第一信号位组和第二信号位组确定出的NAND闪存芯片404，与总线选择器402根据同一选通信号的第一信号位组确定出的一组输入输出总线相对应，即芯片选择器403根据任一选通信号的完整信号确定出的NAND闪存芯片404，是总线选择器402根据同一选通信号的部分信号确定出的一组输入输出总线所连接的NAND闪存芯片阵列中的其中一个NAND闪存芯片404。
具体的，选择器中的总线选择器402包括数据选择器MUX，芯片选择器403包括译码器。数据选择器MUX能够在多路数据传送过程中，根据需要将其中任意一路数据选择出来，也被称为多路选择器或多路开关。示例性的，固态存储硬盘中的总线选择器402为1:4MUX，1:4MUX通过四组输入输出总线与4个NAND闪存芯片阵列连接，1:4MUX根据控制器401输出的选通信号的第一信号位组，在四组输入输出总线中选择其中一组输入输出总线；固态存储硬盘中的芯片选择器403为3-8译码器，3-8译码器的八个输出端口分别与NAND闪存芯片404的使能管脚连接，3-8译码器对接收的选通信号的第一信号位组和第二信号位组进行译码，通过在某一输出端口输出低电平，实现对连接的NAND闪存芯片404的选择。
可选的，选择器还用于：接收控制器401发送的使能信号；根据使能信号，控制选择器是否被启用。选择器中的芯片选择器403和总线选择器402接收同一使能信号，使能信号能够控制芯片选择器403和总线选择器402是否被启用。在大容量固态存储硬盘中，可能设置有多个芯片选择器403和多个总线选择器402配合完成NAND闪存芯片404的选择功能，利用使能信号能够控制启动哪些选择器进行工作。
本实施例还适用于于各种采用NAND闪存芯片的用于存储程序和各种数据信息的记忆部件，包括但不限于固态存储硬盘SSD、Flash存储器、Nand-Flash存储器、手机、存 储板卡等。
本实施例中，该固态存储硬盘包括：控制器、选择器以及N个NAND闪存芯片，N为大于1的整数，N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；选择器分别与控制器以及N个NAND闪存芯片相耦合；控制器用于向选择器输出多个选通信号，其中，多个选通信号用于指示N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的整数；选择器用于根据多个选通信号，选择M个NAND闪存芯片进行数据传输，选择器包括总线选择器和芯片选择器，控制器分别与总线选择器、芯片选择器连接，总线选择器通过P组输入输出总线与N个NAND闪存芯片连接，芯片选择器与N个NAND闪存芯片连接；P为大于等于1的正整数；总线选择器用于根据每一选通信号，确定P组输入输出总线中的一组输入输出总线；芯片选择器用于根据每一选通信号，确定M个NAND闪存芯片中每一NAND闪存芯片。利用总线选择器和芯片选择器联动进行NAND闪存芯片的选通，NAND闪存芯片选通过程不需要软件参与，能够避免增加软件复杂度；通过切换输入输出总线和选通输入输出总线连接的NAND闪存芯片，有效解决了大容量固态存储硬盘的输入输出总线负载较重的问题，有效提升了大容量固态存储硬盘的接口速率，有效提高了大容量固态存储硬盘的数据读写速度；未对固态存储硬盘的NAND闪存芯片数量进行限制，固态存储硬盘的存储容量不受影响，很好地平衡了固态存储硬盘的接口速率与存储容量之间的耦合关系，能够同时满足固态存储硬盘的高接口速率和高存储容量要求；电路实现方式简单，硬件成本不高，适用于各种采用NAND闪存芯片的固态存储硬盘。
图5为本申请实施例提供的再一种固态存储硬盘的结构示意图，固态存储硬盘是以NAND Flash半导体为存储介质的一种硬盘驱动器，其最大优势在于可以提供高于机械硬盘HDD数百倍的读写功能，其主要部件包括SSD控制器501、DRAM缓存器、NAND Flash非易失存储器件及电源模块。为实现固态存储硬盘SSD的大容量存储，通常采用大量的NAND Flash非易失存储器件作为固态存储硬盘SSD的NAND闪存芯片504，NAND闪存芯片504按照多个通道分组，构成多个NAND闪存芯片阵列。
如图5所示，固态存储硬盘SSD中的选择器包括总线选择器和芯片选择器，总线选择器为1:4MUX502，芯片选择器为3-8译码器503，SSD控制器501分别与总线选择器1:4MUX502和芯片选择器3-8译码器503连接。固态存储硬盘SSD的一个通道分组包括8个NAND闪存芯片504，8个NAND闪存芯片504的使能管脚分别为CH0_CE0-CH0_CE7，8个NAND闪存芯片构成4个NAND闪存芯片阵列，总线选择器1:4MUX502通过4组输入输出总线与4个NAND闪存芯片阵列连接，芯片选择器3-8译码器503的8个输出端口分别与8个NAND闪存芯片504的使能管脚CH0_CE0-CH0_CE7连接。
SSD控制器501通过输入输出总线向总线选择器1:4MUX502和芯片选择器3-8译码器503输出多个选通信号，多个选通信号中的每一选通信号包括第一信号位组CE0-CE1和第二信号位组CE2，总线选择器1:4MUX502接收每一选通信号中的第一信号位组CE0-CE1作为通道选择信号SEL0-SEL1，其中SEL0与CE0相同，SEL1与CE1相同。芯片选择器3-8译码器503接收每一选通信号中的第一信号位组CE0-CE1和第二信号位组CE2作为通道选择信号。
总线选择器1:4MUX502中SEL0和SEL1是通道选择信号，2位二进制可用于表示4个状态，4个状态分别对应选择4组输入输出总线，即通过SEL0、SEL1选通其中一组输入输出总线。总线选择器1:4MUX502接收的每一选通信号的第一信号位组包括00、01、10、11，其通过输出0、1、2、3实现对4组输入输出总线的选择。
芯片选择器3-8译码器503中CE0-CE2是通道选择信号(其中，CE0即SEL0，CE1即SEL1)，3位二进制可用于表示8个状态，8个状态分别对应选择8个NAND闪存芯片504的使能管脚，即通过CE0-CE2选通一个NAND闪存芯片504。芯片选择器3-8译码器503接收的每一选通信号的第一信号位组包括00、01、10、11，第二信号位组包括0、1，其通过在8个输出端口中的一个输出端口输出低电平，实现对8个NAND闪存芯片504的使能选择。
图6为本申请实施例提供的一种总线选择器与芯片选择器的控制逻辑示意图，由于总线选择器与芯片选择器均接收每一选通信号的第一信号位组，因此输入输出总线的选择和NAND闪存芯片504的使能选择是同步的，芯片选择器根据任一选通信号的第一信号位组和第二信号位组确定出的NAND闪存芯片504，与总线选择器根据同一选通信号的第一信号位组确定出的一组输入输出总线相对应。示例性的，选通信号的第一信号位组为01，第二信号位组为1，总线选择器1:4MUX502接收选通信号的第一信号位组01，根据选通信号的第一信号位组01确定出输入输出总线1，即实现对第2个输入输出总线的选择。芯片选择器3-8译码器503接收选通信号的第一信号位组01和第二信号位组1，根据选通信号的第一信号位组01和第二信号位组1确定输出端口3输出低电平，对应NAND闪存芯片5043的使能管脚为低电平，实现了对NAND闪存芯片5043的使能选择，NAND闪存芯片5043与第2个输入输出总线相对应。
SSD控制器501还通过向选择器输出使能信号，用于控制是否启用选择器，总线选择器1:4MUX502接收的使能信号MUX_EN#，与芯片选择器3-8译码器503接收的使能信号CE_EN#是同一使能信号，总线选择器1:4MUX502和芯片选择器3-8译码器503具有相同的使能状态。
本实施例中，固态存储硬盘SSD包括：SSD控制器、选择器以及N个NAND闪存芯片，N为大于1的整数；选择器分别与控制器、N个NAND闪存芯片连接；控制器用于向选择器输出多个选通信号，其中，多个选通信号用于指示N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的整数；选择器用于根据多个选通信号，选择M个NAND闪存芯片进行数据传输，选择器包括总线选择器和芯片选择器，控制器分别与总线选择器、芯片选择器连接，总线选择器通过P组输入输出总线与N个NAND闪存芯片连接，芯片选择器与N个NAND闪存芯片连接；P为大于等于1的正整数；总线选择器用于根据每一选通信号，确定P组输入输出总线中的一组输入输出总线；芯片选择器用于根据每一选通信号，确定M个NAND闪存芯片中每一NAND闪存芯片。利用总线选择器和芯片选择器联动进行NAND闪存芯片的选通，NAND闪存芯片的选通方式便捷，硬件成本低，NAND闪存芯片的选通过程不需要软件参与，软件复杂度低；通过输入输出总线切换和选通输入输出总线连接的NAND闪存芯片，有效解决了固态存储硬盘SSD的输入输出总线负载率过高的问题，有效提升了固态存储硬盘SSD的接口速率，有效提高了固态存储硬盘SSD的数据读写速度，能够较好地平衡固态存储硬盘SSD的接 口速率与存储容量之间的耦合关系，能够同时满足固态存储硬盘SSD的高接口速率和高存储容量要求；电路实现方式简单，硬件成本不高，有利于控制固态存储硬盘SSD的硬件成本。
图7为本申请实施例提供的一种固态存储硬盘控制方法的流程图，该方法应用于固态存储硬盘，固态存储硬盘包括控制器、选择器以及N个NAND闪存芯片，N为大于1的正整数，N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；选择器与控制器、N个NAND闪存芯片相耦合；如图7所示，该方法包括：
步骤701、控制器向选择器输出多个选通信号，其中，多个选通信号用于指示出N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的正整数；
步骤702、选择器根据多个选通信号，选择M个NAND闪存芯片进行数据传输。
本实施例中，该方法应用于固态存储硬盘，固态存储硬盘包括控制器、选择器以及N个NAND闪存芯片，N为大于1的正整数，N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；选择器与控制器、N个NAND闪存芯片相耦合；方法包括：控制器向选择器输出多个选通信号，其中，多个选通信号用于指示出N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的正整数；选择器根据多个选通信号，选择M个NAND闪存芯片进行数据传输。利用控制器输出用于指示部分NAND闪存芯片的选通信号，利用选择器选择控制器指示出的部分NAND闪存芯片进行数据传输，有效解决了大容量固态存储硬盘的输入输出总线负载重的问题，有利于有效提升大容量固态存储硬盘的接口速率；相比于为保证大容量固态存储硬盘的接口速率，减少输入输出总线负载的NAND闪存芯片数量的方式，本技术方案能够有效保证固态存储硬盘的容量规格；通过硬件电路方式实现NAND闪存芯片的选择，不需要利用软件参与进行NAND闪存芯片选择，能够避免增加软件复杂度，电路实现方式简单。
图8为本申请实施例提供的另一种固态存储硬盘控制方法的流程图，该方法应用于固态存储硬盘，固态存储硬盘包括控制器、选择器以及N个NAND闪存芯片，N为大于1的正整数，N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；选择器与控制器、N个NAND闪存芯片相耦合，总线选择器通过P组输入输出总线与P个NAND闪存芯片阵列连接，芯片选择器与N个NAND闪存芯片连接；P为大于等于1的正整数；如图8所示，该方法包括：
步骤801、控制器向选择器输出多个选通信号，其中，多个选通信号用于指示出N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的正整数；
步骤802、总线选择器根据每一选通信号，确定P组输入输出总线中的一组输入输出总线；芯片选择器根据每一选通信号，确定M个NAND闪存芯片中每一NAND闪存芯片。
在本实施例中，具体的，每一选通信号包括第一信号位组和第二信号位，可选的，本方法还包括：总线选择器接收每一选通信号中的第一信号位组，并根据第一信号位组，确定P组输入输出总线中的一组输入输出总线；芯片选择器接收每一选通信号中的第一信号位组和第二信号位组，并根据第一信号位组和第二信号位组，确定M个NAND闪存芯片中每一NAND闪存芯片。其中，芯片选择器根据任一选通信号的第一信号位组和第二信 号位组确定出的NAND闪存芯片，与总线选择器根据同一选通信号的第一信号位组确定出的一组输入输出总线相对应。
作为一种可选方式，总线选择器包括数据选择器MUX，芯片选择器包括译码器。
可选的，本方法还包括：选择器接收控制器发送的使能信号；并根据使能信号，控制选择器是否启动。
本实施例中，该方法应用于固态存储硬盘，固态存储硬盘包括控制器、选择器以及N个NAND闪存芯片，N为大于1的正整数，N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；选择器与控制器、N个NAND闪存芯片相耦合；总线选择器通过P组输入输出总线与P个NAND闪存芯片阵列连接，芯片选择器与N个NAND闪存芯片连接；P为大于等于1的正整数；该方法包括：控制器向选择器输出多个选通信号，其中，多个选通信号用于指示出N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的正整数；总线选择器根据每一选通信号，确定P组输入输出总线中的一组输入输出总线；芯片选择器根据每一选通信号，确定M个NAND闪存芯片中每一NAND闪存芯片。利用总线选择器和芯片选择器联动进行NAND闪存芯片的选通，NAND闪存芯片选通过程不需要软件参与，能够避免增加软件复杂度；通过切换输入输出总线和选通输入输出总线连接的NAND闪存芯片，有效解决了大容量固态存储硬盘的输入输出总线负载较重的问题，有效提升了大容量固态存储硬盘的接口速率，有效提高了大容量固态存储硬盘的数据读写速度；未对固态存储硬盘的NAND闪存芯片数量进行限制，固态存储硬盘的存储容量不受影响，很好地平衡了固态存储硬盘的接口速率与存储容量之间的耦合关系，能够同时满足固态存储硬盘的高接口速率和高存储容量要求；电路实现方式简单，硬件成本不高，适用于各种采用存储介质的固态存储硬盘。
本申请实施例还提供一种控制器，控制器用于固态存储硬盘，固态存储硬盘包括选择器以及N个NAND闪存芯片，N为大于1的整数，N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；选择器分别与控制器以及N个NAND闪存芯片相耦合；控制器用于向选择器输出多个选通信号，以供选择器根据多个选通信号，选择M个NAND闪存芯片进行数据传输，其中，多个选通信号用于指示N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的整数。
作为一种可选方式，选择器包括总线选择器和芯片选择器，控制器分别与总线选择器、芯片选择器连接，总线选择器通过P组输入输出总线与P个NAND闪存芯片阵列连接，芯片选择器与N个NAND闪存芯片连接；
控制器用于向总线选择器输出多个选通信号，以供总线选择器根据多个选通信号中的每一选通信号，确定P组输入输出总线中的一组输入输出总线；
控制器还用于向芯片选择器输出多个选通信号，以供芯片选择器根据多个选通信号中的每一选通信号，确定M个NAND闪存芯片中每一NAND闪存芯片。
作为一种可选方式，每一选通信号包括第一信号位组和第二信号位组；
控制器用于向总线选择器输出多个选通信号中的每一选通信号的第一信号位组，以供总线选择器根据每一选通信号的第一信号位组，确定P组输入输出总线中的一组输入输出总线；
控制器还用于向芯片选择器输出多个选通信号中的每一选通信号的第一信号位组和第二信号位组，以供芯片选择器根据每一选通信号的第一信号位组和第二信号位组，确定M个NAND闪存芯片中每一NAND闪存芯片。
作为一种可选方式，控制器还用于向选择器发送使能信号，并根据使能信号，控制选择器是否被启用。
根据本申请的实施例，本申请还提供了一种终端设备，终端设备中包括实施例3和实施例4中描述的固态存储硬盘。
图9为本申请实施例提供的一种控制系统的结构示意图，如图9所示，控制系统中包括网络设备901和固态存储硬盘902，固态存储硬盘902包括前任一实施例描述的固态存储硬盘。
根据本申请的实施例，本申请还提供了一种电子设备和一种可读存储介质。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如，同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如，红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据固态存储硬盘。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如，固态硬盘(solid state disk，SSD))等。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请实施例所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
在本申请实施例中，上述各实施例之间可以相互参考和借鉴，相同或相似的步骤以及名词均不再一一赘述。
应该理解，可以使用上面所示的各种形式的流程，重新排序、增加或删除步骤。例如，本发申请中记载的各步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本申请公开的技术方案所期望的结果，本文在此不进行限制。
上述具体实施方式，并不构成对本申请保护范围的限制。本领域技术人员应该明白的是，根据设计要求和其他因素，可以进行各种修改、组合、子组合和替代。任何在本申请的精神和原则之内所作的修改、等同替换和改进等，均应包含在本申请保护范围之内。

Claims (19)

  1. 一种固态存储硬盘，其特征在于，包括：
    控制器、选择器以及N个NAND闪存芯片，N为大于1的整数，所述N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；
    所述选择器分别与所述控制器以及所述N个NAND闪存芯片相耦合；
    所述控制器用于向所述选择器输出多个选通信号，其中，所述多个选通信号用于指示所述N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的整数；
    所述选择器用于根据所述多个选通信号，选择所述M个NAND闪存芯片进行数据传输。
  2. 根据权利要求1所述的固态存储硬盘，其特征在于，所述选择器包括总线选择器和芯片选择器，所述控制器分别与所述总线选择器、所述芯片选择器连接，所述总线选择器通过P组输入输出总线与所述P个NAND闪存芯片阵列连接，所述芯片选择器与所述N个NAND闪存芯片连接；
    所述总线选择器用于根据每一所述选通信号，确定所述P组输入输出总线中的一组输入输出总线；
    所述芯片选择器用于根据每一所述选通信号，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
  3. 根据权利要求2所述的固态存储硬盘，其特征在于，每一所述选通信号包括第一信号位组和第二信号位组；
    所述总线选择器用于接收每一所述选通信号中的第一信号位组，并根据第一信号位组，确定所述P组输入输出总线中的一组输入输出总线；
    所述芯片选择器用于接收每一所述选通信号中的第一信号位组和第二信号位组，并根据第一信号位组和第二信号位组，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
  4. 根据权利要求3所述的固态存储硬盘，其特征在于，所述芯片选择器根据任一选通信号的第一信号位组和第二信号位组确定出的NAND闪存芯片，与所述总线选择器根据同一选通信号的第一信号位组确定出的一组输入输出总线相对应。
  5. 根据权利要求1-4任一项的固态存储硬盘，其特征在于，所述总线选择器包括数据选择器MUX，所述芯片选择器包括译码器。
  6. 根据权利要求1-5任一项所述的固态存储硬盘，其特征在于，所述选择器还用于：
    接收所述控制器发送的使能信号；
    根据所述使能信号，控制所述选择器是否被启用。
  7. 一种控制器，其特征在于，所述控制器用于固态存储硬盘，所述固态存储硬盘包括选择器以及N个NAND闪存芯片，N为大于1的整数，所述N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；
    所述选择器分别与所述控制器以及所述N个NAND闪存芯片相耦合；
    所述控制器用于向所述选择器输出多个选通信号，以供所述选择器根据所述多个选通 信号，选择M个NAND闪存芯片进行数据传输，其中，所述多个选通信号用于指示所述N个NAND闪存芯片中的所述M个NAND闪存芯片，M为大于等于1、且小于等于N的整数。
  8. 根据权利要求7所述的控制器，其特征在于，所述选择器包括总线选择器和芯片选择器，所述控制器分别与所述总线选择器、所述芯片选择器连接，所述总线选择器通过P组输入输出总线与所述P个NAND闪存芯片阵列连接，所述芯片选择器与所述N个NAND闪存芯片连接；
    所述控制器用于向所述总线选择器输出多个选通信号，以供所述总线选择器根据所述多个选通信号中的每一所述选通信号，确定所述P组输入输出总线中的一组输入输出总线；
    所述控制器还用于向所述芯片选择器输出多个选通信号，以供所述芯片选择器根据所述多个选通信号中的每一所述选通信号，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
  9. 根据权利要求8所述的控制器，其特征在于，每一所述选通信号包括第一信号位组和第二信号位组；
    所述控制器用于向所述总线选择器输出多个选通信号中的每一选通信号的第一信号位组，以供所述总线选择器根据每一选通信号的第一信号位组，确定所述P组输入输出总线中的一组输入输出总线；
    所述控制器还用于向所述芯片选择器输出多个选通信号中的每一选通信号的第一信号位组和第二信号位组，以供所述芯片选择器根据每一选通信号的第一信号位组和第二信号位组，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
  10. 根据权利要求7-9任一项所述的控制器，其特征在于，所述控制器还用于向所述选择器发送使能信号，并根据所述使能信号，控制所述选择器是否被启用。
  11. 一种固态存储硬盘的控制方法，其特征在于，所述方法应用于固态存储硬盘，所述固态存储硬盘包括控制器、选择器以及N个NAND闪存芯片，N为大于1的正整数，所述N个NAND闪存芯片构P个NAND闪存芯片阵列，P为大于等于1、且小于等于N的整数；所述选择器与所述控制器、所述N个NAND闪存芯片相耦合；所述方法包括：
    所述控制器向所述选择器输出多个选通信号，其中，所述多个选通信号用于指示出所述N个NAND闪存芯片中的M个NAND闪存芯片，M为大于等于1、且小于等于N的正整数；
    所述选择器根据所述多个选通信号，选择所述M个NAND闪存芯片进行数据传输。
  12. 根据权利要求11所述的方法，其特征在于，所述选择器包括总线选择器和芯片选择器，所述控制器分别与所述总线选择器、所述芯片选择器连接，所述总线选择器通过P组输入输出总线与所述P个NAND闪存芯片阵列连接，所述芯片选择器与所述N个NAND闪存芯片连接；所述方法包括：
    所述总线选择器根据每一所述选通信号，确定所述P组输入输出总线中的一组输入输出总线；
    所述芯片选择器根据每一所述选通信号，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
  13. 根据权利要求12所述的方法，其特征在于，每一所述选通信号包括第一信号位 组和第二信号位组，所述方法包括：
    所述总线选择器接收每一所述选通信号中的第一信号位组，并根据第一信号位组，确定所述P组输入输出总线中的一组输入输出总线；
    所述芯片选择器接收每一所述选通信号中的第一信号位组和第二信号位组，并根据第一信号位组和第二信号位组，确定所述M个NAND闪存芯片中每一NAND闪存芯片。
  14. 根据权利要求13所述的方法，其特征在于，所述芯片选择器根据任一选通信号的第一信号位组和第二信号位组确定出的NAND闪存芯片，与所述总线选择器根据同一选通信号的第一信号位组确定出的一组输入输出总线相对应。
  15. 根据权利要求11-14任一项的方法，其特征在于，所述总线选择器包括数据选择器MUX，所述芯片选择器包括译码器。
  16. 根据权利要求11-15任一项所述的方法，其特征在于，所述方法还包括：
    所述选择器接收所述控制器发送的使能信号；
    并根据所述使能信号，控制所述选择器是否被启用。
  17. 一种终端设备，其特征在于，所述终端设备中包括如权利要求1-6任一项所述固态存储硬盘。
  18. 一种控制系统，其特征在于，所述控制系统中包括终端设备和如权利要求1-6任一项所述固态存储硬盘；或者，所述控制系统中包括网络设备和如权利要求1-6任一项所述固态存储硬盘。
  19. 一种计算机可读存储介质，其特征在于，包括指令，当其在计算机上运行时，使得计算机执行如权利要求11-16任一项所述的方法。
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