WO2023020484A1 - 基于龙芯处理器的存储主板 - Google Patents

基于龙芯处理器的存储主板 Download PDF

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Publication number
WO2023020484A1
WO2023020484A1 PCT/CN2022/112758 CN2022112758W WO2023020484A1 WO 2023020484 A1 WO2023020484 A1 WO 2023020484A1 CN 2022112758 W CN2022112758 W CN 2022112758W WO 2023020484 A1 WO2023020484 A1 WO 2023020484A1
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Prior art keywords
power supply
capacitor
output interface
chip
controller
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PCT/CN2022/112758
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English (en)
French (fr)
Inventor
李修录
尹善腾
朱小聪
吴健全
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深圳市安信达存储技术有限公司
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Publication of WO2023020484A1 publication Critical patent/WO2023020484A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Definitions

  • the embodiment of the utility model relates to the technical field of chips, in particular to a storage motherboard based on a Godson processor.
  • the storage disk of the existing Godson processor is usually integrated with PCIe transmission data differential pin pairs for data storage, but the number of PCIe transmission data differential pin pairs integrated in the storage disk of the existing Godson processor is limited, resulting in Some storage disks of Godson processors cannot meet the needs of large-capacity storage and fast storage of data in the information age.
  • the embodiment of the present invention provides a storage motherboard based on the Loongson processor, which is used to solve the problems of small storage capacity and low storage efficiency of the storage disk of the existing Loongson processor.
  • the utility model also provides a storage motherboard based on the Loongson processor, comprising:
  • the bridge chip is connected to the Godson processor through the HT3.0 interface;
  • the board is attached to the Godson processor, and the embedded memory chip is connected to the bridge;
  • the embedded memory chip includes a controller, flash memory and cache, and the controller is connected to the flash memory and the The cache; the embedded memory chip is used to store the data to be processed transmitted by the Godson processor.
  • the embedded memory chip is provided with four sets of first PCIe transmission data differential pin pairs;
  • the bridge is provided with four sets of second differential pin pairs for PCIe transmission data
  • the four sets of second PCIe transmission data differential pin pairs are respectively corresponding to the four first PCIe transmission data differential pin pairs, and the four second PCIe transmission data differential pin pairs are respectively corresponding to the corresponding first PCIe transmission data differential pin pairs.
  • the embedded memory chip further includes a bus controller, and the controller is connected to the bus controller;
  • Described flashing memory comprises Flash controller and Flash flash memory chip array; Described Flash controller is connected with described Flash flash memory chip array and described bus controller respectively;
  • the cache includes a DRAM controller and a DDR3 DRAM storage array; the DRAM controller is connected to the DDR3 DRAM storage array and the bus controller respectively.
  • the storage motherboard further includes a power supply circuit
  • the power supply circuit includes a first power supply circuit connected to the first power supply chip and a second power supply circuit connected to the second power supply chip;
  • the first power supply chip includes multiple sets of first power input interfaces, and the multiple sets of first power input interfaces are connected to an external power supply;
  • the first power supply chip also includes a first output interface and a second output interface, and the second output interface includes a second main output interface and a second I/O output interface;
  • the first power supply circuit includes a The first inductance for voltage, the second inductance for voltage stabilization, the first capacitance for coupling, the second capacitance for coupling, and the third capacitance for coupling;
  • the first power supply chip is connected to one end of the first inductance, the other end of the first inductance is connected to the first output interface and the input end of the controller, and the first output interface is connected to the first One end of a capacitor, the other end of the first capacitor is grounded;
  • the second main output interface is connected to the first input end of the flash memory, the second main output interface is connected to one end of the second capacitor, and the other end of the second capacitor is grounded;
  • the second I/O output interface is connected to one end of the second inductor, and the other end of the second inductor is connected to the second input end of the flash memory and the second I/O output interface, and the second I/O The O output interface is connected to one end of the third capacitor, and the other end of the third capacitor is grounded;
  • the second power supply chip includes a second power input interface and an enable pin, and the second power input interface and the enable pin are connected to the external power supply; the second power supply circuit includes a the fourth capacitor;
  • the second power supply chip also includes a third output interface, the third output interface is connected to the input end of the buffer, the third output interface is connected to one end of the fourth capacitor, and the other end of the fourth capacitor One end is grounded.
  • the first power supply circuit is connected with one or more first decoupling capacitors for energy storage and one or more second decoupling capacitors for energy storage; the second power supply circuit is connected with One or more third decoupling capacitors for energy storage.
  • controller, the flash memory and the cache are packaged in the embedded memory chip by BGA technology.
  • the embedded memory chip board is pasted on the Loongson processor, and the space occupied by the embedded memory chip installed on the Loongson processor is small, and the shock resistance is good;
  • the chip has a high degree of integration, and through the combination of Loongson processor and embedded memory chip, the capacity of data storage is increased, the efficiency of data storage is improved, and it can meet the needs of large-capacity storage and fast storage of data in the information age .
  • Fig. 1 schematically shows a schematic diagram of an environmental application of a storage motherboard based on a Loongson processor according to an embodiment of the present application
  • Fig. 2 is the overall structure schematic diagram of the storage motherboard based on the Loongson processor of the utility model embodiment
  • Figure 2-1 is a schematic structural view of the embedded memory chip in the storage motherboard based on the Loongson processor according to the embodiment of the present invention
  • Fig. 3 is the schematic circuit diagram of the first power supply circuit in the storage motherboard based on the Loongson processor of the utility model embodiment
  • Fig. 4 is the circuit schematic diagram of the second power supply circuit in the storage motherboard based on the Loongson processor of the utility model embodiment
  • FIG. 5 is a schematic diagram of circuit connections of one or more first decoupling capacitors in a storage motherboard based on a Loongson processor according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of the circuit connection of one or more second decoupling capacitors in the storage motherboard based on the Loongson processor according to the embodiment of the present invention
  • FIG. 7 is a schematic diagram of the circuit connection of one or more second decoupling capacitors in the storage motherboard based on the Loongson processor according to the embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the circuit connection of one or more third decoupling capacitors in the storage motherboard based on the Godson processor according to the embodiment of the present invention.
  • Loongson processor also known as Loongson platform, Loongson processor can be Loongson 3A4000 chip.
  • the Loongson processor is a Loongson 3 high-performance 64-bit multi-core processor that integrates multiple 64-bit quad-launch high-performance Loongson IP cores. This series of chips is oriented to desktop, server, digital signal processing (DSP) and high-end embedded applications. Due to its low power consumption, some chips can also be used in high-performance ruggedized computers and other equipment. It is one of China's nationally produced CPU (Central Processing Unit / Processor, central processing unit).
  • Bridge piece it can be Godson 7A1000 bridge piece.
  • the Godson 7A1000 bridge chip is a supporting bridge chip for the Godson 3 series processors for servers and desktops.
  • the main peripheral interfaces of the bridge chip include 3 x8 PCIe 2.0 interfaces, 2 x4 PCIe 2.0 interfaces, three SATA2.0, six-way USB2.0, two-way GMAC, two-way DVO, and various other small interfaces.
  • the embedded memory chip can be a self-developed AXD PCIe NVMe BGA SSD embedded memory chip; it is a self-developed BGA package that integrates NAND flash memory, DRAM cache, and self-developed controller Embedded memory chips.
  • the applicant of the utility model understands that the storage disks of domestic chip platforms such as Loongson processors are all standard solid-state hard disks, such as solid-state hard disks of mSATA (mini-SATA, a mini version of SATA interface, which is a computer bus), 7+
  • the solid-state hard disk with 15PIN (chip) interface has at least the following defects:
  • the data stored in the solid-state hard disk of the existing Loongson processor usually adopts the SATA protocol (Serial Advanced Technology Attachment, a protocol used when transmitting signals through an industry-standard serial hardware drive interface) or the USB protocol (Universal Serial Bus, A protocol used to transmit signals through the Universal Serial Bus) for data transmission, the upper limit of the speed is not high, and it cannot meet the processing needs of big data in the information age.
  • SATA Serial Advanced Technology Attachment
  • USB protocol Universal Serial Bus, A protocol used to transmit signals through the Universal Serial Bus
  • FIG. 1 schematically shows a schematic diagram of an environment application of a data storage method based on a Godson processor according to an embodiment of the present application.
  • the environmental application schematic diagram includes a Godson processor 10, a bridge 20 and an embedded memory chip 30; the Godson processor 10 is connected to the bridge 20, and the bridge 20 is connected to the bridge
  • the embedded memory chip is connected through the first PCIe transmission data differential pin pair, and the Godson processor 10 is connected with the embedded memory chip 30 through the bridge sheet 20; the embedded memory chip 30 is integrated with a flash memory, cache and controller.
  • the utility model aims to provide a data storage motherboard based on the Loongson processor.
  • the key points of the utility model are:
  • the data transmission protocol between the self-developed AXD PCIe NVMe embedded memory chip and the Loongson processor is PCIe3.0X4, with a bandwidth of 8GB/s and a high speed limit, which can meet the needs of big data processing in the information age .
  • the self-developed AXD PCIe NVM embedded memory chip is a BGA-packaged embedded memory chip that integrates NAND Flash flash memory, DRAM cache, and a self-developed controller.
  • One or more embodiments will be provided below to specifically introduce the data storage solution based on the Godson processor.
  • FIG. 2 it schematically shows the overall structure of a Loongson processor-based storage motherboard 1 according to an embodiment of the present invention.
  • the storage motherboard 1 based on the Loongson processor comprises: the Loongson processor 10, bridges 20 and embedded memory chips 30, the Loongson processor is used to transmit storage signals, and the storage signals are Based on PCIe3.0X 4.
  • the signal of the data transmission protocol the bridge plate 20 can be connected to the Godson processor 10 through the HT3.0 interface; the embedded memory chip 30 board is attached to the Godson processor 10, and the embedded memory chip 30 Connect the bridge 20; the embedded memory chip 30 includes a controller 4, a flash memory and a cache, and the controller 4 connects the flash memory and the cache; the embedded memory chip 30 is used to store the Godson The data to be processed transmitted by the processor 10.
  • the Loongson processor 10 is a Loongson 3A4000 chip.
  • the bridge 20 may be a Godson 7A1000 bridge.
  • the embedded memory chip 30 can be a self-developed AXD PCIe NVMe BGA SSD embedded memory chip. Described flash memory can be NAND Flash flash memory 5.
  • the cache can be DRAM cache 6 (Dynamic Random Access Memory, dynamic random access memory).
  • the board paste is a point-to-point connection
  • the space occupied by the embedded memory chip 30 on the Godson processor 10 is small, and effectively improves the connection of the embedded memory chip 30 on the Godson processor 10. of shock resistance.
  • the embedded memory chip 30 has a high degree of integration; the interface of the memory motherboard 1 is rich in types, which can meet various usage demands of users for memory products.
  • the embedded memory chip 30 is provided with four sets of first PCIe transmission data differential Pin pairs; the bridge sheet 20 is provided with four sets of second PCIe transmission data differential pin pairs; the four sets of second PCIe transmission data differential pin pairs correspond to the four sets of first PCIe transmission data respectively one by one
  • the four sets of second differential pin pairs for PCIe transmission data are respectively communicatively connected to the corresponding first differential pin pairs for PCIe transmission data, so as to realize signal transmission.
  • the corresponding relationship between the four sets of first PCIe transmission data differential pin pairs and the four second PCIe transmission data differential pin pairs follows the principle of one-to-one correspondence between RX and TX, where RX represents receiving differential signals, and TX Indicates to send a differential signal, P indicates the positive pole, and N indicates the negative pole.
  • the embedded memory chip 30 also includes a bus controller, and the controller 4 is connected to the bus controller; the flash memory includes a Flash controller and a Flash controller. Flash memory chip array; the Flash controller is connected with the Flash flash memory chip array and the bus controller respectively; the cache includes a DRAM controller and a DDR3 DRAM storage array; the DRAM controller is connected with the DDR3 DRAM storage The array is connected to the bus controller.
  • the flash memory and the cache are controlled by the controller 4 to realize the data storage function of the embedded memory chip 30 .
  • the embedded memory chip 30 implements signal transmission between its internal modules through the PCIe bus, and realizes signal transmission between the embedded memory chip 30 and an external processor (such as the Godson processor 10 ) through the PCIe terminal.
  • the PCIe bus includes a PCIe physical layer
  • the PCIe physical layer is the bottom layer of the PCIe bus
  • the PCIe physical layer also includes a PCIe MAC (Media Access Control, media data storage control) layer.
  • the core involved in the PCIe MAC layer is the PCIe NVMe standard (which is an industry standard applicable to solid-state hard drives based on the PCIe protocol).
  • Described embedded storage chip 30 comprises bus controller, dual-core CPU (ie controller 4), RAID codec, Flash controller, Flash flash memory chip array, security engine, main system buffer zone, DMA controller, DRAM controller And DDR3 DRAM (a cache product of computer memory specification), in which the bus controller is connected to the dual-core CPU, RAID codec (Redundant Arrays of Independent Disks, disk array codec), Flash controller, security engine, main system buffer, DMA controller (Direct Memory Access, direct memory access, a controller that allows hardware devices of different speeds to communicate) and The DRAM controller, the Flash controller is connected to the Flash memory chip array, and the DRAM controller is connected to the DDR3 DRAM.
  • dual-core CPU ie controller 4
  • RAID codec Redundant Arrays of Independent Disks, disk array codec
  • Flash controller security engine
  • main system buffer main system buffer
  • DMA controller Direct Memory Access, direct memory access, a controller that allows hardware devices of different speeds to communicate
  • the controller, the flash memory and the cache are packaged in the embedded memory chip by BGA technology.
  • BGA All Grid Array
  • BGA packaging technology is a ball grid array packaging technology, which is a high-density surface mount packaging technology.
  • Embedded memory chips using BGA packaging technology have smaller volume, faster and more effective heat dissipation performance and electrical performance under the same capacity.
  • the storage motherboard 1 also includes a power supply circuit, and the power supply circuit includes a first power supply circuit connected to the first power supply chip and a A second power supply circuit connected to the second power supply chip;
  • the first power supply chip includes multiple sets of first power input interfaces, and the multiple sets of first power input interfaces are connected to an external power supply;
  • the first power supply chip also includes a first output interface and a second output interface, and the second output interface includes a second main output interface and a second I/O output interface;
  • the first power supply circuit includes a The first inductance for voltage, the second inductance for voltage stabilization, the first capacitance for coupling, the second capacitance for coupling, and the third capacitance for coupling;
  • the first power supply chip is connected to one end of the first inductance, the other end of the first inductance is connected to the first output interface and the input end of the controller 4, and the first output interface is connected to the one end of the first capacitor, and the other end of the first capacitor is grounded;
  • the second main output interface is connected to the first input end of the flash memory, the second main output interface is connected to one end of the second capacitor, and the other end of the second capacitor is grounded;
  • the second I/O output interface is connected to one end of the second inductor, and the other end of the second inductor is connected to the second input end of the flash memory and the second I/O output interface, and the second I/O The O output interface is connected to one end of the third capacitor, and the other end of the third capacitor is grounded;
  • the second power supply chip includes a second power input interface and an enable pin, and the second power input interface and the enable pin are connected to the external power supply; the second power supply circuit includes a the fourth capacitor;
  • the second power supply chip also includes a third output interface, the third output interface is connected to the input end of the buffer, the third output interface is connected to one end of the fourth capacitor, and the other end of the fourth capacitor One end is grounded.
  • FIG. 3 schematically shows a schematic diagram of a power supply circuit of the first power supply circuit
  • FIG. 4 schematically shows a schematic diagram of a second power supply circuit. details as follows:
  • the first power supply circuit As shown in Figure 3, the first power supply circuit:
  • the first power supply circuit includes a first power supply chip, and the first power supply chip includes multiple sets of first power input interfaces, such as two sets of VIN1, two sets of VIN2, two sets of VIN3 and VIN, and the multiple sets of first The power input interface is connected to the external power supply H33V.
  • first power input interface is connected to the external power supply H33V.
  • two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected in parallel through wires, all of which are connected to the external power supply H33V.
  • Two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected to a capacitor and then grounded.
  • the first power supply chip also includes a first output interface VOUT3 (such as pin G1) and a second output interface, and the second output interface includes a second main output interface VOUT1 (such as pins D5, D6) and a second I/O output interface VOUT2 (such as pin E6);
  • the first power supply circuit includes a first inductor L3 for elegance, a second inductor L2 for voltage stabilization, a first capacitor C19 for coupling, and The second capacitor C10 for coupling and the third capacitor C16 for coupling.
  • the first power supply circuit also includes a first inductance connection interface LX3 (such as pins F3 and G3), the first inductance connection interface LX3 is connected to one end of the first inductance L3, and the other end of the first inductance L3 Connect the first output interface VOUT3 to the input terminal VCCK of the controller 4 (such as pins G7, G8, G11, G12, H7, H8, H11, H12, J7, J8, J11, J12), the first An output interface VOUT3 is connected to one end of the first capacitor C19, and the other end of the first capacitor C19 is grounded.
  • a first inductance connection interface LX3 such as pins F3 and G3
  • the first inductance connection interface LX3 is connected to one end of the first inductance L3, and the other end of the first inductance L3 Connect the first output interface VOUT3 to the input terminal VCCK of the controller 4 (such as pins G7, G8, G11, G12, H7, H8, H
  • the second main output interface VOUT1 is connected to the first input terminal VCC3F of the flash memory (such as pins D10, E9, E10, W9, W10, Y9, Y10), and the second main output interface VOUT1 is connected to the second One end of the capacitor C10, and the other end of the second capacitor C10 are grounded.
  • the first power supply circuit also includes a second inductance connection interface LX2 (such as pins F5 and F6), the second inductance connection interface LX2 is connected to one end of the second inductance L2, and the other end of the second inductance L2 Connect the second I/O output interface VOUT2 and the second input terminal VCCFQ of the flash memory (such as pins R8, R11, R12, T7, T8, T11, T12, U7, U8, U11, U12), the The second I/O output interface VOUT2 is connected to one end of the third capacitor C16, and the other end of the third capacitor C16 is grounded.
  • a second inductance connection interface LX2 such as pins F5 and F6
  • the second inductance connection interface LX2 is connected to one end of the second inductance L2
  • the other end of the second inductance L2 Connect the second I/O output interface VOUT2 and the second input terminal VCCFQ of the flash memory (such as pins R8, R11, R
  • the first power supply circuit also includes a first ground interface PGND1 (such as pin A5, A6), a second ground interface PGND2 (such as pin E5), a third ground interface PGND3 (such as pin F4, G4) and a fourth Ground interface AGND (such as pin C1).
  • PGND1 such as pin A5, A6
  • PGND2 such as pin E5
  • PGND3 such as pin F4, G4
  • fourth Ground interface AGND such as pin C1
  • the second power supply circuit As shown in Figure 4, the second power supply circuit:
  • the second power supply circuit includes a second power supply chip, the second power supply chip includes a second power input interface VIN and an enable pin EN, and the second power input interface VIN and the enable pin EN Connect the external power supply H33V; the second power supply circuit includes a fourth capacitor C23 for coupling;
  • the second power supply chip also includes a third output interface VOUT, the third output interface VOUT is connected to the input terminal V18 of the buffer (such as pin R7), and the third output interface VOUT is connected to the fourth capacitor one end of the fourth capacitor, and the other end of the fourth capacitor is grounded.
  • the second power supply chip also includes ground terminals, such as GND and SGND.
  • the first power supply circuit is connected to one or more A first decoupling capacitor for energy storage and one or more second decoupling capacitors for energy storage; the second power supply circuit is connected with one or more third decoupling capacitors for energy storage.
  • the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor Through the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor, the interference of other signals is avoided during signal transmission, and the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor are all It has the function of caching energy.
  • the first decoupling capacitor includes capacitor C6542, capacitor BC46, capacitor BC47, and capacitor BC49, wherein one end of capacitor C6542 is connected to the input terminal VCCK of the controller 4, and one end of capacitor C6542 is connected to one end of capacitor BC46 , the other end of capacitor C6542 is connected to the other end of capacitor BC46, and the other end of capacitor C6542 is grounded; one end of capacitor BC46 is connected to one end of capacitor BC47, the other end of capacitor BC46 is connected to the other end of capacitor BC47; one end of capacitor BC47 is connected to capacitor BC49 One end of the capacitor BC47 is connected to the other end of the capacitor BC49.
  • the second decoupling capacitor includes capacitor C6537, capacitor BC48, capacitor BC35, and capacitor BC40, wherein one end of capacitor C6537 is connected to the first input terminal VCC3F of the flash memory, and one end of capacitor C6537 is connected to one end of capacitor BC48 , the other end of capacitor C6537 is connected to the other end of capacitor BC48, and the other end of capacitor C6537 is grounded; one end of capacitor BC48 is connected to one end of capacitor BC35, the other end of capacitor BC48 is connected to the other end of capacitor BC35; one end of capacitor BC35 is connected to capacitor BC40 One end of the capacitor BC35 is connected to the other end of the capacitor BC40.
  • the second decoupling capacitor also includes capacitor C6541, capacitor BC51, capacitor BC38, capacitor BC52 and capacitor BC55, wherein one end of capacitor C6541 is connected to the second input terminal VCCFQ of the flash memory, and one end of capacitor C6541 is connected to One end of capacitor BC51, the other end of capacitor C6541 is connected to the other end of capacitor BC51, and the other end of capacitor C6541 is grounded; one end of capacitor BC51 is connected to one end of capacitor BC38, and the other end of capacitor BC51 is connected to the other end of capacitor BC38; the other end of capacitor BC38 One end is connected to one end of capacitor BC52, the other end of capacitor BC38 is connected to the other end of capacitor BC52; one end of capacitor BC52 is connected to one end of capacitor BC55, and the other end of capacitor BC52 is connected to the other end of capacitor BC55.
  • the third decoupling capacitor also includes a capacitor C6538 and a capacitor BC45, wherein one end of the capacitor C6538 is connected to the input terminal V18 of the buffer, one end of the capacitor C6538 is connected to one end of the capacitor BC45, and the other end of the capacitor C6538 is connected to The other end of the capacitor BC45, and the other end of the capacitor C6538 is grounded.
  • the embedded memory chip is directly mounted on the Loongson processor. Compared with the storage solid-state hard disk with gold fingers, it occupies less space and has better shock resistance.
  • the data transmission protocol of the embedded memory chip is the PCIe3.0X4 protocol, the bandwidth can reach 8GB/s, and the upper limit of the speed is high, which can meet the demand for fast data storage in today's information age.
  • the embedded memory chip is a BGA-packaged embedded memory chip that integrates NAND Flash flash memory, DRAM cache, and self-developed controller. It is equipped with a Loongson processor to realize a national production platform, which will help promote domestic CPUs to The development of domestic storage media.

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Abstract

本实用新型提供一种基于龙芯处理器的存储主板，包括：所述龙芯处理器；桥片，通过HT3.0接口连接所述龙芯处理器；以及嵌入式存储芯片，板贴于所述龙芯处理器，所述嵌入式存储芯片连接所述桥片；所述嵌入式存储芯片包括控制器、闪存和缓存，所述控制器连接所述闪存和所述缓存；所述嵌入式存储芯片用于存储所述龙芯处理器传输的待处理数据。在本实用新型中，通过板贴在龙芯处理器上的所述嵌入式存储芯片和龙芯处理器的结合的方式，并且所述嵌入式存储芯片集成化程度高，有助于数据快速存储、提高数据存储效率。

Description

基于龙芯处理器的存储主板 技术领域
本实用新型实施例涉及芯片技术领域，尤其涉及一种基于龙芯处理器的存储主板。
 背景技术
随着信息技术的发展，信息化时代对于大数据存储的需求也随之提高。目前，国内大部分计算机产品中应用的CPU（Central Processing Unit / Processor，中央处理器）的存储盘设计采用的是国外的CPU芯片结合国外的存储芯片实现数据的存储。由于芯片留有后门，国外的存储芯片应用到国产的计算机系统中，信息的安全性和保密性难以得到保证。因此，国产化CPU芯片应运而生，比如龙芯处理器。
 技术问题
现有的龙芯处理器的存储盘通常集成有用于实现数据存储的PCIe传输数据差分引脚对，但现有的龙芯处理器的存储盘集成的PCIe传输数据差分引脚对的数量有限，导致现有的龙芯处理器的存储盘无法满足信息化时代对于数据的大容量存储和快速存储的需求。
 技术解决方案
有鉴于此，本实用新型实施例提供了一种基于龙芯处理器的存储主板，用于解决现有的龙芯处理器的存储盘存储容量小、存储效率低的问题。
本实用新型实施例是通过下述技术方案来解决上述技术问题：
本实用新型还提供一种基于龙芯处理器的存储主板，包括：
所述龙芯处理器；
桥片，通过HT3.0接口连接所述龙芯处理器；以及
嵌入式存储芯片，板贴于所述龙芯处理器，所述嵌入式存储芯片连接所述桥片；所述嵌入式存储芯片包括控制器、闪存和缓存，所述控制器连接所述闪存和所述缓存；所述嵌入式存储芯片用于存储所述龙芯处理器传输的待处理数据。
可选地，所述嵌入式存储芯片设置有四组第一PCIe传输数据差分引脚对；
所述桥片设有四组第二PCIe传输数据差分引脚对；
所述四组第二PCIe传输数据差分引脚对分别一一对应于所述四组第一PCIe传输数据差分引脚对，所述四组第二PCIe传输数据差分引脚对分别与对应的第一PCIe传输数据差分引脚对通信连接，以实现信号传输。
可选地，所述嵌入式存储芯片还包括总线控制器，所述控制器连接所述总线控制器；
所述闪存包括Flash控制器和Flash闪存芯片阵列；所述Flash控制器分别与所述Flash闪存芯片阵列和所述总线控制器连接；
所述缓存包括DRAM控制器和DDR3 DRAM存储阵列；所述DRAM控制器分别与所述DDR3 DRAM存储阵列和所述总线控制器连接。
可选地，所述存储主板还包括供电电路，所述供电电路包括与第一电源供电芯片连接的第一供电电路和与第二电源供电芯片连接的第二供电电路；
所述第一电源供电芯片包括多组第一电源输入接口，所述多组第一电源输入接口连接外部电源；
所述第一电源供电芯片还包括第一输出接口和第二输出接口，所述第二输出接口包括第二主输出接口和第二I/O输出接口；所述第一供电电路包括用于稳压的第一电感、用于稳压的第二电感、用于耦合的第一电容、用于耦合的第二电容和用于耦合的第三电容；
所述第一电源供电芯片连接所述第一电感的一端，所述第一电感的另一端连接所述第一输出接口和所述控制器的输入端，所述第一输出接口连接所述第一电容的一端，所述第一电容的另一端接地；
所述第二主输出接口连接所述闪存的第一输入端，所述第二主输出接口连接所述第二电容的一端，所述第二电容的另一端接地；
所述第二I/O输出接口连接第二电感的一端，所述第二电感的另一端连接所述闪存的第二输入端和所述第二I/O输出接口，所述第二I/O输出接口连接所述第三电容的一端，所述第三电容的另一端接地；
所述第二电源供电芯片包括第二电源输入接口和使能引脚，所述第二电源输入接口和所述使能引脚连接所述外部电源；所述第二供电电路包括用于耦合的第四电容；
所述第二电源供电芯片还包括第三输出接口，所述第三输出接口连接所述缓存的输入端，所述第三输出接口连接所述第四电容的一端，所述第四电容的另一端接地。
可选地，所述第一供电电路连接有一个或多个用于储能的第一去耦电容和一个或多个用于储能的第二去耦电容；所述第二供电电路连接有一个或多个用于储能的第三去耦电容。
可选地，所述控制器、所述闪存以及所述缓存通过BGA技术封装于所述嵌入式存储芯片内。
本实用新型实施例提供的基于龙芯处理器的存储主板，嵌入式存储芯片板贴于龙芯处理器上，嵌入式存储芯片安装在龙芯处理器上所占的空间小，抗震性好；嵌入式存储芯片集成化程度高，且通过龙芯处理器结合嵌入式存储芯片的方式，增大了数据存储的容量，提高了数据存储的效率，能够满足信息化时代对于数据的大容量存储和快速存储的需求。
以下结合附图和具体实施例对本实用新型进行详细描述，但不作为对本实用新型的限定。
 附图说明
图1示意性示出了基于本申请实施例之基于龙芯处理器的存储主板的环境应用示意图；
图2为本实用新型实施例之基于龙芯处理器的存储主板的整体结构示意图；
图2-1为本实用新型实施例之基于龙芯处理器的存储主板中所述嵌入式存储芯片的结构示意图；
图3为本实用新型实施例之基于龙芯处理器的存储主板中第一供电电路的电路示意图；
图4为本实用新型实施例之基于龙芯处理器的存储主板中第二供电电路的电路示意图；
图5为本实用新型实施例之基于龙芯处理器的存储主板中一个或多个第一去耦电容的电路连接示意图；
图6为本实用新型实施例之基于龙芯处理器的存储主板中一个或多个第二去耦电容的电路连接示意图；
图7为本实用新型实施例之基于龙芯处理器的存储主板中一个或多个第二去耦电容的电路连接示意图；
图8为本实用新型实施例之基于龙芯处理器的存储主板中一个或多个第三去耦电容的电路连接示意图。
 本发明的最佳实施方式
为了使本实用新型的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本实用新型进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本实用新型，并不用于限定本实用新型。基于本实用新型中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本实用新型保护的范围。
需要说明的是，在本实用新型实施例中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本实用新型要求的保护范围之内。
在本实用新型的描述中，需要理解的是，步骤前的数字标号并不标识执行步骤的前后顺序，仅用于方便描述本实用新型及区别每一步骤，因此不能理解为对本实用新型的限制。
术语解释：
龙芯处理器：又称龙芯平台，龙芯处理器可以为龙芯3A4000芯片。龙芯处理器为龙芯3号高性能64位多核处理器片内集成多个64位四发射高性能龙芯IP核。该系列芯片面向桌面、服务器、数字信号处理（DSP）和高端嵌入式等应用，由于其低功耗的特性，部分芯片亦可应用于高性能的加固计算机等装备。是中国全国产化CPU（Central Processing Unit / Processor，中央处理器）的之一。
桥片：可以为龙芯7A1000桥片。龙芯 7A1000 桥片是面向服务器及桌面领域的龙芯 3 号系列处理器配套桥片。该桥片的主要外围接口包括 3个 x8 PCIe 2.0 接口、2 个 x4 PCIe 2.0 接口、三路 SATA2.0、六路 USB2.0、两路GMAC、两路 DVO，及其它各种小接口。
嵌入式存储芯片：在本申请中，嵌入式存储芯片可以为自研的AXD PCIe NVMe BGA SSD嵌入式存储芯片；是自研的集NAND flash闪存、DRAM缓存、自主研发控制器为一体的BGA封装嵌入式存储芯片。
本实用新型申请人了解到：诸如龙芯处理器的国产芯片平台的存储盘都是标准固态硬盘，例如：mSATA（mini-SATA，迷你版SATA接口，为一种计算机总线）的固态硬盘、7+15PIN（芯片）接口的固态硬盘，至少存在以下缺陷：
（1）现有龙芯处理器的固态硬盘占用空间较大、抗震性较差。
（2）现有龙芯处理器的固态硬盘存储数据通常采用SATA协议（Serial Advanced Technology Attachment，一种通过基于行业标准的串行硬件驱动器接口传输信号时使用的协议）或者USB协议（Universal Serial Bus，一种通过通用串行总线传输信号时使用的协议）进行数据传输，速度上限不高，无法满足信息化时代的大数据的处理需求。
（3）现有龙芯处理器的固态硬盘集成程度较差。
为解决上述问题，下文将提供多个实施例，下文提供的各个实施例可以用于实现基于龙芯处理器的数据存储。
图1示意性示出了基于本申请实施例的基于龙芯处理器的数据存储方法的环境应用示意图。在示例性的实施例中，该环境应用示意图包括龙芯处理器10、桥片20和嵌入式存储芯片30；所述龙芯处理器10与所述桥片20连接，所述桥片20与所述嵌入式存储芯片通过第一PCIe传输数据差分引脚对连接，所述龙芯处理器10通过所述桥片20和所述嵌入式存储芯片30连接；所述嵌入式存储芯片30内集成有闪存、缓存和控制器。
本实用新型旨在提供一种基于龙芯处理器的数据存储主板，本实用新型的关键点在于：
（1）通过将自研发的AXD PCIe NVMe嵌入式存储芯片板贴于龙芯处理器上，实现占空间小，抗震性好的效果。
（2）自研发的AXD PCIe NVMe嵌入式存储芯片与龙芯处理器进行数据传输的数据传输协议是PCIe3.0X4的，带宽为8GB/s，速度上限高，可以满足信息化时代的大数据处理需求。
（3）自研发的AXD PCIe NVM嵌入式存储芯片是集NAND Flash闪存、DRAM缓存、自主研发的控制器为一体的BGA封装嵌入式存储芯片，搭配龙芯处理器，实现全国产化平台，打造属于国产CPU到国产存储介质的链条。
以下将提供一个或多个实施例，来具体介绍基于龙芯处理器的数据存储方案。
参阅图2，示意性示出了本实用新型实施例之一种基于龙芯处理器的存储主板1的整体结构示意图。
如图2所示，所述基于龙芯处理器的存储主板1包括：所述龙芯处理器10、桥片20以及嵌入式存储芯片30，所述龙芯处理器用于传输存储信号，所述存储信号为基于PCIe3.0X 4数据传输协议的信号；所述桥片20可以通过HT3.0接口连接所述龙芯处理器10；所述嵌入式存储芯片30板贴于所述龙芯处理器10，所述嵌入式存储芯片30连接所述桥片20；所述嵌入式存储芯片30包括控制器4、闪存和缓存，所述控制器4连接所述闪存和所述缓存；所述嵌入式存储芯片30用于存储所述龙芯处理器10传输的待处理数据。其中，所述龙芯处理器10为龙芯3A4000芯片。所述桥片20可以为龙芯7A1000桥片。所述嵌入式存储芯片30可以为自研的AXD PCIe NVMe BGA SSD嵌入式存储芯片。所述闪存可以为NAND Flash闪存5。所述缓存可以为DRAM缓存6（Dynamic Random Access Memory，动态随机存取存储器）。
在本实用新型中，由于板贴是点对点的连接，因此所述嵌入式存储芯片30安装在龙芯处理器10上所占的空间小，并且有效提高了嵌入式存储芯片30在龙芯处理器10上的抗震性。并且所述嵌入式存储芯片30集成化程度高；所述存储主板1的接口种类丰富，可以满足用户对存储产品的多种使用需求。
为了保证所述嵌入式存储芯片30和所述龙芯处理器10之间能够实现正常的信号传输，在示例性的实施例中，所述嵌入式存储芯片30设置有四组第一PCIe传输数据差分引脚对；所述桥片20设有四组第二PCIe传输数据差分引脚对；所述四组第二PCIe传输数据差分引脚对分别一一对应于所述四组第一PCIe传输数据差分引脚对，所述四组第二PCIe传输数据差分引脚对分别与对应的第一PCIe传输数据差分引脚对通信连接，以实现信号传输。在本实施中，四组第一PCIe传输数据差分引脚对和四组第二PCIe传输数据差分引脚对的对应关系遵循RX与TX一一对应的原则，其中，RX表示接收差分信号，TX表示发送差分信号，P表示正极，N表示负极。
为了实现嵌入式存储芯片30中各个模块之间的信号传输，所述嵌入式存储芯片30还包括总线控制器，所述控制器4连接所述总线控制器；所述闪存包括Flash控制器和Flash闪存芯片阵列；所述Flash控制器分别与所述Flash闪存芯片阵列和所述总线控制器连接；所述缓存包括DRAM控制器和DDR3 DRAM存储阵列；所述DRAM控制器分别与所述DDR3 DRAM存储阵列和所述总线控制器连接。在本实施例中，通过控制器4控制所述闪存和所述缓存以实现所述嵌入式存储芯片30的数据存储功能。
结合图2-1，示出了所述嵌入式存储芯片30的结构示意图。所述嵌入式存储芯片30通过PCIe总线实现其内部各个模块之间的信号传输以及实现所述嵌入式存储芯片30与外部处理器（如龙芯处理器10）之间通过PCIe端的信号传输。其中，所述PCIe总线包括PCIe物理层，PCIe物理层为PCIe总线的最底层，PCIe物理层还包括PCIe MAC（Media Access Control，媒体数据存储控制）层。在本实用新型中，PCIe MAC层涉及的核心为PCIe NVMe标准（是一种适用于基于PCIe协议的固态硬盘行业标准）。
所述嵌入式存储芯片30包括总线控制器、双核CPU（即控制器4）、RAID编解码器、Flash控制器、Flash闪存芯片阵列、安全引擎、主系统缓冲区、DMA控制器、DRAM控制器以及DDR3 DRAM（一种计算机内存规格的缓存产品），其中，总线控制器连接分别连接双核CPU、RAID编解码器(Redundant Arrays of Independent Disks, 磁盘阵列编解码器)、Flash控制器、安全引擎、主系统缓冲区、DMA控制器（Direct Memory Access，直接存储器访问，一种允许不同速度的硬件装置沟通的控制器）和DRAM控制器，Flash控制器连接Flash闪存芯片阵列，DRAM控制器连接DDR3 DRAM。
在示例性的实施例中，所述控制器、所述闪存以及所述缓存通过BGA技术封装于所述嵌入式存储芯片内。BGA(Ball Grid Array)封装技术为球状引脚栅格阵列封装技术，是一种高密度表面装配封装技术。采用BGA封装技术的嵌入式存储芯片在相同容量下，具有更小的体积、更加快速有效的散热性能和电性能。
为了实现对所述嵌入式存储芯片30的供电；在示例性的实施例中，所述存储主板1还包括供电电路，所述供电电路包括与第一电源供电芯片连接的第一供电电路和与第二电源供电芯片连接的第二供电电路；
所述第一电源供电芯片包括多组第一电源输入接口，所述多组第一电源输入接口连接外部电源；
所述第一电源供电芯片还包括第一输出接口和第二输出接口，所述第二输出接口包括第二主输出接口和第二I/O输出接口；所述第一供电电路包括用于稳压的第一电感、用于稳压的第二电感、用于耦合的第一电容、用于耦合的第二电容和用于耦合的第三电容；
所述第一电源供电芯片连接所述第一电感的一端，所述第一电感的另一端连接所述第一输出接口和所述控制器4的输入端，所述第一输出接口连接所述第一电容的一端，所述第一电容的另一端接地；
所述第二主输出接口连接所述闪存的第一输入端，所述第二主输出接口连接所述第二电容的一端，所述第二电容的另一端接地；
所述第二I/O输出接口连接第二电感的一端，所述第二电感的另一端连接所述闪存的第二输入端和所述第二I/O输出接口，所述第二I/O输出接口连接所述第三电容的一端，所述第三电容的另一端接地；
所述第二电源供电芯片包括第二电源输入接口和使能引脚，所述第二电源输入接口和所述使能引脚连接所述外部电源；所述第二供电电路包括用于耦合的第四电容；
所述第二电源供电芯片还包括第三输出接口，所述第三输出接口连接所述缓存的输入端，所述第三输出接口连接所述第四电容的一端，所述第四电容的另一端接地。
为了更好的控制预设上电时序，请参阅图3和图4，图3示意性示出了第一供电电路的供电电路示意图，图4示意性示出了第二供电电路示意图。具体如下：
如图3所示，第一供电电路：
所述第一供电电路包括第一电源供电芯片，所述第一电源供电芯片包括多组第一电源输入接口，例如两组VIN1、两组VIN2、两组VIN3和VIN，所述多组第一电源输入接口连接外部电源H33V。示例性的，两组VIN1、两组VIN2、两组VIN3和VIN通过导线并联，均连接外部电源H33V。两组VIN1、两组VIN2、两组VIN3和VIN均连接一个电容之后接地。
所述第一电源供电芯片还包括第一输出接口VOUT3（如引脚G1）和第二输出接口，所述第二输出接口包括第二主输出接口VOUT1（如引脚D5、D6）和第二I/O输出接口VOUT2（如引脚E6）；所述第一供电电路包括用于文雅的第一电感L3、用于稳压的第二电感L2、用于耦合的第一电容C19、用于耦合的第二电容C10和用于耦合的第三电容C16。
所述第一供电电路还包括第一电感连接接口LX3（如引脚F3、G3），所述第一电感连接接口LX3连接所述第一电感L3的一端，所述第一电感L3的另一端连接所述第一输出接口VOUT3和所述控制器4的输入端VCCK（例如引脚G7、G8、G11、G12、H7、H8、H11、H12、J7、J8、J11、J12），所述第一输出接口VOUT3连接所述第一电容C19的一端，所述第一电容C19的另一端接地。
所述第二主输出接口VOUT1连接所述闪存的第一输入端VCC3F（例如引脚D10、E9、E10、W9、W10、Y9、Y10），所述第二主输出接口VOUT1连接所述第二电容C10的一端，所述第二电容C10的另一端接地。
所述第一供电电路还包括第二电感连接接口LX2（如引脚F5、F6），所述第二电感连接接口LX2连接所述第二电感L2的一端，所述第二电感L2的另一端连接所述第二I/O输出接口VOUT2和所述闪存的第二输入端VCCFQ（例如引脚R8、R11、R12、T7、T8、T11、T12、U7、U8、U11、U12），所述第二I/O输出接口VOUT2连接所述第三电容C16的一端，所述第三电容C16的另一端接地。
所述第一供电电路还包括第一接地接口PGND1（如引脚A5、A6）、第二接地接口PGND2（如引脚E5）、第三接地接口PGND3（如引脚F4、G4）以及第四接地接口AGND（如引脚C1）。
如图4所示，第二供电电路：
所述第二供电电路包括第二电源供电芯片，所述第二电源供电芯片包括第二电源输入接口VIN和使能引脚EN，所述第二电源输入接口VIN和所述使能引脚EN连接所述外部电源H33V；所述第二供电电路包括用于耦合的第四电容C23；
所述第二电源供电芯片还包括第三输出接口VOUT，所述第三输出接口VOUT连接所述缓存的输入端V18（例如引脚R7），所述第三输出接口VOUT连接所述第四电容的一端，所述第四电容的另一端接地。所述第二电源供电芯片还包括接地端，例如GND和SGND。
为了在供电电路无法为所述嵌入式存储芯片30供电或者无法及时供电时，保证嵌入式存储芯片30的正常运行，如图5-图8所示，所述第一供电电路连接有一个或多个用于储能的第一去耦电容和一个或多个用于储能的第二去耦电容；所述第二供电电路连接有一个或多个用于储能的第三去耦电容。通过上述第一去耦电容、第二去耦电容和第三去耦电容，在信号传输过程中避免其他信号的干扰，且第一去耦电容、第二去耦电容以及第三去耦电容均具备缓存能量的功能。在高频器件工作的时候，在频率的影响下，产生很大的电感影响，而导致嵌入式存储芯片30各个模块的供电不及时或者是供电电路与嵌入式存储芯片30断开连接时，通过上述去耦电容及时为所述嵌入式存储芯片30各个模块供电，保证嵌入式存储芯片30能够正常运行。
如图5所示，第一去耦电容包括电容C6542、电容BC46、电容BC47、电容BC49，其中，电容C6542的一端连接所述控制器4的输入端VCCK，电容C6542的一端连接电容BC46的一端，电容C6542的另一端连接电容BC46的另一端，且电容C6542的另一端接地；电容BC46的一端连接电容BC47的一端，电容BC46的另一端连接电容BC47的另一端；电容BC47的一端连接电容BC49的一端，电容BC47的另一端连接电容BC49的另一端。
如图6所示，第二去耦电容包括电容C6537、电容BC48、电容BC35、电容BC40，其中，电容C6537的一端连接所述闪存的第一输入端VCC3F，电容C6537的一端连接电容BC48的一端，电容C6537的另一端连接电容BC48的另一端，且电容C6537的另一端接地；电容BC48的一端连接电容BC35的一端，电容BC48的另一端连接电容BC35的另一端；电容BC35的一端连接电容BC40的一端，电容BC35的另一端连接电容BC40的另一端。
如图7所示，第二去耦电容还包括电容C6541、电容BC51、电容BC38、电容BC52和电容BC55，其中，电容C6541的一端连接所述闪存的第二输入端VCCFQ，电容C6541的一端连接电容BC51的一端，电容C6541的另一端连接电容BC51的另一端，且电容C6541的另一端接地；电容BC51的一端连接电容BC38的一端，电容BC51的另一端连接电容BC38的另一端；电容BC38的一端连接电容BC52的一端，电容BC38的另一端连接电容BC52的另一端；电容BC52的一端连接电容BC55的一端，电容BC52的另一端连接电容BC55的另一端。
如图8所示，第三去耦电容还包括电容C6538和电容BC45，其中，电容C6538的一端连接所述缓存的输入端V18，电容C6538的一端连接电容BC45的一端，电容C6538的另一端连接电容BC45的另一端，且电容C6538的另一端接地。
本实用新型实施例至少具有以下有益效果：
（1）所述嵌入式存储芯片直接板贴在龙芯处理器上，相比于有金手指的存储固态硬盘，所占空间小，抗震性能好。
（2）所述嵌入式存储芯片的数据传输协议为PCIe3.0X4协议，带宽可达到8GB/s，速度上限高，可以满足当今信息化时代的对数据快速存储的需求。
（3）所述嵌入式存储芯片是集NAND Flash闪存、DRAM缓存、自主研发控制器为一体的BGA封装嵌入式存储芯片，搭配龙芯处理器，实现全国产化平台，有助于推动国产CPU到国产存储介质的发展。
上述本实用新型实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。
以上仅为本实用新型的优选实施例，并非因此限制本实用新型的专利范围，凡是利用本实用新型说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本实用新型的专利保护范围内。

Claims (6)

  1. 一种基于龙芯处理器的存储主板，其特征在于，包括：
    所述龙芯处理器；
    桥片，通过HT3.0接口连接所述龙芯处理器；以及
    嵌入式存储芯片，板贴于所述龙芯处理器，所述嵌入式存储芯片连接所述桥片；所述嵌入式存储芯片包括控制器、闪存和缓存，所述控制器连接所述闪存和所述缓存；所述嵌入式存储芯片用于存储所述龙芯处理器传输的待处理数据。
  2. 根据权利要求1所述的基于龙芯处理器的存储主板，其特征在于，所述嵌入式存储芯片设置有四组第一PCIe传输数据差分引脚对；
    所述桥片设有四组第二PCIe传输数据差分引脚对；
    所述四组第二PCIe传输数据差分引脚对一一对应于所述四组第一PCIe传输数据差分引脚对，所述四组第二PCIe传输数据差分引脚对分别与对应的第一PCIe传输数据差分引脚对通信连接，以实现信号传输。
  3. 根据权利要求1所述的基于龙芯处理器的存储主板，其特征在于，所述嵌入式存储芯片还包括总线控制器，所述控制器连接所述总线控制器；
    所述闪存包括Flash控制器和Flash闪存芯片阵列；所述Flash控制器分别与所述Flash闪存芯片阵列和所述总线控制器连接；
    所述缓存包括DRAM控制器和DDR3 DRAM存储阵列；所述DRAM控制器分别与所述DDR3 DRAM存储阵列和所述总线控制器连接。
  4. 根据权利要求1所述的基于龙芯处理器的存储主板，其特征在于，所述存储主板还包括供电电路，所述供电电路包括与第一电源供电芯片连接的第一供电电路和与第二电源供电芯片连接的第二供电电路；
    所述第一电源供电芯片包括多组第一电源输入接口，所述多组第一电源输入接口连接外部电源；
    所述第一电源供电芯片还包括第一输出接口和第二输出接口，所述第二输出接口包括第二主输出接口和第二I/O输出接口；所述第一供电电路包括用于稳压的第一电感、用于稳压的第二电感、用于耦合的第一电容、用于耦合的第二电容和用于耦合的第三电容；
    所述第一电源供电芯片连接所述第一电感的一端，所述第一电感的另一端连接所述第一输出接口和所述控制器的输入端，所述第一输出接口连接所述第一电容的一端，所述第一电容的另一端接地；
    所述第二主输出接口连接所述闪存的第一输入端，所述第二主输出接口连接所述第二电容的一端，所述第二电容的另一端接地；
    所述第二I/O输出接口连接第二电感的一端，所述第二电感的另一端连接所述闪存的第二输入端和所述第二I/O输出接口，所述第二I/O输出接口连接所述第三电容的一端，所述第三电容的另一端接地；
    所述第二电源供电芯片包括第二电源输入接口和使能引脚，所述第二电源输入接口和所述使能引脚连接所述外部电源；所述第二供电电路包括用于耦合的第四电容；
    所述第二电源供电芯片还包括第三输出接口，所述第三输出接口连接所述缓存的输入端，所述第三输出接口连接所述第四电容的一端，所述第四电容的另一端接地。
  5. 根据权利要求4所述的基于龙芯处理器的存储主板，其特征在于，所述第一供电电路连接有一个或多个用于储能的第一去耦电容和一个或多个用于储能的第二去耦电容；所述第二供电电路连接有一个或多个用于储能的第三去耦电容。
  6. 根据权利要求1所述的基于龙芯处理器的存储主板，其特征在于，所述控制器、所述闪存以及所述缓存通过BGA技术封装于所述嵌入式存储芯片内。
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