CN102934244A - 发射辐射的半导体本体、用于制造发射辐射的半导体本体的方法和发射辐射的半导体器件 - Google Patents
发射辐射的半导体本体、用于制造发射辐射的半导体本体的方法和发射辐射的半导体器件 Download PDFInfo
- Publication number
- CN102934244A CN102934244A CN2011800286696A CN201180028669A CN102934244A CN 102934244 A CN102934244 A CN 102934244A CN 2011800286696 A CN2011800286696 A CN 2011800286696A CN 201180028669 A CN201180028669 A CN 201180028669A CN 102934244 A CN102934244 A CN 102934244A
- Authority
- CN
- China
- Prior art keywords
- semiconductor body
- bearing bed
- contact structures
- layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 58
- 230000005670 electromagnetic radiation Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 54
- 230000005855 radiation Effects 0.000 claims description 37
- 230000006835 compression Effects 0.000 claims description 23
- 238000007906 compression Methods 0.000 claims description 23
- 238000003466 welding Methods 0.000 claims description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000004411 aluminium Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 33
- 238000000151 deposition Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 6
- 238000012856 packing Methods 0.000 description 6
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000009940 knitting Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92227—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Led Device Packages (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Wire Bonding (AREA)
Abstract
本发明提出一种发射辐射的半导体本体(14),所述半导体本体除了带有适合产生电磁辐射的有源区(4)的外延的半导体层序列(3)之外具有承载层,所述承载层设置成机械地稳固外延的半导体层序列(3)。此外,半导体本体(14)具有接触结构(9,91)以用于电接触半导体本体(14),所述接触结构分别具有体积区域(12)和表面接合区域(13),其中表面接合区域由与体积区域(12)的材料不同的材料形成。此外,提出一种用于制造这种半导体本体(14)和带有这种半导体本体(14)的器件的方法。
Description
技术领域
本发明涉及一种发射辐射的半导体本体、一种用于制造发射辐射的半导体本体的方法和一种发射辐射的半导体器件。
背景技术
参考文献EP 1 657 757 A2描述带有发射辐射的半导体本体的发射辐射的半导体器件,所述半导体本体借助于例如为超声波摩擦焊接或热压缩的接合方法经由后侧的电接触部导电地施加到芯片承载体上。
为了制造后侧的接触部,例如在参考文献US 2005/0247944 A1中描述,借助于球形焊接器在半导体本体上依次施加各个导电接触部。该制造方法由于连续的过程控制是相对耗费时间的。
发明内容
本发明的目的是提出一种半导体本体,所述半导体本体适合借助于尤其为超声波摩擦焊接或热压缩的接合方法施加到芯片承载体上。此外,本发明的目的是提供一种用于制造这种半导体本体的简化的方法。本发明的另一目的在于提供一种带有这种发射辐射的半导体本体的发射辐射的器件。
所述目的通过带有权利要求1的特征的半导体本体、通过带有权利要求8的步骤的方法并且通过带有权利要求14的特征的发射辐射的半导体器件来实现。
有利的改进形式和实施形式分别在从属权利要求中说明。
发射辐射的半导体本体尤其包括:
-外延的半导体层序列,其带有适合产生电磁辐射的有源区,
-承载层,所述承载层设置成机械地稳固外延的半导体层序列,和
-接触结构,以用于电接触半导体本体,所述接触结构分别具有体积区域和表面接合区域。此外,表面接合区域由与体积区域的材料不同的材料形成。
表面接合区域尤其适合借助于例如为超声波摩擦焊接和/或热压缩的接合方法与芯片承载体连接。尤其优选的是,芯片承载体和表面接合区域之间的连接构成为是导电的。尤其优选的是,表面接合区域构成为是能够被超声波摩擦焊接的和/或是能够被热压缩的,也就是说,所述表面接合区域能够借助于超声波摩擦焊接和/或热压缩与芯片承载体连接。
接触结构优选设置在半导体本体的后侧上,其中后侧与半导体本体的发射辐射的前侧相对置。
根据一个实施形式,总是分别通过唯一的体积区域和唯一的表面接合区域形成唯一的接触结构。
承载层优选地构成为是金属的并且例如具有下述材料中的至少一种或者由这些材料中的至少一种制成:镍、钼、铜。所述材料例如能够借助于电镀工艺施加到外延的半导体层序列上。
根据发射辐射的半导体本体的一个实施形式,体积区域由与承载层相同的材料形成。对此,不强制认为接触结构的体积区域例如通过如下面详细地说明的减成法由承载层的材料形成。相反也可能的是,为了形成接触结构的体积区域,以结构化的方式将另外的层施加到承载层上,所述另外的层具有与承载层的相同的材料或者由相同的材料制成。
在此也可能的是,体积区域的材料和承载层的材料稍微彼此不同,例如基于不同的或依次进行的制造工艺。
尤其优选地,另外的层具有例如为镍、钼或铜的金属材料或者由所述材料中的一种制成。
根据发射辐射的半导体本体的另一个实施形式,接触结构通过突出部构成,所述突出部分别优选具有20μm和200μm之间的宽度,其中包括边界值。
根据发射辐射的半导体本体的另一个实施形式,接触结构通过突出部形成,所述突出部分别优选具有5μm和50μm之间的高度,其中包括边界值。
根据发射辐射的半导体本体的另一个实施形式,表面接合区域具有下述材料中的至少一种或者由下述材料中的至少一种制成:金、铜、铝。尤其优选地的是在此使用金,因为其例如为延展性的材料特性尤其好地适合于超声波摩擦焊接和热压缩的接合方法。此外有利的是,与例如为铜或铝的其他金属不同的是,金在其表面上最多具有极其少的氧化层,使得能够取消在超声波摩擦焊接或热压缩之前去除氧化层的步骤,该步骤如通常例如在使用铜或铝的情况下执行。
如果将铜或铝用于表面接合区域,那么用于例如借助于超声波摩擦焊接或热压缩尤其优选在由惰性气体例如氮气或稀有气体组成的保护气氛下执行将半导体本体与芯片承载体连接的后续的连接步骤。
根据发射辐射的半导体本体的另一个实施形式,接触结构通过突出部形成,其中表面区域分别在两侧突出于体积区域。在此,接触结构例如通过蘑菇状的突出部形成,其中体积区域构成蘑菇的茎并且表面接合区域构成蘑菇的盖。如下面详细地说明,蘑菇形的突出部尤其能够通过经由光刻胶掩膜对表面接合区域进行电镀沉积来产生。因为电镀沉积工艺通常具有各向同性的特征,在此构成带有倒圆的棱边的盖形结构。
根据发射辐射的半导体本体的另一个实施形式,接触结构分别具有矩形的、正方形的、圆的或环形的基面。
用于制造半导体本体的方法尤其包括下述步骤:
-提供带有有源区的外延的半导体层序列,所述有源区适合产生电磁辐射,
-将承载层施加到外延的半导体层序列的主侧上,其中承载体设置用于机械地稳固外延的半导体层序列,
-施加能够接合的层,
-借助于光刻法在承载体上构成接触结构,其中接触结构分别具有体积区域和表面接合区域。
外延的半导体层序列通常在适合的生长衬底上外延地生长。
在施加承载层之后通常将生长衬底从外延的半导体层序列中去除或者打薄,使得生长衬底单独不适合于机械地稳固外延的半导体层序列。
生长衬底例如通过抛光、刻蚀或借助于激光剥离工艺从外延的半导体层序列去除或者相应地打薄。
承载层、尤其是金属的承载层例如借助于电镀沉积工艺、溅镀或蒸镀施加到外延的半导体层序列上。
尤其当能够接合的层具有金属材料时,所述能够接合的层例如同样通过电镀工艺、通过溅镀或蒸镀产生。优选地,表面接合区域由能够接合的层的材料形成。
能够接合的层尤其优选地构成为是能够被超声波摩擦焊接的和/或能够被热压缩的。尤其地,能够接合的层具有下述材料中的至少一种或者由下述材料中的至少一种制成:金、铜、铝。
根据方法的一个实施形式,在承载层和能够接合的层之间将另外的层施加到承载层上。所述另外的层优选地具有与承载层相同的材料。尤其优选地,所述另外的层由与承载层相同的材料形成,也就是说,另外的层的材料成分在制造公差之内不显著地与承载层的材料成分不同。然而,由于用于制造承载层和另外的层的不同的制造工艺技术或两个依次紧随的工艺步骤而能够在两个层的材料成分中出现细微的偏差。
根据方法的另一个实施形式,接触结构的体积区域由另外的层的材料形成。方法的所述实施形式是加成法,因为以附加层的形式提供形成接触结构的体积区域的材料。
为了形成接触结构,例如将光刻胶层施加到承载层上,所述光刻胶层空出应当在其中形成接触结构的突出部的区域。随后,——例如以电镀方式——沉积另外的层,使得其在光刻胶层之内填充空出的区域。在此可能的是,另外的层完全地或仅部分地填充光刻胶层之内的整个留空部。为了形成表面接合区域,因此在方法的该实施形式中优选地沉积另外的能够接合的层,所述另外的能够接合的层同样遵循通过光刻胶层预设的结构化。最后,去除光刻胶层,使得接触结构仅以带有各一个体积区域和各一个表面接合区域的突出部的形式保留在承载层上。
替选于上述加成法,也能够执行减成法。在减成法中,接触结构的体积区域直接由承载层的材料形成,例如通过刻蚀。
此处所述方法的特别的优点在于,所述方法能够在晶圆级上、也就是说在分割半导体本体之前执行。这允许简单地并且快速地制造接触结构。此外,由于光结构化而可在并行的工艺中产生接触结构。
所实现的接触结构还是良好地导热和导电的,并且能够在少许工艺步骤中实现。此外,在用于制造接触结构的方法中,仅有少量的热输入到半导体本体中并且尤其输入到带有产生辐射的有源区的半导体层序列中。此外,此处提出的制造方法通常使得接下来清洗半导体本体是多余的。
根据另一个实施形式,能够接合的层以直接接触的方式施加到承载层上。
发射辐射的半导体器件例如能够通过将上述发射辐射的半导体本体施加到芯片承载体上来制造。尤其优选地,半导体本体借助于超声波摩擦焊接或热压缩施加在芯片承载体上。为此,承载体优选具有接触区域,所述接触区域设置为待与半导体本体的接触结构连接。接触区域优选地具有金属化部,所述金属化部是能够被超声波摩擦焊接的和/或是能够被热压缩的。对此,例如由下述金属中的一种制成的或具有下述金属中的一种的金属化部是适合的:金、铜、铝。
有利地,例如与借助粘接或者钎焊相比,多个半导体本体能够借助超声波摩擦焊接或热压缩的接合方法以彼此间更小的间距例如固定在承载体上。
根据发射辐射的半导体器件的另一个实施形式,至少在接触结构之间引入电绝缘的填充材料。填充材料优选地在施加到承载体上之后引入到接触结构之间。
附图说明
本发明的其他有利的实施形式和改进形式从以下结合附图描述的实施例中得出。
图1A至1G示出在根据第一实施例的不同的方法步骤期间的晶圆复合物的示意剖面图。
图2示出根据一个实施例的半导体本体的示意剖面图。
图3A和3B分别示出在根据两个不同的实施例的半导体本体的示意俯视图。
图4A至4F示出在根据另一实施例的不同的方法步骤期间的晶圆复合物的示意剖面图。
图5A至5E示出在根据另一实施例的不同的方法步骤期间的晶圆复合物的示意剖面图。
图6A至6H示出在根据另一实施例的不同的方法步骤期间的晶圆复合物的示意剖面图。
图7A至7D示出在根据一个实施例的不同的方法步骤期间的发射辐射的半导体器件的示意剖面图。
具体实施方式
相同的、相同类型的或起相同作用的元件在附图中设有相同的附图标记。附图和在附图中描述的元件彼此间的尺寸比例不能够看作是按照比例的。相反地,为了更好的可视性和/或为了更好的理解,能够夸张大地示出各个元件、尤其是层厚度。
图1A示出承载层1,在所述承载层的第一主侧2上设置有外延的半导体层序列3。承载层1机械地稳固半导体层序列3。外延的半导体层序列3目前已经在芯片区域中被结构化,其中每一个芯片区域随后是完成的半导体本体的一部分。外延的半导体层序列3具有适合产生电磁辐射的有源区4(在图1A至1G中没有示出)。
尤其优选地,另一层10构成为金属的并且具有与承载层1相同的材料,例如镍、钼、铜。
承载层1目前构成为金属的并且例如具有镍、钼、铜。
有源区4优选包括pn结、双异质结构、单量子阱或者尤其优选多量子阱结构(MQW)以用于产生辐射。术语量子阱结构在此不包括关于量子化的维数的说明。因此,所述量子阱结构还包括量子阱、量子线和量子点和所述结构的任意的组合。
在承载层1和结构化的外延的半导体层序列3之间设置层5。所述层5例如能够是接合层以用于将外延的半导体层序列3与承载层1连接,所述接合层例如具有焊料或粘合剂。此外,如果承载层1电镀地生长,那么层5也能够是金属的起始层。
如图1B示例地示出,将光刻胶层7施加到承载层1的与第一主侧2对置的第二主侧6上。
现在将光刻胶层7结构化,使得在光刻胶层7中出现开口8,所述开口完全地穿透光刻胶层7(图1C)。光刻胶层7中的开口8预设随后产生的接触结构9的形状。
在图1D中示出的下一方法步骤中,在光刻胶层7上沉积另外的层10,其中另外的层10的材料完全地填充光刻胶层7中的开口8直至光刻胶层7的边缘。因此,另外的层10根据光刻胶层7以结构化的方式施加到承载层1上。接触结构9的体积区域11由金属层10的材料形成。因此,根据图1A至1G的实施例的方法是加成法。
尤其优选地,另外的层10构成为金属的并且具有与承载层1相同的材料,例如镍、钼、铜。
在另一方法步骤中,现在将能够接合的层11施加到另外的层10上(图1E)。能够接合的层11优选地构成为是能够被超声波摩擦焊接的和/或是能够被热压缩的并且具有下述材料中的一种:金、铜、铝。例如借助于电镀沉积工艺施加能够接合的层11。在此,另外的层10的表面形成用于沉积能够接合的层11的起点,使得在此从位于其下方的结构化的另外的层10出发形成盖形结构。
在图1F中示意地描述的下一步骤中,去除光刻胶层7。以该方式和方法在承载层1的第二主侧6上形成接触结构9,所述接触结构分别具有体积区域12和表面接合区域13。表面区域13在此由能够接合的层11的材料形成。如果能够接合的层11因此是能够被超声波摩擦焊接的和/或是能够被热压缩的,那么表面区域13也是能够被超声波摩擦焊接的和/或是能够被热压缩的。
在下一步骤中,将晶圆复合物分割成各个半导体本体14(图1G)。
借助于根据图1A至1G的方法,例如能够制造如在图2中示意示出的发射辐射的半导体本体14。
根据图2的实施例的半导体本体14具有外延生长的半导体层序列3,所述半导体层序列3包括有源区4。外延的半导体层序列3设置在承载层1的第一主侧2上,其中承载层1用于机械地稳固外延的半导体层序列3。在外延的半导体层序列3和承载层1之间设置有层5。
在承载层1的第二主侧6上设置有接触结构9。接触结构9包括体积区域12,所述体积区域由与承载层1相同的材料形成。此外,接触结构9包括表面接合区域13,所述表面接合区域优选地构成为是能够被超声波摩擦焊接的和/或是能够被热压缩的。接触结构91的表面接合区域13目前设置为与体积区域12直接接触。此外,接触结构9的体积区域12设置为与承载层1直接接触。
在根据图2的半导体本体14中,接触结构9通过蘑菇形的突出部形成,其中体积区域12构成蘑菇的茎并且表面接合区域13构成蘑菇的盖。因此,表面接合区域13侧向地突出于体积区域12并且具有倒圆的棱边。
如同在图3A中示例示出的半导体本体的俯视图,接触结构9的基面能够分别构成为矩形的或正方形的。此外,接触结构9的基面也能够构成为圆的或环绕的(图3B)。
以下根据图4A至4F描述用于制造接触结构9的加成法的另一个实施例。在此,根据图4A至4C的方法步骤基本上相当于根据图1A至1C的方法步骤。
然而,与根据图1A至1G的实施例的方法不同的是,另外的层10沉积在结构化的光刻胶层7上,使得所述另外的层的材料仅部分地填充光刻胶层7中的开口8(图4D)。在下一步骤中,现在施加能够接合的层11,其中所述能够接合的层也不完全地填充开口8的剩余高度(图4E)。
在下一步骤中,现在去除光刻胶层7(图4F),并且分割半导体本体14(没有示出)。
以该方式和方法形成接触结构9,其中与根据图2的接触结构9相对地,表面接合区域13在侧向上与体积区域12一起终止。
以下根据图5A至5E详细阐明加成法的一个实施例。
图5A示出已经在各个芯片区域中结构化的外延的半导体层序列3,所述半导体层序列3设置在承载层1上。在承载层1和外延的半导体层序列3之间设置例如能够是反射层的层5。
与图1A和4A不同的是,在根据图5A的晶圆复合物中,在承载层1的第二主侧6上以非结构化的方式施加例如由金制成的能够接合的层11。如在图5B中可见,将光刻胶层7施加到能够接合的层11上,所述光刻胶层接下来根据期望的接触结构9来结构化(图5C)。光刻胶层7在此对应于随后要产生的接触结构9而具有开口8,所述开口8完全穿透光刻胶层7。
在下一步骤中,能够接合的层11和承载层1的一部分根据已结构化的光刻胶层7例如借助于湿法化学刻蚀来结构化(图5D)。此后再次去除光刻胶层7(图5E)。
在该方法中也形成接触结构9,所述接触结构中的每个具有体积区域12和表面接合区域13。在此,表面接合区域13侧向地与体积区域12一起终止。
以下将根据图6A至6H描述减成法的另一个实施例。根据图6A至6C的方法步骤在此基本上相当于根据图1A至1C的方法步骤。
然而,与根据图1A至1G的方法不同的是,在将光刻胶层7结构化之后不施加另外的层10,而是例如借助于刻蚀去除承载层1的在光刻胶层7的开口8之内的材料本身(图6D)。在去除光刻胶层7之后,如在图6E中示出,以该方式和方法形成随后的接触结构9的体积区域12。
在下一步骤中,将另外的光刻胶层15以结构化的方式施加到承载层1的第二主侧6上,使得另外的光刻胶层15的材料完全地填充在接触结构9的体积区域12之间的凹部(图6F)。
在下一步骤中,现在将能够接合的层11例如通过电镀沉积施加到另外的光刻胶层15上(图6G)。
由此在去除第二光刻胶层15之后形成接触结构9,其中每个接触结构91由体积区域12和表面接合区域13形成。体积区域12在此由承载层1的材料制成并且表面接合区域13优选地具有能够被热压缩的和/或能够被超声波摩擦焊接的材料,所述材料优选地不同于体积区域12的材料(图6H)。
在根据图7A至7D的实施例的方法中,在第一步骤中提供芯片承载体16,在所述芯片承载体上,在接触区域17之内施加优选是能够被超声波摩擦焊接的和/或是能够被热压缩的金属化部(图7A)。
在第二步骤中,例如能够借助于上述方法中的一种制造的半导体本体14借助于例如为超声波摩擦焊接和/或热压缩的接合方法经由其后侧的接触结构9与芯片承载体16的接触区域17导电地连接(图7B),其中所述接触结构优选具有能够被超声波摩擦焊接的和/或能够被热压缩的表面接合区域13。半导体本体14在前侧借助于接合线18与芯片承载体16上的焊盘19电接触(图7C)。
在下一步骤中,如在图7D中示例地示出,将填充材料20引入到芯片承载体16和构成接触结构9的突出部之间。例如能够用作填充材料20的是下述材料中的一种:例如热固性的环氧树脂、硅树脂、例如包括环氧树脂和硅树脂的混合材料。根据一个实施形式,填充材料20具有例如二氧化钛的填充材料。
本申请要求德国专利申请DE 10 2010 023 343.9的优先权,其内容在此通过引用并入本文。
本发明没有通过根据实施例进行的描述而限制于此。相反地,本发明包括每个新特征以及特征的任意的组合,这尤其包括权利要求中的特征的任意的组合,即使所述特征或所述组合自身没有明确地在权利要求或实施例中说明也如此。
Claims (15)
1.发射辐射的半导体本体(14),带有:
-外延的半导体层序列(3),所述外延的半导体层序列带有适合产生电磁辐射的有源区(4),
-承载层(1),所述承载层设置成机械地稳固所述外延的半导体层序列(3),和
-接触结构(9,91),所述接触结构用于电接触所述半导体本体(14),所述接触结构分别具有体积区域(12)和表面接合区域(13),其中所述表面接合区域(13)由与所述体积区域(12)的材料不同的材料形成。
2.根据上一项权利要求所述的发射辐射的半导体本体(14),其中所述体积区域(12)由与所述承载层(1)相同的材料形成。
3.根据上述权利要求之一所述的发射辐射的半导体本体,其中所述承载层(1)具有金属材料,所述金属材料优选地选自下述材料:镍、钼、铜。
4.根据上述权利要求之一所述的发射辐射的半导体本体(14),其中所述表面接合区域(13)具有下述材料中的至少一种:金、铜、铝。
5.根据上述权利要求之一所述的发射辐射的半导体本体(14),其中所述接触结构(9)通过突出部形成,所述突出部分别具有20μm和200μm之间的宽度和/或5μm和50μm之间的高度,其中包括边界值。
6.根据上述权利要求之一所述的发射辐射的半导体本体(14),其中所述接触结构(9)通过突出部形成,其中所述表面接合区域分别在两侧突出于所述体积区域。
7.根据上述权利要求之一所述的发射辐射的半导体本体(14),其中所述表面接合区域构成为能够被超声波摩擦焊接的和/或是能够被热压缩的。
8.用于制造发射辐射的半导体本体(14)的方法,具有以下步骤:
-提供带有有源区(4)的外延的半导体层序列(3),所述有源区适合产生电磁辐射,
-将承载层(1)施加到所述外延的半导体层序列(3)的主侧上,其中所述承载层(1)设置为用于机械地稳固所述外延的半导体层序列(3),
-施加能够接合的层(11),
-在所述承载层(1)上借助于光刻法构造接触结构(9),其中所述接触结构(9)分别具有体积区域(12)和表面接合区域(13)。
9.根据上一项权利要求所述的方法,其中在所述承载层(1)和所述能够接合的层(11)之间施加由与所述承载层(1)相同的材料制成的另外的层(10),并且所述承载层(1)的材料优选地构成为是金属的。
10.根据上一项权利要求所述的方法,其中所述接触结构(9)的所述体积区域(12)由所述另外的层(10)的材料形成。
11.根据权利要求8所述的方法,其中所述接触结构(9)的所述体积区域(12)由所述承载层(1)的材料形成。
12.根据上一项权利要求所述的方法,其中所述能够接合的层(11)以直接接触的方式施加到所述承载层(1)上。
13.根据权利要求8至12之一所述的方法,其中所述表面接合区域和/或所述能够接合的层构成为能够被超声波摩擦焊接的和/或是能够被热压缩的。
14.具有根据权利要求1至7之一所述的发射辐射的半导体本体(14)的发射辐射的半导体器件,所述半导体本体施加到芯片承载体(16)上。
15.根据上一个权利要求所述的发射辐射的半导体器件,其中所述半导体本体(14)借助于超声波摩擦焊接或热压缩施加到所述芯片承载体(16)上。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102010023343.9 | 2010-06-10 | ||
DE102010023343A DE102010023343A1 (de) | 2010-06-10 | 2010-06-10 | Strahlungsemittierender Halbleiterkörper, Verfahren zur Herstellung eines strahlungsemittierenden Halbleiterkörpers und strahlungsemittierendes Halbleiterbauelement |
PCT/EP2011/059485 WO2011154441A1 (de) | 2010-06-10 | 2011-06-08 | Strahlungsemittierender halbleiterkörper, verfahren zur herstellung eines strahlungsemittierenden halbleiterkörpers und strahlungsemittierendes halbleiterbauelement |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102934244A true CN102934244A (zh) | 2013-02-13 |
CN102934244B CN102934244B (zh) | 2015-11-25 |
Family
ID=44356273
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201180028669.6A Active CN102934244B (zh) | 2010-06-10 | 2011-06-08 | 发射辐射的半导体本体、用于制造发射辐射的半导体本体的方法和发射辐射的半导体器件 |
Country Status (8)
Country | Link |
---|---|
US (1) | US8816375B2 (zh) |
EP (2) | EP2580792B1 (zh) |
JP (1) | JP5749336B2 (zh) |
KR (1) | KR20130058720A (zh) |
CN (1) | CN102934244B (zh) |
DE (1) | DE102010023343A1 (zh) |
TW (1) | TW201214773A (zh) |
WO (1) | WO2011154441A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107389178A (zh) * | 2016-04-05 | 2017-11-24 | 欧司朗股份有限公司 | 声学传感器 |
CN109390282A (zh) * | 2012-11-23 | 2019-02-26 | 奥斯兰姆奥普托半导体有限责任公司 | 用于将复合体分割成半导体芯片的方法和半导体芯片 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102013212928A1 (de) * | 2013-07-03 | 2015-01-08 | Osram Opto Semiconductors Gmbh | Verfahren zum Herstellen eines optoelektronischen Bauelements |
DE102015105666A1 (de) * | 2015-04-14 | 2016-10-20 | Osram Opto Semiconductors Gmbh | Verfahren zur Montage eines ersten Bauteils auf einem zweiten Bauteil und Verfahren zur Herstellung einer elektronischen Vorrichtung mit einem ersten Bauteil und einem zweiten Bauteil |
DE102015112280A1 (de) * | 2015-07-28 | 2017-02-02 | Osram Opto Semiconductors Gmbh | Bauelement mit einem metallischen Träger und Verfahren zur Herstellung von Bauelementen |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
CN1445869A (zh) * | 2002-03-14 | 2003-10-01 | 株式会社东芝 | 半导体发光芯片及半导体发光器件 |
US20080135859A1 (en) * | 2006-12-08 | 2008-06-12 | Samsung Electro-Mechanics Co., Ltd | Vertical structure led device and method of manufacturing the same |
US7687322B1 (en) * | 2005-10-11 | 2010-03-30 | SemiLEDs Optoelectronics Co., Ltd. | Method for removing semiconductor street material |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08115989A (ja) * | 1994-08-24 | 1996-05-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5779924A (en) * | 1996-03-22 | 1998-07-14 | Hewlett-Packard Company | Ordered interface texturing for a light emitting device |
US6562660B1 (en) * | 2000-03-08 | 2003-05-13 | Sanyo Electric Co., Ltd. | Method of manufacturing the circuit device and circuit device |
TW507482B (en) * | 2000-06-09 | 2002-10-21 | Sanyo Electric Co | Light emitting device, its manufacturing process, and lighting device using such a light-emitting device |
TW511422B (en) * | 2000-10-02 | 2002-11-21 | Sanyo Electric Co | Method for manufacturing circuit device |
US6900476B2 (en) | 2001-11-30 | 2005-05-31 | Osram Opto Semiconductors Gmbh | Light-emitting semiconductor component |
JP3705791B2 (ja) | 2002-03-14 | 2005-10-12 | 株式会社東芝 | 半導体発光素子および半導体発光装置 |
JP2004235505A (ja) | 2003-01-31 | 2004-08-19 | Shin Etsu Handotai Co Ltd | 発光素子及び半導体素子用オーミック電極構造 |
US7427805B2 (en) * | 2003-10-14 | 2008-09-23 | Shen Ming-Tung | Light-emitting diode chip package body and packaging method thereof |
US20050247944A1 (en) | 2004-05-05 | 2005-11-10 | Haque Ashim S | Semiconductor light emitting device with flexible substrate |
JP2006066449A (ja) | 2004-08-24 | 2006-03-09 | Toshiba Corp | 半導体発光素子 |
US7419839B2 (en) | 2004-11-12 | 2008-09-02 | Philips Lumileds Lighting Company, Llc | Bonding an optical element to a light emitting device |
US20060154393A1 (en) | 2005-01-11 | 2006-07-13 | Doan Trung T | Systems and methods for removing operating heat from a light emitting diode |
TWI422044B (zh) | 2005-06-30 | 2014-01-01 | Cree Inc | 封裝發光裝置之晶片尺度方法及經晶片尺度封裝之發光裝置 |
TWI274430B (en) * | 2005-09-28 | 2007-02-21 | Ind Tech Res Inst | Light emitting device |
JP2007288050A (ja) * | 2006-04-19 | 2007-11-01 | Shinko Electric Ind Co Ltd | 半導体装置および半導体装置の製造方法 |
TW200933755A (en) | 2008-01-18 | 2009-08-01 | Advanced Semiconductor Eng | Chip package process and structure thereof |
KR100999736B1 (ko) * | 2010-02-17 | 2010-12-08 | 엘지이노텍 주식회사 | 발광 소자, 발광 소자 제조방법 및 라이트 유닛 |
-
2010
- 2010-06-10 DE DE102010023343A patent/DE102010023343A1/de not_active Withdrawn
-
2011
- 2011-05-19 TW TW100117534A patent/TW201214773A/zh unknown
- 2011-06-08 KR KR1020137000600A patent/KR20130058720A/ko not_active Application Discontinuation
- 2011-06-08 EP EP11723981.4A patent/EP2580792B1/de active Active
- 2011-06-08 CN CN201180028669.6A patent/CN102934244B/zh active Active
- 2011-06-08 US US13/698,302 patent/US8816375B2/en active Active
- 2011-06-08 EP EP18158977.1A patent/EP3349260B1/de active Active
- 2011-06-08 WO PCT/EP2011/059485 patent/WO2011154441A1/de active Application Filing
- 2011-06-08 JP JP2013513673A patent/JP5749336B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
CN1445869A (zh) * | 2002-03-14 | 2003-10-01 | 株式会社东芝 | 半导体发光芯片及半导体发光器件 |
US7687322B1 (en) * | 2005-10-11 | 2010-03-30 | SemiLEDs Optoelectronics Co., Ltd. | Method for removing semiconductor street material |
US20080135859A1 (en) * | 2006-12-08 | 2008-06-12 | Samsung Electro-Mechanics Co., Ltd | Vertical structure led device and method of manufacturing the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109390282A (zh) * | 2012-11-23 | 2019-02-26 | 奥斯兰姆奥普托半导体有限责任公司 | 用于将复合体分割成半导体芯片的方法和半导体芯片 |
CN109390282B (zh) * | 2012-11-23 | 2023-07-25 | 奥斯兰姆奥普托半导体有限责任公司 | 用于将复合体分割成半导体芯片的方法和半导体芯片 |
CN107389178A (zh) * | 2016-04-05 | 2017-11-24 | 欧司朗股份有限公司 | 声学传感器 |
Also Published As
Publication number | Publication date |
---|---|
JP2013529394A (ja) | 2013-07-18 |
US8816375B2 (en) | 2014-08-26 |
CN102934244B (zh) | 2015-11-25 |
EP3349260B1 (de) | 2019-09-18 |
WO2011154441A1 (de) | 2011-12-15 |
KR20130058720A (ko) | 2013-06-04 |
EP2580792B1 (de) | 2018-05-16 |
DE102010023343A1 (de) | 2011-12-15 |
US20130134473A1 (en) | 2013-05-30 |
TW201214773A (en) | 2012-04-01 |
EP2580792A1 (de) | 2013-04-17 |
JP5749336B2 (ja) | 2015-07-15 |
EP3349260A1 (de) | 2018-07-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI385825B (zh) | 光電元件及其製造方法 | |
KR101681242B1 (ko) | 발광다이오드의 제조방법 및 이에 의해 제조된 발광다이오드 | |
US9978918B2 (en) | Method for producing an optoelectronic device | |
CN102934244B (zh) | 发射辐射的半导体本体、用于制造发射辐射的半导体本体的方法和发射辐射的半导体器件 | |
US10170675B2 (en) | P—N separation metal fill for flip chip LEDs | |
CN102460742B (zh) | 光电子半导体本体或光电子半导体芯片的能用于高电流的接触 | |
WO2014048988A1 (de) | Verfahren zur herstellung eines optoelektronischen bauelements | |
KR20160013875A (ko) | 복수의 광전자 반도체 칩을 제조하는 방법 및 광전자 반도체 칩 | |
US20180219146A1 (en) | Method for producing a component, and a component | |
TW200822197A (en) | Method of super flat chemical mechanical polishing (SF-CMP) technology for thin film GAN devices and semiconductor produced thereof | |
CN103515254A (zh) | 芯片布置组件及用于形成芯片布置组件的方法 | |
US11038083B2 (en) | Optoelectronic semiconductor chip | |
US11195974B2 (en) | Semiconductor chips and method for producing semiconductor chips | |
CN115210883A (zh) | 包括金属网格的激光剥离加工系统 | |
CN102891127A (zh) | 电子部件 | |
KR101806806B1 (ko) | 전자 소자 탑재용 기판의 제조방법 | |
US10483444B2 (en) | Method of producing an optoelectronic semiconductor component, optoelectronic semiconductor component, and temporary carrier | |
CN104704642B (zh) | 用于制造光电子器件的方法 | |
KR20220106786A (ko) | 기판 접합 | |
CN117337481A (zh) | 半导体元件和其制造方法 | |
CN1964083A (zh) | 发光二极管及其电极压焊点的形成方法 | |
KR20080028068A (ko) | 플립본딩형 발광소자 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |