CN102844861B - 对用于裸片翘曲减少的组装的ic封装衬底的tce补偿 - Google Patents

对用于裸片翘曲减少的组装的ic封装衬底的tce补偿 Download PDF

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CN102844861B
CN102844861B CN201180019483.4A CN201180019483A CN102844861B CN 102844861 B CN102844861 B CN 102844861B CN 201180019483 A CN201180019483 A CN 201180019483A CN 102844861 B CN102844861 B CN 102844861B
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die
substrate
dies
coefficient
thermal expansion
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CN102844861A (zh
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玛格丽特·罗丝·西蒙斯-马修斯
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H10P72/7418—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. a chip mounting substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/314—Bonding techniques, e.g. hybrid bonding characterized by direct bonding of pads or other interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
CN201180019483.4A 2010-04-29 2011-04-29 对用于裸片翘曲减少的组装的ic封装衬底的tce补偿 Active CN102844861B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/770,058 US8298863B2 (en) 2010-04-29 2010-04-29 TCE compensation for package substrates for reduced die warpage assembly
US12/770,058 2010-04-29
PCT/US2011/034444 WO2011139875A2 (en) 2010-04-29 2011-04-29 Tce compensation for ic package substrates for reduced die warpage assembly

Publications (2)

Publication Number Publication Date
CN102844861A CN102844861A (zh) 2012-12-26
CN102844861B true CN102844861B (zh) 2016-01-13

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Country Status (4)

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US (3) US8298863B2 (https=)
JP (1) JP2013526066A (https=)
CN (1) CN102844861B (https=)
WO (1) WO2011139875A2 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227295B2 (en) * 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8786066B2 (en) 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
US8796075B2 (en) * 2011-01-11 2014-08-05 Nordson Corporation Methods for vacuum assisted underfilling
US9443783B2 (en) * 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US10153179B2 (en) 2012-08-24 2018-12-11 Taiwan Semiconductor Manufacturing Company Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
KR20140110334A (ko) * 2013-03-07 2014-09-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP2014179419A (ja) * 2013-03-14 2014-09-25 Alpha- Design Kk 電子部品の接合方法
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US20150014852A1 (en) * 2013-07-12 2015-01-15 Yueli Liu Package assembly configurations for multiple dies and associated techniques
US9892970B2 (en) 2016-06-02 2018-02-13 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
US9929085B2 (en) 2016-06-02 2018-03-27 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
WO2018013086A1 (en) 2016-07-12 2018-01-18 Hewlett-Packard Development Company, L.P. Composite wafers
KR102649471B1 (ko) 2016-09-05 2024-03-21 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US9966363B1 (en) * 2017-02-03 2018-05-08 Nanya Technology Corporation Semiconductor apparatus and method for preparing the same
US10396003B2 (en) * 2017-10-18 2019-08-27 Micron Technology, Inc. Stress tuned stiffeners for micro electronics package warpage control
US10548230B2 (en) * 2018-01-04 2020-01-28 Micron Technology, Inc. Method for stress reduction in semiconductor package via carrier
CN111989771A (zh) * 2018-02-19 2020-11-24 迪德鲁科技(Bvi)有限公司 制造玻璃框架扇出型封装的系统和方法
US10692793B2 (en) * 2018-03-02 2020-06-23 Micron Technology, Inc. Electronic device with a package-level thermal regulator mechanism and associated systems, devices, and methods
CN110634806A (zh) * 2018-06-21 2019-12-31 美光科技公司 半导体装置组合件和其制造方法
US11694906B2 (en) 2019-09-03 2023-07-04 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US12412862B2 (en) * 2021-04-28 2025-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6284573B1 (en) * 1998-05-21 2001-09-04 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US20030199121A1 (en) * 2000-07-27 2003-10-23 Caletka David Vincent Wafer scale thin film package
US20050099783A1 (en) * 2001-03-28 2005-05-12 International Business Machines Corporation Hyperbga buildup laminate
TWI245381B (en) * 2003-08-14 2005-12-11 Via Tech Inc Electrical package and process thereof
TWI254425B (en) * 2004-10-26 2006-05-01 Advanced Semiconductor Eng Chip package structure, chip packaging process, chip carrier and manufacturing process thereof
US20070155048A1 (en) * 2005-12-29 2007-07-05 Micron Technology, Inc. Methods for packaging microelectronic devices and microelectronic devices formed using such methods
US20070273046A1 (en) * 2005-09-09 2007-11-29 Horst Theuss Semiconductor component with connecting elements and method for producing the same
US20080048343A1 (en) * 2000-12-06 2008-02-28 Micron Technology, Inc. Thin flip-chip method
TW200824060A (en) * 2006-11-17 2008-06-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US20080179758A1 (en) * 2007-01-25 2008-07-31 Raytheon Company Stacked integrated circuit assembly
US20100072606A1 (en) * 2008-09-25 2010-03-25 Wen-Kun Yang Stacking Package Structure with Chip Embedded Inside and Die Having Through Silicon Via and Method of the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003092375A (ja) * 2001-09-19 2003-03-28 Matsushita Electric Ind Co Ltd 半導体装置、その製造方法およびその検査方法
JP3831287B2 (ja) * 2002-04-08 2006-10-11 株式会社日立製作所 半導体装置の製造方法
KR100555505B1 (ko) * 2003-07-09 2006-03-03 삼성전자주식회사 실리사이드층의 증착 및 제거에 의해서 콘택홀 바닥에서확장된 오픈 선폭을 구현하는 연결 콘택 형성 방법
JP4527991B2 (ja) * 2004-01-28 2010-08-18 株式会社日立製作所 マルチチップモジュールの製造方法
US7256483B2 (en) * 2004-10-28 2007-08-14 Philips Lumileds Lighting Company, Llc Package-integrated thin film LED
JP4790297B2 (ja) * 2005-04-06 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR100688560B1 (ko) * 2005-07-22 2007-03-02 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
JP5065586B2 (ja) * 2005-10-18 2012-11-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4390775B2 (ja) * 2006-02-08 2009-12-24 Ｏｋｉセミコンダクタ株式会社 半導体パッケージの製造方法
US7473577B2 (en) 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US7846776B2 (en) * 2006-08-17 2010-12-07 Micron Technology, Inc. Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods
US20080188037A1 (en) 2007-02-05 2008-08-07 Bridge Semiconductor Corporation Method of manufacturing semiconductor chip assembly with sacrificial metal-based core carrier
US8012857B2 (en) * 2007-08-07 2011-09-06 Semiconductor Components Industries, Llc Semiconductor die singulation method
TWI375321B (en) * 2007-08-24 2012-10-21 Xintec Inc Electronic device wafer level scale packages and fabrication methods thereof
JP2009117767A (ja) * 2007-11-09 2009-05-28 Shinko Electric Ind Co Ltd 半導体装置の製造方法及びそれにより製造した半導体装置
US20100090339A1 (en) * 2008-09-12 2010-04-15 Kumar Ananda H Structures and Methods for Wafer Packages, and Probes
US8237257B2 (en) * 2008-09-25 2012-08-07 King Dragon International Inc. Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US7863092B1 (en) * 2008-09-30 2011-01-04 Xilinx, Inc. Low cost bumping and bonding method for stacked die
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof
KR101698805B1 (ko) * 2010-03-23 2017-02-02 삼성전자주식회사 웨이퍼 레벨의 패키지 방법 및 그에 의해 제조되는 반도체 소자

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US6284573B1 (en) * 1998-05-21 2001-09-04 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US20030199121A1 (en) * 2000-07-27 2003-10-23 Caletka David Vincent Wafer scale thin film package
US20080048343A1 (en) * 2000-12-06 2008-02-28 Micron Technology, Inc. Thin flip-chip method
US20050099783A1 (en) * 2001-03-28 2005-05-12 International Business Machines Corporation Hyperbga buildup laminate
TWI245381B (en) * 2003-08-14 2005-12-11 Via Tech Inc Electrical package and process thereof
TWI254425B (en) * 2004-10-26 2006-05-01 Advanced Semiconductor Eng Chip package structure, chip packaging process, chip carrier and manufacturing process thereof
US20070273046A1 (en) * 2005-09-09 2007-11-29 Horst Theuss Semiconductor component with connecting elements and method for producing the same
US20070155048A1 (en) * 2005-12-29 2007-07-05 Micron Technology, Inc. Methods for packaging microelectronic devices and microelectronic devices formed using such methods
TW200824060A (en) * 2006-11-17 2008-06-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US20080179758A1 (en) * 2007-01-25 2008-07-31 Raytheon Company Stacked integrated circuit assembly
US20100072606A1 (en) * 2008-09-25 2010-03-25 Wen-Kun Yang Stacking Package Structure with Chip Embedded Inside and Die Having Through Silicon Via and Method of the same

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US20140183719A1 (en) 2014-07-03
US8298863B2 (en) 2012-10-30
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JP2013526066A (ja) 2013-06-20
US20110266693A1 (en) 2011-11-03
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US8759154B2 (en) 2014-06-24

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