WO2011139875A2 - Tce compensation for ic package substrates for reduced die warpage assembly - Google Patents

Tce compensation for ic package substrates for reduced die warpage assembly Download PDF

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Publication number
WO2011139875A2
WO2011139875A2 PCT/US2011/034444 US2011034444W WO2011139875A2 WO 2011139875 A2 WO2011139875 A2 WO 2011139875A2 US 2011034444 W US2011034444 W US 2011034444W WO 2011139875 A2 WO2011139875 A2 WO 2011139875A2
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WO
WIPO (PCT)
Prior art keywords
die
substrate
package substrate
contacts
attaching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2011/034444
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English (en)
French (fr)
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WO2011139875A3 (en
Inventor
Margaret Rose Simmons-Matthews
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Texas Instruments Inc
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Texas Instruments Japan Ltd
Texas Instruments Inc
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Filing date
Publication date
Application filed by Texas Instruments Japan Ltd, Texas Instruments Inc filed Critical Texas Instruments Japan Ltd
Priority to CN201180019483.4A priority Critical patent/CN102844861B/zh
Priority to JP2013508271A priority patent/JP2013526066A/ja
Publication of WO2011139875A2 publication Critical patent/WO2011139875A2/en
Publication of WO2011139875A3 publication Critical patent/WO2011139875A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H10P72/7418—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. a chip mounting substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/314—Bonding techniques, e.g. hybrid bonding characterized by direct bonding of pads or other interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • Disclosed embodiments relate to integrated circuit (“IC”) packaging, and more particularly to die assembly.
  • die bonding or "die attach” describes the operation of attaching semiconductor die either to a package substrate or to some other substrate such as tape carrier for tape automated bonding.
  • the die is first picked from a separated wafer or waffle tray, aligned to a target pad on the carrier or substrate, and then permanently attached, usually by a solder or epoxy bond.
  • Die attach temperatures during assembly of IC die is generally performed at a temperature of least 150 °C, and can be performed at temperatures of 375 °C or more for eutectic die attach.
  • Assembly of very thin die ( ⁇ 100 ⁇ thick, e.g., 20 to 80 ⁇ ) to some package substrates, such as organic substrates, is known to be difficult due to the warpage of the die caused by the large coefficient of thermal expansion ("CTE") mismatch between the die and the package substrate.
  • CTE coefficient of thermal expansion
  • the CTE of the die may be about 3 ppm/°C
  • the CTE of the organic substrate may be about 20 ppm/°C or higher.
  • This problem can be further aggravated by thin package substrates (e.g., about 100-200 ⁇ thick) that may lack of rigidity over temperature.
  • TSVs through-substrate vias
  • studs e.g., gold studs
  • Warpage is also especially problematic for die stacks when one of the die has contacts on both sides, for example, involving flip chip package substrate connections on one side of the die and small area TSV connections on the other side of the die.
  • One known method for addressing the above described warpage problem is using low CTE package substrates that provide improved CTE matching relative to the die.
  • ceramic substrates and some specialized polymer substrates may provide improved CTE matching with the die.
  • low CTE package substrates are generally significantly more expensive as compared to conventional epoxy-glass resin-based (e.g., BT resin) organic substrates. What is needed is new packaging methodology for minimizing warpage and resulting effects of the CTE mismatch between the die and package substrate during assembly to allow use of conventional polymer substrates.
  • a composite carrier comprising a package substrate including at least one embedded metal layer that has its bottom surface secured to a semiconductor wafer controls the CTE mismatch between the die and the substrate.
  • the Inventor has recognized that the CTE of the composite carrier will be largely driven by the CTE of the semiconductor carrier wafer which is selected to match the CTE of the die so that despite the CTE mismatch between the die and the package substrate, the package substrate will have little impact on ACTE driven warpage during assembly.
  • the die and the wafer carrier can both comprise silicon.
  • the package substrate is generally a polymer substrate, such as an organic substrate.
  • the package substrate has a TCE that is at least is 10 ppm/°C different (typically being higher) as compared to the CTE of the die.
  • the composite carrier can be provided prior to the start of the assembly process.
  • Die attach processing is performed on the package substrate while the semiconductor wafer is attached thereto that acts as a carrier wafer.
  • the semiconductor wafer may be removed later in the assembly flow after all die attachment is complete at which time the need for flat die surfaces is no longer generally important.
  • a plurality of electrically conductive connectors e.g., a BGA
  • Sawing through the package substrate forms a plurality of die packages.
  • Disclosed embodiments include assembly of single die packages and stacked die packages that include two or more stacked die.
  • the die can include TSV die.
  • FIG. 1 shows an example method for assembling die packages in accordance with principles of the invention.
  • FIG. 2 shows an example method for assembling stacked die packages.
  • FIG. 3 shows an example method for assembling stacked die packages that include die with through- substrate vias (TSVs).
  • TSVs through- substrate vias
  • FIGS. 4A-4G are cross-sectional views illustrating steps in the example method of FIG. 3.
  • FIG. 1 shows an example embodiment of a method 100 for assembling die packages.
  • Step 101 comprises attaching contacts that are on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier.
  • the first die may be attached face down (i.e., flip chip) or face up (i.e., circuit side up)(e.g., for later wire bonding, or using through- substrate via (TSV) die).
  • TSV through- substrate via
  • the coefficient of thermal expansion (CTE) difference between the die (e.g., about 3 ppm/°C for a silicon die) and the package substrate is generally at least 10 ppm/°C.
  • step 101 comprises die attach and underfill of a plurality of singulated die to a polymer package substrate via reflow soldering of solder bumps, copper pillars, gold studs, or other suitable attachment method.
  • the plurality of first die can be provided in wafer form, instead of singulated die form, so that the wafer is attached to the package substrate.
  • the composite carrier comprises a package substrate including one or more embedded metal layers secured at a bottom surface to a semiconductor wafer.
  • the package substrate can be a polymer substrate, such as an organic substrate.
  • the package substrate can also be a ceramic substrate or other substrate.
  • the package substrate can be a thin package substrate, such as an organic substrate that has a thickness of ⁇ 200 ⁇ , such as about 100 to 200 ⁇ .
  • the CTE of the composite carrier will be largely driven by the CTE of the semiconductor carrier wafer which is selected to match the CTE of the die. Accordingly, despite the CTE mismatch between the die and the package substrate, the package substrate will have little impact on ACTE driven warpage during assembly.
  • Step 102 comprises an optional overmolding step that can comprise overmolding with an appropriate material (e.g., mold compound, adhesive).
  • Step 103 comprises removing the semiconductor carrier wafer from the package substrate. Release methods can include thermal, solvent or laser aided methods.
  • Step 104 comprises attaching a plurality of electrically conductive connectors (e.g., a ball grid array (BGA)) to the bottom surface of the package substrate.
  • Step 105 comprises sawing through the package substrate to form a plurality of singulated die packages.
  • BGA ball grid array
  • FIG. 2 shows an example method 200 for assembling stacked die packages, according to a disclosed embodiment.
  • Step 201 comprises attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier.
  • the composite carrier comprises a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer.
  • step 201 comprises die attach and underfill of a plurality of singulated first die to a polymer package substrate via reflow soldering of solder bumps, copper pillars, gold studs, or other suitable attachment method.
  • the plurality of first die can be provided in wafer form so that the wafer is attached to the package substrate.
  • step 202 a plurality of singulated second die are attached to the first die to form a plurality of die stacks on the package substrate.
  • singulated second die are attached using soldering or copper bonding, and are then underfilled.
  • Step 203 comprises an optional overmolding step that can comprise overmolding with an appropriate material (e.g., mold compound, adhesive).
  • Step 204 comprises removing the semiconductor carrier wafer from the package substrate. As described above, release methods can include thermal, solvent or laser aided methods.
  • Step 205 comprises attaching a plurality of electrically conductive connectors (e.g., BGA) to the bottom surface of the package substrate.
  • Step 206 comprises sawing through the package substrate to form a plurality of singulated stacked die packages.
  • FIG. 3 shows an example method 300 for assembling stacked die packages that include TSV die, according to a disclosed embodiment.
  • Step 301 comprises attaching a topside of a plurality of first TSV die having embedded TSVs including topside pads coupled to substrate pads on a top surface of a composite carrier.
  • step 301 comprises die attach and underfill singulated first TSV die to a polymer package substrate via reflow soldering of solder bumps, copper pillars, or other suitable attachment method.
  • the plurality of first TSV die can be provided in wafer form referred to herein as a TSV wafer.
  • the plurality of first TSV die are thinned to expose the TSVs to provide exposed bottomside TSV areas.
  • Step 303 comprises attaching a plurality of singulated second die to the bottomside TSV contacts of the first TSV die to form a plurality of die stacks on the package substrate.
  • singulated second die are attached using soldering or copper bonding, and are then underfilled.
  • Step 304 comprises an optional overmolding step that can comprise overmolding with an appropriate material (e.g., mold compound, adhesive).
  • Step 305 comprises removing the semiconductor carrier wafer from the package substrate.
  • release methods can include thermal, solvent or laser aided methods.
  • Step 306 comprises attaching a plurality of electrically conductive connectors (e.g., BGA) to the bottom surface of the package substrate.
  • Step 307 comprises sawing through the package substrate to form a plurality of singulated stacked die packages.
  • FIGs. 4A-G show successive cross sectional depictions that result from steps in the example method described relative to FIG. 3.
  • FIG. 4A is a cross sectional depiction following die attach and underfill of singulated TSV die (shown as TSV Die 1) to a multi-layer substrate 201 that is adhered to a semiconductor wafer 202 (e.g., a silicon wafer) that together constitute composite carrier 205.
  • TSV die 1 are shown flip chip attached.
  • Topside pads 206 of TSV die 1 are shown coupled to substrate pads 207 on the package substrate 201.
  • TSV Die 1 are generally at least 500 ⁇ thick.
  • FIG. 4B is a cross sectional depiction showing an electronic assembly 400 following thinning of the bottomside of the TSV Die 1 to form a thinned TSV die 410 by an appropriate method, such as backgrind, CMP, and/or substrate (e.g., a silicon) etch to expose embedded TSVs 215.
  • the thinned TSV die 1 are generally ⁇ 150 ⁇ thick, typically 20 to 80 ⁇ thick.
  • TSV contact pads 211 e.g. copper pads
  • At least a portion of the TSVs 215 are coupled to the topside pads 206.
  • FIG. 4C is a cross sectional depiction showing an electronic assembly 450 following die attach and underfill of singulated 2 nd die (shown as Die 2) to thinned TSV die 410 via a suitable method such as soldering, or copper bonding.
  • FIG. 4D is a cross sectional depiction following overmolding with an appropriate material 425 such as mold compound or an adhesive.
  • FIG. 4E is a cross sectional depiction following removal of the semiconductor wafer 202 from bottom of the polymer package substrate 201.
  • Die 2 is a memory die and TSV Die 1 is a processor die. Although not shown, additional die may be stacked on Die 2.
  • FIG. 4F is a cross sectional depiction following attaching of BGA package solder balls 218 to the package substrate 201.
  • FIG. 4G is a cross sectional depiction following sawing through the overmold 425 and package substrate 201 to singulate the stacked die packages.
  • the composite carrier has been described above as comprising a package substrate on a semiconductor wafer
  • the package substrate can comprise entirely the semiconductor (e.g., silicon, to match the semiconductor die) to achieve the same controlled warpage during the assembly process.
  • the active circuitry formed on the top semiconductor surface comprises circuit elements that generally include transistors, diodes, capacitors, and resistors, as well as signal lines and other electrical conductors that interconnect these various circuit elements.
  • Disclosed embodiments can be integrated into a variety of process flows to form a variety of devices and related products.
  • the semiconductor substrates may include various elements therein and/or layers thereon. These can include barrier layers, other dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc.
  • disclosed embodiments can be used in a variety of processes including bipolar, CMOS, BiCMOS and MEMS processes.

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
PCT/US2011/034444 2010-04-29 2011-04-29 Tce compensation for ic package substrates for reduced die warpage assembly Ceased WO2011139875A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201180019483.4A CN102844861B (zh) 2010-04-29 2011-04-29 对用于裸片翘曲减少的组装的ic封装衬底的tce补偿
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Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8227295B2 (en) * 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8786066B2 (en) 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
US8796075B2 (en) * 2011-01-11 2014-08-05 Nordson Corporation Methods for vacuum assisted underfilling
US9443783B2 (en) * 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US10153179B2 (en) 2012-08-24 2018-12-11 Taiwan Semiconductor Manufacturing Company Carrier warpage control for three dimensional integrated circuit (3DIC) stacking
KR20140110334A (ko) * 2013-03-07 2014-09-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP2014179419A (ja) * 2013-03-14 2014-09-25 Alpha- Design Kk 電子部品の接合方法
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US20150014852A1 (en) * 2013-07-12 2015-01-15 Yueli Liu Package assembly configurations for multiple dies and associated techniques
US9892970B2 (en) 2016-06-02 2018-02-13 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
US9929085B2 (en) 2016-06-02 2018-03-27 Globalfoundries Inc. Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
WO2018013086A1 (en) 2016-07-12 2018-01-18 Hewlett-Packard Development Company, L.P. Composite wafers
KR102649471B1 (ko) 2016-09-05 2024-03-21 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US9966363B1 (en) * 2017-02-03 2018-05-08 Nanya Technology Corporation Semiconductor apparatus and method for preparing the same
US10396003B2 (en) * 2017-10-18 2019-08-27 Micron Technology, Inc. Stress tuned stiffeners for micro electronics package warpage control
US10548230B2 (en) * 2018-01-04 2020-01-28 Micron Technology, Inc. Method for stress reduction in semiconductor package via carrier
CN111989771A (zh) * 2018-02-19 2020-11-24 迪德鲁科技(Bvi)有限公司 制造玻璃框架扇出型封装的系统和方法
US10692793B2 (en) * 2018-03-02 2020-06-23 Micron Technology, Inc. Electronic device with a package-level thermal regulator mechanism and associated systems, devices, and methods
CN110634806A (zh) * 2018-06-21 2019-12-31 美光科技公司 半导体装置组合件和其制造方法
US11694906B2 (en) 2019-09-03 2023-07-04 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US12412862B2 (en) * 2021-04-28 2025-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US6008070A (en) * 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
US6506681B2 (en) * 2000-12-06 2003-01-14 Micron Technology, Inc. Thin flip—chip method
US6879492B2 (en) * 2001-03-28 2005-04-12 International Business Machines Corporation Hyperbga buildup laminate
JP2003092375A (ja) * 2001-09-19 2003-03-28 Matsushita Electric Ind Co Ltd 半導体装置、その製造方法およびその検査方法
JP3831287B2 (ja) * 2002-04-08 2006-10-11 株式会社日立製作所 半導体装置の製造方法
KR100555505B1 (ko) * 2003-07-09 2006-03-03 삼성전자주식회사 실리사이드층의 증착 및 제거에 의해서 콘택홀 바닥에서확장된 오픈 선폭을 구현하는 연결 콘택 형성 방법
TWI245381B (en) * 2003-08-14 2005-12-11 Via Tech Inc Electrical package and process thereof
JP4527991B2 (ja) * 2004-01-28 2010-08-18 株式会社日立製作所 マルチチップモジュールの製造方法
TWI254425B (en) * 2004-10-26 2006-05-01 Advanced Semiconductor Eng Chip package structure, chip packaging process, chip carrier and manufacturing process thereof
US7256483B2 (en) * 2004-10-28 2007-08-14 Philips Lumileds Lighting Company, Llc Package-integrated thin film LED
JP4790297B2 (ja) * 2005-04-06 2011-10-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR100688560B1 (ko) * 2005-07-22 2007-03-02 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
JP5065586B2 (ja) * 2005-10-18 2012-11-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE102005053842B4 (de) * 2005-11-09 2008-02-07 Infineon Technologies Ag Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben
SG133445A1 (en) * 2005-12-29 2007-07-30 Micron Technology Inc Methods for packaging microelectronic devices and microelectronic devices formed using such methods
JP4390775B2 (ja) * 2006-02-08 2009-12-24 Ｏｋｉセミコンダクタ株式会社 半導体パッケージの製造方法
US7473577B2 (en) 2006-08-11 2009-01-06 International Business Machines Corporation Integrated chip carrier with compliant interconnect
US7846776B2 (en) * 2006-08-17 2010-12-07 Micron Technology, Inc. Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods
TWI316749B (en) * 2006-11-17 2009-11-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US7605477B2 (en) 2007-01-25 2009-10-20 Raytheon Company Stacked integrated circuit assembly
US20080188037A1 (en) 2007-02-05 2008-08-07 Bridge Semiconductor Corporation Method of manufacturing semiconductor chip assembly with sacrificial metal-based core carrier
US8012857B2 (en) * 2007-08-07 2011-09-06 Semiconductor Components Industries, Llc Semiconductor die singulation method
TWI375321B (en) * 2007-08-24 2012-10-21 Xintec Inc Electronic device wafer level scale packages and fabrication methods thereof
JP2009117767A (ja) * 2007-11-09 2009-05-28 Shinko Electric Ind Co Ltd 半導体装置の製造方法及びそれにより製造した半導体装置
US20100090339A1 (en) * 2008-09-12 2010-04-15 Kumar Ananda H Structures and Methods for Wafer Packages, and Probes
US8106504B2 (en) * 2008-09-25 2012-01-31 King Dragon International Inc. Stacking package structure with chip embedded inside and die having through silicon via and method of the same
US8237257B2 (en) * 2008-09-25 2012-08-07 King Dragon International Inc. Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same
US7863092B1 (en) * 2008-09-30 2011-01-04 Xilinx, Inc. Low cost bumping and bonding method for stacked die
US8952519B2 (en) * 2010-01-13 2015-02-10 Chia-Sheng Lin Chip package and fabrication method thereof
KR101698805B1 (ko) * 2010-03-23 2017-02-02 삼성전자주식회사 웨이퍼 레벨의 패키지 방법 및 그에 의해 제조되는 반도체 소자

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US20140183719A1 (en) 2014-07-03
US8298863B2 (en) 2012-10-30
JP2013526066A (ja) 2013-06-20
US20110266693A1 (en) 2011-11-03
WO2011139875A3 (en) 2012-02-23
CN102844861B (zh) 2016-01-13
US20130029457A1 (en) 2013-01-31
US8759154B2 (en) 2014-06-24

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