CN102800596A - 埋置有源元件的树脂基板及其制备方法 - Google Patents
埋置有源元件的树脂基板及其制备方法 Download PDFInfo
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- CN102800596A CN102800596A CN2011101355303A CN201110135530A CN102800596A CN 102800596 A CN102800596 A CN 102800596A CN 2011101355303 A CN2011101355303 A CN 2011101355303A CN 201110135530 A CN201110135530 A CN 201110135530A CN 102800596 A CN102800596 A CN 102800596A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (15)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011101355303A CN102800596A (zh) | 2011-05-24 | 2011-05-24 | 埋置有源元件的树脂基板及其制备方法 |
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Application Number | Priority Date | Filing Date | Title |
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CN2011101355303A CN102800596A (zh) | 2011-05-24 | 2011-05-24 | 埋置有源元件的树脂基板及其制备方法 |
Publications (1)
Publication Number | Publication Date |
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CN102800596A true CN102800596A (zh) | 2012-11-28 |
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CN2011101355303A Pending CN102800596A (zh) | 2011-05-24 | 2011-05-24 | 埋置有源元件的树脂基板及其制备方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210249345A1 (en) * | 2019-11-27 | 2021-08-12 | Applied Materials, Inc. | Package core assembly and fabrication methods |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6156980A (en) * | 1998-06-04 | 2000-12-05 | Delco Electronics Corp. | Flip chip on circuit board with enhanced heat dissipation and method therefor |
CN201134440Y (zh) * | 2007-07-24 | 2008-10-15 | 亿光电子工业股份有限公司 | 发光二极管封装改良结构 |
CN101433133A (zh) * | 2006-03-31 | 2009-05-13 | 琳得科株式会社 | 电路基板的制造方法及采用该方法制得的电路基板 |
-
2011
- 2011-05-24 CN CN2011101355303A patent/CN102800596A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6156980A (en) * | 1998-06-04 | 2000-12-05 | Delco Electronics Corp. | Flip chip on circuit board with enhanced heat dissipation and method therefor |
CN101433133A (zh) * | 2006-03-31 | 2009-05-13 | 琳得科株式会社 | 电路基板的制造方法及采用该方法制得的电路基板 |
CN201134440Y (zh) * | 2007-07-24 | 2008-10-15 | 亿光电子工业股份有限公司 | 发光二极管封装改良结构 |
Non-Patent Citations (2)
Title |
---|
LARS BOETTCHER ET AL.: "Embedding of chips for system in package realization-technology and applications", 《MICROSYSTEMS,PACKAGING,ASSEMBLY & CIRCUITS TECHNOLOGY CONFERENCE,2008》 * |
ROLF ASCHENBRENNER: "System-in-package solutions with embedded active and passive components", 《2008 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING》 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20210249345A1 (en) * | 2019-11-27 | 2021-08-12 | Applied Materials, Inc. | Package core assembly and fabrication methods |
US11881447B2 (en) * | 2019-11-27 | 2024-01-23 | Applied Materials, Inc. | Package core assembly and fabrication methods |
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Effective date of registration: 20140801 Address after: 610041, Sichuan, Chengdu hi tech Development Zone, 188 Rui Rui Road, No. 6, No. 2 building Applicant after: CHENGDU RUIHUA OPTOELECTRONIC TECHNOLOGY Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Applicant before: Institute of Microelectronics of the Chinese Academy of Sciences |
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