CN1027945C - 电子零件装配模件 - Google Patents
电子零件装配模件 Download PDFInfo
- Publication number
- CN1027945C CN1027945C CN92103441A CN92103441A CN1027945C CN 1027945 C CN1027945 C CN 1027945C CN 92103441 A CN92103441 A CN 92103441A CN 92103441 A CN92103441 A CN 92103441A CN 1027945 C CN1027945 C CN 1027945C
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- Prior art keywords
- projected electrode
- electronic
- mounting module
- protective layer
- semiconductor element
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Abstract
提供一种电子零件装配模件,它具有配线底板和通过该配线底板上的多个凸起电极群连接的电子零件或半导体元件,连接电子零件的上述多个凸起电极群中2个以上凸起电极在与电子零件的连接面和与底板的连接面之间有缩颈部,该缩颈部的横截面的纵向尺寸和横向尺寸或短径和长径不同,同时缩颈部的横向或长径沿电子零件的外周或边配置,用印刷导电性粘合剂的方法将相对配置的电子零件和配线底板同导电性凸起电极连接起来。
Description
本发明涉及电子零件装配模件,尤其是涉及通过配线底板上的导电性凸起电极来安装电子零件的电子零件装配模件及其制造方法,以及带有该电子零件装配模件的装置。
原有的电子零件中,有硅片等半导体元件、在硅底板等上形成电阻的电阻片或涂敷多层电介质的电容器片等。这些零件在电路连接上具有微细的连接部分,当与作为基底的底板之间的热膨胀差异较大时,会发生如下问题。下面针对半导体元件来说明这些问题,但不言而喻,对其它电子零件来说也是一样。
半导体元件的连接间距是探索微小化的一种途径。由于半导体元件周围的连接点个数有增多的趋势,更加促使连接间距的微小化。驱动液晶显示元件的IC(显示控制器)就是连接间距微小的半导体元件的典型实例。而且在液晶显示元件底板上进行多层接线是有困难的,结果连接端子就集中在IC片的外周部分,所以间距就更加微小了。
用于将IC片外周排列的一系列端子连接在配线底板上的方
法,一般有引线接合法、使用聚酰亚胺类带子的TAB〔Tape Auto-mated Bonding(自动焊接带)〕等。然而在这些方法中,间距仍有一定限度。前者受焊头尺寸限制,后者受铜箔的加工精度限制。
不受上述限度制约的一种结构,称作倒扣或倒装片,例如半导体元件的表面与配线底板表面相对的结构。在这种结构中,为了确保半导体元件和配线底板的电路导通及绝缘,通常需要凸起电极。当然,不一定必须要有凸起电极,如特开平2-84747号公报所提出的不使用凸起电极的方案。还有如特开昭57-28337号公报、特开平2-54946号公报及特开平2-82545号公报提出的将连接构件设置在半导体元件和配线底板之间的一种结构。
可是考虑到成本、批量生产性等实际问题,还是形成凸起电极的方法最合理。因此有关凸起电极的专利很多。另外还分为将半导体元件还是配线底板形成凸起。关于在配线底板上设置凸起的技术,已公开发表在特开昭61-245543号、特开昭62-161187号、特开昭63-40331号、特开昭63-92036号、特开昭63-220533号、特开平1-273327号、特开平1-281433号、特开平2-28340号、特开昭62-35597号、特开昭63-70888号各公报中。特别是像液晶显示元件那样只在大型配线底板周边安装半导体元件时,与所使用的底板面积相比,所形成的凸起的个数少,从成本方面考虑,这种结构不利。
与此相反,在半导体元件上设置凸起的结构更合理,因此申请专
利的也多。关于凸起的材质问题,在TAB中最一般的是使用Au(金),特开昭60-85545号公报等多数是这方面的申请。其它引人注目的是以利用变形能力大的特征,使用焊锡的实例。可以举出特开平2-37724号、特开昭63-9136号、特开昭62-287647号、特开昭63-122155号公报为例。总之是选择软材料。后面将要介绍,缓解半导体元件与配线底板的热膨胀差异引起的应力为首要目的。形成凸起的方法一般是采用电镀,但像特开昭63-304587号公报、或像特开昭61-117846号公报所述,是利用导线的方法,也引人注目。
不管上述的哪一种技术,连接间距变小时,不可避免地要使半导体元件和配线底板之间的间隙变小。结果因半导体元件和配线底板之间的热膨胀差异而产生很大的应力。于是就像《日经微型器件》1989年7月号第46页至47页中所述,在半导体元件和配线底板之间填加树脂,以缓解分散应力。
然而如《电子情报通信学会论文誌》第J73-C-Ⅱ卷,第9册,第516-524页(1990年9月)所述,这种结构的缺点是可靠性有赖于树脂的物性。因此,不使用树脂来缓解应力的结构就变得重要了。
一般来说,电极基板上形成的凸起的俯视断面形状呈圆形。与此相反,可以举出特开平2-170548号公报或特开平1-243533号公报所示的技术,能使凸起的平面纵横尺寸不同,使一个方向的尺寸比另一方向的尺寸大。前一公报中是用焊锡形成凸起,俯视断面形状呈
椭圆形,其配置方法的实施例是使短边方向朝向基片中心。但是,这种方法是为了使基片相对于基板的位置高精度的配合。后一公报中所述的凸起电极的平面形状呈葫芦形。这种凸起不仅长边方向的剪切力大,短边方向的剪切力也很大。以上两例中的凸起都是使用焊锡,没有考虑因凸起的变形而造成的底面的热形变。
在特开昭61-43438号公报中叙述了使凸起的纵断面取亚铃形状的方法,是一种用缩颈部的弯曲来吸收底面产生的热形变的方式。但是,使用这种方式,凸起的刚性不具有各向异性。
如上所述,在原有的技术中看不到关于吸收电子零件与配线底板之间的热膨胀差的带本质性的对策的技术。
本发明的目的是提供一种能吸收电子零件与配线底板之间的热膨胀差的电子零件装配模件及其制造方法,这种方法不同于上述原有技术,不是依靠在电子零件与配线底板之间填充树脂来缓解应力。
本发明者为达到上述目的而专心研究的结果,得出了适用于吸收凸起电极上的应力的结构。但是,如上所述,由于连接间距小,凸起电极的高度也小,因此为了充分发挥应力缓解的效果,就必须将凸起电极作得很细。可是凸起电极变细时,半导体元件的机械保持能力变坏。为了满足与此相反的要求,就要在凸起电极的结构或配置方面采取特殊办法。
即,使电子零件和配线底板表面面对面地连接,在采用所谓倒扣
或具有倒装片式连接结构的电子零件装配模件上,使设置在电子零件表面上或配线底板表面上的导电性的凸起电极的形状在该电子零件和该配线底板之间具有缩颈部,且使该缩颈部的横断面的纵向尺寸和横向尺寸不同,或短径与长径尺寸不同。
另外,在上述结构中,还要将缩颈部的横向或长径沿配线底板上安装的电子零件的外周或边缘配置。
下面作更具体的说明。
首先,本发明中必要的基本结构如前所述,采用本结构时,不只限于后面所述的实施例,也可能是下述的种种形式的变形。
(a)可在配线底板上形成凸起电极。
(b)在具有多个凸起部的形状时,在实施例中是基座公用,前端部公用或单用,但是,也可以基座单用。
(c)凸起部、前端部、以及基座可以使用不同的材料。当然也可以用不同的材料组成凸起部(内部与外表、中央部分与两端等)。
另外,关于上述结构的电子零件装配模件的制造方法,不只限于后面所述的实施例,也可采用原来已知的制造方法。
再者,在本发明的情况下,不需要在电子零件和配线底板之间的凸起电极周边填充树脂,但若将粘接性好的树脂填充在电子零件和配线底板的间隙中也没关系。
在所谓背面馈送或倒装片式连接结构中,在电子零件和配线底板间的连接部分产生的主要应力是由于两者的热膨胀系数不同而产
生的热应力。例如,在驱动液晶显示元件的IC中,连接端子几乎同样配置在半导体元件周围。半导体元件与配线底板之间因热膨胀系数不同而产生的热应力,以半导体元件的中心部分作为中点而呈放射状。在各连接端子上,应力朝向半导体元件的中心方向。半导体元件可以是硅,热膨胀系数小,约为3×10-6/℃,配线底板的热膨胀系数约为1×10-5/℃。因此由于温度的升高或降低,半导体元件与配线底板之间便产生相对位移。
伴随这种位移而产生的应力,这里成为问题的是热应力。为了使热应力小一些,其有效的直接解决方法是将半导体元件和配线底板之间的距离加大。但是连接间距变小时,要增大连接间隙是困难的的。例如在特开昭57-28337号公报所述的实施例中,虽然连接用引出头在300μm以上,但要用它来连接间距为50μm、直径为25μm的连接端子时,考虑到连接间距和连接间隙的关系,其形状接近细长导线。直径为25μm的连接端子,与引线接合法用的导线直径大致相同。在这么小的直径下,长度也有300μm,稍加外力,导线就会变形。因此会产生种种问题。例如连接前后搬运时,邻近的端子彼此之间接触时,稍加外力就会将连接端子压弯,不能保持连接间隙。但实用上最重要的还不是上述问题,问题是实用上很难用合适的成本实现这种结构。如果能用低成本实现这种结构,而且又能使连接端子的形变小的话,可以说是一种理想的连接状态。
在实现这种结构的困难现状中,用实用上可接受的成本实现尽
可能小的连接间隙时,必须充分实现应力缓解。因此,在将连接端子切断时,必须使载面积小。然而截面积小时虽然能使产生的热应力小,但与此同时,对其它负载的反作用力也减弱。
本发明者的着眼点是使在平行于应力方向的截面上产生的应力与连接端子的粗细的二次方成正比,而在与应力方向正交的截面上,连接端子的粗细对应力无影响。作为半导体元件与配线底板的连接端子,可考虑采用半导体元件一侧的铝导线终端部分上形成的凸起电极。凸起电极分三个部分。它们是与半导体元件一侧的铝导线终端部分连接的基座、两端宽的柱形凸起部、以及连接用的宽的前端部。设置在配线底板上的配线82的前端的底板一侧的连接起来。将凸起部切成的断面,不是正多边形或圆形,而是类似于长方形的扁平多边形或带圆角的扁平多边形、长圆形、椭圆形之类,随方向的不同,断面宽度也不同。使这种断面上所受的对连接寿命有影响的热应力的方向与断面上最窄的方向一致。即如图6所示那样配置凸起电极81,使其短边沿着放射方向、与热应力的作用方向平行。这样做可使用由于所产生的放射状相对位移而产生的热应力小,而且对作用于半导体元件50整体下的其它力来说,连接端子整体呈圆形支柱,刚性大,是一种理想的连接结构。
再来看看连接端子部分内部的应力分布情况,应力集中的地方是凸起电极的根部及前端部,为了缓解应力,加大这一部分的截面积是重要的,另外注意到使柱的两端具有一定的曲率是有效的。满足上
述所要求的事项的典型的凸起电极的详细截面示于图7。在与热应力平行的截面上,凸起部81细,在与热应力垂直的截面上,凸起部81粗。
以上详细说明的电子零件装配模件之一例示于图25A及图25B。
如图25A及25B所示,电子零件装配模件500是安装在底板上的半导体元件501和在硅基板上形成电阻及电容的基片502等电子元件的总称。基板503和电子零件502连接时,是使用凸起电极504,能使电子零件工作时连接部分产生的热应力及作用于电子零件上的外力有效地得到缓解。因此不仅对于半导体元件501,而且对于例如形成电阻的基片502等电子零件,本发明的模件结构是有用的。
下面对附图作一简单说明:
图1是表示本发明的第1实施例的透视图;
图2是表示本发明的第1实施例一部分的透视图;
图3是表示本发明的第1实施例的剖面图;
图4A及图4B是表示第1实施例的制作工序的模式剖面图;
图5是表示本发明的作用的平面图;
图6是表示本发明作用的平面图;
图7是表示本发明的作用的剖面图;
图8是表示本发明的作用的斜视图;
图9是表示第2实施例效果的平面图;
图10是第4实施例的局部放大的剖面图;
图11A及图11B是表示第4实施例作用的模式剖面图;
图12是表示第4实施例的作用的曲线图;
图13A及图13B是表示第4实施例的制作工序的模式剖面图;
图14A及图14B是表示第5实施例的作用的模式剖面图;
图15A及图15B是表示第5实施例的制作工序的示意图;
图16A及图16B是表示第5实施例的第1变形的制作工序的示意图;
图17A及图17B是表示第5实施例的第2变形例的制作工序的示意图;
图18A及图18B是表示第6实施例的制作工序的示意图;
图19是液晶显示元件外观略图;
图20是表示第10实施例的工序图;
图21是表示第11实施例的工序图;
图22是表示第12实施例的工序图;
图23A及图23B是从斜下方看到的第13实施例的斜视图;
图24是第13实施例的制作方法说明图;
图25A及图25B是表示本发明的电子零件装配模件之一例的示意图。
下面通过实施例来更具体地说明本发明。另外,本发明不限于这
些实施例。
按照图1至图24的顺序说明本发明的实施例1至实施例13。
参照图1至图4A及4B说明本发明的第1个实施例。
图1是从斜上方看到的本发明的第1实施例的斜视图。图2是将连接端子部分放大后的斜视图。图3是将图2的局部放大后的剖面图。图4A是本实施例的制作工序的流程,图4B是其模式剖面图。这里为了简单起见,图1中用虚线表示半导体元件10,并将包括铝配线的半导体元件10内部的结构全部省略。同样,在图2中除铝配线20以外,将半导体元件10及玻璃基板14省略。在图3中,将半导体元件10内部的晶体三极管、二极管、电阻、电容等功能元件及连接这些元件的配线省略,总括起来作为硅基板30。剖面平行于热应力。
本实施例的半导体元件的实际装配结构,是在玻璃基板14的表面上形成由ITO(铟和锡的复合氧化物)构成的透明配线13,再用导电性粘合剂12将上述玻璃基板14和予先形成凸起电极11的半导体元件10连接起来而成。凸起电极11与半导体元件10连接的部分形成宽阔的形状,这部分称为基座1101。为了可靠地与导电性粘合剂12连接,其前端部1103也形成宽阔的形状。中央部位是凸起部1102,图中呈薄板状,但用平行于玻璃基板14和半导体元件10的平面切割最细部分所得的截面呈长圆形。由图1可知,凸起部1102的配置方式,从整体上看呈圆筒形。若从正上方看,其形状近似图5所
示。在有热应力时,这种形状具有柔软性,而且对于外力等其它负载具有足够的刚性。图1中画出来的凸起电极11有10个,这是为了容易看而省略的结果,实际上是192个。半导体元件10是边长为4mm的正方形,在正方形的各边上每边平均排列48个凸起电极,间距为80μm。图2中用符号g表示的连接间隙约25μm,这是凸起电极11的高度(即基座1101的厚度、凸起部1102的高度和前端部1103的厚度合计起来的高度)和导电性粘合剂12的厚度的合计值。更详细地说,即在厚5μm的基座1101和铝配线20的界面上有由厚100nm的铬膜3201和厚500nm的金膜3202重叠而成的薄膜,作为电镀基底膜32。此膜的用途是防止铝配线20和凸起电极11上的铜互相扩散,以及凸起电极11电镀时用来供给电流。在凸起部1102和基座1101的连接部分,以及在凸起部1102和前端部1103的连接部分,为了避免应力集中而有一定的曲率(图3中的R)。其值为15μm。在凸起部1102的中央最细的部分,受热应力作用的方向的宽度为2μm,与其垂直的方向为30μm。基底1101及前端部1103的大小都是40μm的正方形。
参照图4A及4B说明本实施例的制造方法。图4A所示为制作工序,图4B所示为各工序中形成的剖面。图中的电镀基底膜32虽然是用一层膜来表示,这只是为了简化,前面已经讲过,该膜是由铬膜3201和金膜3202构成的两层结构。另外将铝配线20及除含有表面保护膜31的电镀基底膜32以外的其它结构省略了,总括起来作
为硅基板30。
(1)用保护层40形成基座1101的图形,在此图形中用电解镀膜法形成基座1101。厚度为5μm。为了将保护层作为阳性层使用,电镀液是酸性硫酸铜浴。
(2)将保护层40剥离,再形成厚约20μm的保护层41。在此状态下,用主要成分为(NH4)2S2O5和NH4I的腐蚀液,将基座1101的一部分腐蚀掉。
(3)利用保护层41进行电解镀膜,形成凸起部1102及前端部1103。
(4)将保护层41剥离,用电镀膜作掩膜,将电镀基底膜32腐蚀掉。
玻璃基板14的热膨胀系数为4.6×10-6,数值较小温度从常温(20℃)上升到80℃时,半导体元件10与玻璃底板14之间的最大位移约为0.3μm。尽管如此,这个数值将引起凸起部1102发生塑性形变。在凸起部1102产生的最大应力约达15kg/mm2。可是在与基座1101下部的铝配线20的界面上,以及与前端部1103的导电性粘合剂的界面上,使应力缓解到约0.5kg/mm2。这是使各界面保持安全的足够小的值。结果通过了从-30℃到85℃的温度循环试验。另外,受到破坏的地方是凸起部1102。再者,因予先将基座1101部分腐蚀掉了一部分,所以应力减弱的电镀连接部分偏离应力最集中的基座1101和凸起部分1102的接点,成为可靠性高的结构。
参照图8-图9说明本发明的第2个实施例。
图8是从斜上方看到的本发明的第2个实施例的局部斜视图。图9是从玻璃基板一侧看到的第1实施例和本实施例的平面图。图8中为了简单起见,将全部含有铝配线的半导体元件及玻璃基板省略。同样的原因,图9中将含有铝配线的半导体元件中的结构、凸起的前端部、导电性粘合剂及玻璃底板省略。
在本实施例中,在一个连接处设置若干个凸起。图8是在平行于热应力的方向排列3个凸起部11002的实施例。这是3个凸起部公用一个基座11001和一个前端部11003的一种结构。
本发明的制作工序,只是将图4中的保护层41的图形改变成有三个穴的图形,基本上与第1实施例相同,这里从略。
图9是本实施例的凸起结构。本实施例中的凸起与热应力平行的宽度与第1实施例相同,另外,3个凸起部11002的垂直于热应力方向的宽度的总和与第1实施例相同,因此其机械特性与第1实施例相同。可是凸起电极在半导体元件10上所必需的面积,在本实施例中要小一些。因此若保持凸起电极之间的间隙大小相同时,能设置较多的凸起电极,另外,如图9所示,如果凸起电极数量相同时,电极间的间隙便可取得较大。
凸起部11002的数量,不必是这里说明的3个,可根据需要适当地选择2个以上即可。
下面说明第2实施例的第1个变形例。与第2实施例不同的是
在垂直于热应力的方向上排列3个凸起部。3个凸起部的作用与平行于热应力方向的宽度相等,而垂直于热应力方向的宽度等于这3个凸起沿该方向的宽度之和的单一凸起部的作用相同。
本实施例中只是保护层图形与和2实施例的不同,因此本实施例的制作工序与第2实施例相同,故从略。
这种结构的优点是凸起部之间有间隙,将树脂填充在半导体元件和玻璃基板之间后,对于包括对凸起部的间隙进行必要的加工的工序是有利的。
这里说明的凸起部的数量是3个,当然这不是必需的,可根据需要适当地选择2个以上即可。
再来说明第2实施例的第2个变形例。在与热应力平行的方向上和垂直方向上,分别排列2个凸起部。其作用与平行于热应力方向的宽度和4个凸起部相等,而垂直于热应力方向的宽度等于这四个凸起部沿该方向的宽度之和的单一凸起的作用相同。
本实施例中只是保护层的图形与第2实施例的不同,因此本实施例的制作工序与第2实施例相同,故从略。
这种结构的优点在于与第2实施例及与第2实施例的第1变形例之间的特性。它具有能使基板部分的面积小的特征,而且对凸起部之间的间隙进行必要的加工有利。
这里说明的凸起部的个数是4个,当然这不是必需的,可根据需要适当地选择3个以上即可。
下面说明第2实施例的第3个变形例。其结构基本上酷似第2实施例。唯一不同的地方是前端部分离。
本实施例的制作工序与第2实施例相同。但也不完全相同,凸起部电镀时,要选择电镀条件,以使前端部彼此不接触,电镀时在保护层图形上下功夫就能实现。
这种结构的优点与第2实施例几乎相同。与第2实施例相比,前端部柔软,能充分地利用导电性粘合剂的柔软性,具有使应力更加缓解的优点。
这里说明的凸起部的个数是3个,当然这不是必需的,可根据需要适当地选择2个以上即可。
包括以上3个变形例的第2实施例的共同特征是有许多个凸起,能使凸起部的感应分量小,这在电气特性中是有利的。这一特征在使用高频信号的应用中特别可贵。
说明本发明的第3实施例。
在本实施例中,凸起电极最细的部分的横截面呈椭圆形。
一般来说,掩膜为长方形时,保护层是圆角长方形。在第1实施例及第2实施例中,凸起具有圆角长方形的剖面。在本实施例中,如图中右侧所示,掩膜近似于椭圆形状,使得感光性树脂的剖面形状呈椭圆。取这种形状时,当热应力的方向稍微偏离凸起的短边方向时,热应力方向沿横向改变的幅度比长方形小。总之,热应力方向偏移时,性能劣化得小。
参照图10至图13说明本发明的第4个实施例。图10是本实施例的局部放大剖面图,图11A及11B是说明由于基座厚度的不同造成的应力集中情况不同的剖面模式图,图12是表示由基座厚度造成的界面应力大小的曲线图,图13是表示本实施例的制作方法的工序图。
图10是本实施例中的连接部分的放大剖面图。是平行于热应力的纵剖面。这里为了简化,也将半导体元件内部结构省略,只取作硅基板170。在从半导体元件内部引出的铝配线171的前端部分上,设有表面保护膜172的开口部分,通过电镀基底膜173,电镀镍形成基座17401。电镀基底膜173由铬膜17301和金膜17302构成。与以上所述的结构不同,凸起电极174的凸起部17402及前端部17403是由导电性树脂构成的。这种树脂是含有微细金粉的环氧树脂。基座17401的厚度为5μm,凸起部17402的高度为20μm。凸起部的最细部分为2μm。凸起的前端部17403是用含有微细金粉的环氧树脂的导电性粘合剂175粘接在玻璃底板177上的透明电极176上的。
在本实施例中,因凸起部17402是用树脂构成的,所以增加了凸起电极174的整体柔软性,能使连接部分产生的热应力小。在本实施例中,基座17401不使用树脂的原因,是因为(1)金属的刚性大,所以能有效地扩散凸起部分的应力、(2)与树脂不同,无透水性,能防止水分进入半导体元件内部。这里要研究一下基座的厚度。图
11A及11B所示为模式图,凸起内的最大应力产生在凸起部和基座的交界附近的凸起部上。如图中箭头所示。图中夸张地表示出形变情况,可清楚地看出,一侧被拉伸,另一侧被压缩。如图11A所示,如果基座18001薄时,在凸起部18002产生的应力不能在薄的基座18001中充分扩散,几乎大小不变地作用到界面181。与此相反,如图11B所示,如果基座18201厚时,凸起部18202的应力能充分地在厚的基座18201内部扩散。另一方面,受到厚基座18201和基底184之间因热膨胀差异而产生的热应力的作用,图中在界面183附近用箭头表示。如图12所示,在基座和基底的界面上产生的热应力随厚度的增加而增大。在凸起部产生的应力随基座增厚而在界面上扩散变小,逐渐接近一常数。两者合成后的应力便是界面上产生的最大应力。因此基座有一个与界面上发生的最大应力为最小值相对应的厚度。基座如果采用树脂,比采用金属时,应力的扩散能力差,而另一方面,产生的热应力小。因此采用树脂基座时,比金属基座厚一些好。
参照图13A及13B说明本实施例的制造方法。图13A表示工序,图13B表示各工序间的剖面情况。图中虽然将电镀基底膜173作为一层膜来表示,但这是简化的结果,与其它实施例一样,它是由铬膜17301和金膜17302构成的二层结构。另外,将包含铝配线171及表面保护膜172的电镀基底膜173以外的其它结构省略,总括起来作为硅基板201。
(1)用保护层200形成基座17401的图形,在此图形中用电镀方法形成基座17401。因保护层200采用正性的,所以电镀液是酸性瓦特浴。
(2)将保护层200剥掉,再形成厚约20μm的保护层202。然后将表面上已形成了保护层202的硅基板201放入容器(图中未示出)中,再用旋转真空泵(图中未示出)抽出容器中的空气。
(3)用配合器203,向保护层202的孔上滴下导电性树脂204。
(4)导入空气,利用空气压力将导电性树脂204填入保护层202的孔中。
(5)除去保护层202。然后在200℃温度下进行20分钟热处理,使导电性树脂204硬化,形成凸起部17402及前端部17403。最后以凸起电极174作为掩膜,将电镀基底膜173腐蚀掉。
制作方法不限于上述方法,还可选用下述方法。
(a)向容器内施加大于大气压的压力,更可靠地压入。
(b)在进行树脂硬化的热处理时,同时进行保护层的分解。
(c)在大气或真空中,不用配合器,而是用网板印刷的方法,将导电性树脂涂敷在保护层的孔上。
另外,在本实施例中,基座是采用镍,当然用铜也可以,还可以采用金、焊锡合金等。镍比铜难氧化,而且因使用酸性电镀浴,所以采用镍。
参照图14A及14B至图17说明本发明的第5个实施例。图
14A及14B是用来说明由于凸起部两端的曲率大小不同而造成的应力集中不同的剖面模式图,图15A及图15B是表示本实施例的制作方法的工序图。
本实施全是欲使凸起部的基座与前端部的交界部分的曲率大的一种制作方法。首先说明凸起部的基座与前端部的交界部分的曲率大小及其效果。图14A及14B形象地示出了凸起电极的形状、最大应力的产生位置、以及最大应力的大小。图中符号的位置就是最大应力的位置,符号的大小就是最大应力的大小。图14A是凸起部21002的基座21001与前端部21003的交界部分的曲率小时的情况,图14B是曲率大时的情况。凸起电极近似于悬臂梁上的应力分布。即应力最大的部位,就是图中用符号表示的部位。如图14B所示,当凸起部21002的基座21001与前端部21003的交界部分的曲率大时,应力集中得到缓解。如第4实施例中所述,基座21001上的应力被扩散,凸起部21002内的应力当然有希望变小。本实施例是本发明者为了增大该曲率经研究后实现的。
下面参照图15A及图15B说明本实施例的制作方法。图15A表示工序,图15B表示各工序之间的剖面情况。图中将电镀基底膜222表示为一层膜,这是简化的结果,与其它实施例一样,它是由铬膜和金膜构成的两层结构。另外将包含铝配线及表面保护膜的电镀基底膜222以外的结构省略,总括起来作为硅基板221。
(1)用保护层223形成基座22001的图形,用电镀方法在该图形
中形成基座22001。厚度为5μm。因保护层采用阳性的,所以电镀液是酸性硫酸铜浴。
(2)将保护层223剥离,再形成厚约20μm的保护层224。在此状态下,用(NH4)2S2O5和NH4I为主要成分的腐蚀液,将基座22001的一部分腐蚀掉。
(3)在氮气中加热到110℃,保持30分钟。保护层224增大了流动性,拐角部分的曲率变大后,成为保护层225。
(4)利用变形后的保护层225进行电镀,形成凸起部22002及前端部22003。
(5)将变形后的保护层225剥离,用电镀膜作为掩膜,将电镀基座膜222腐蚀掉。
本发明的优点是工序简单。另一方面,其缺点是所得到的曲率随温度条件的变化而变化。
其次,参照图16A及图16B说明本实施例的第1个变形例。图16A表示工序,图16B表示各工序之间的剖面情况。图中将电镀基底膜232作为一层膜来表示,这样表示是为了简化,与其它实施例一样,它是由铬膜和金膜构成的两层结构。另外,将包含铝配线及表面保护膜的电镀基底膜232以外的其它结构省略,总括起来作为硅基板231。
(1)用保护层233形成基座23001的图形,用电镀方法在该图形中形成基座23001。厚度为5μm。因保护层采用阳性的,因此不使用
碱性电镀液。而是使用酸性的硫酸铜浴。
(2)将保护层233剥离,涂敷厚约5μm的曝光前的保护层234。
(3)利用具有黑色部分23601和透明部分23602的玻璃掩膜236进行曝光。光照射部分的保护层变成曝过光的保护层234。
(4)涂敷厚约15μm的曝光前的保护层237。用比玻璃掩膜236窄一些的玻璃掩膜(图中未示出)对透明部分进行曝光,形成曝过光的保护层238。这时因保护层厚,表面部分稍有点弯曲。
(5)对保护层进行显影和烘干。烘烤时,一边烤,保护层一边流动,使得保护层端部的曲率变大。
(6)在此状态下,用以(NH4)2S2O5和NH4I为主要成分的腐蚀液将基座23001的一部分腐蚀掉。
(7)放在丙酮和水的体积比为1∶1的混合溶液中浸渍约10秒钟。显影后的保护层239及229受到极其微小的腐蚀。这时,拐角部分的腐蚀比平坦部分重一些,形成拐角部分的曲率大的腐蚀过的保护层228及227。
(8)利用腐蚀过的保护层228及227的积层体进行电镀,形成凸起部23002及前端部23003。
(9)将腐蚀过的保护层228及227的积层体剥离,以基座23001为掩膜,将电镀基底膜232腐蚀掉。
本实施例的优点是因利用掩膜获得曲率,所以制作条件变化时,能使所获得的曲率变化小。相反的方面是需进行多次涂敷保护
层、烘干、曝光、工序复杂。
另外,在本变形例中,为了使保护层的角变圆,用丙酮进行了轻微的腐蚀。与利用热形成曲率相比,保护层因受热发生质变很小,这一点是有利的。
在本变形例中,保护层分两个阶段,还可再增加阶段数,能制作出形状光滑的凸起。
接着参照图17A及17B说明本实施例的第2个变形例。在本实施例中,利用湿法腐蚀形成曲率,实现在其它实施例中难以实现的在基座与凸起部的连接部分形成曲率。
图17A表示工序,图17B表示各工序之间的剖面情况。图中将电镀基底膜241作为一层膜来表示,这样表示是为了简化,与其它实施例一样,它是由铬膜和金膜构成的两层结构。另外,将包含铝配线及表面保护膜的电镀基底膜241以外的其它结构省略,总括起来作为硅基板240。
(1)用保护层242形成基座24501的图形,用电镀方法在该图形中形成初始凸起243。基座24501的目标厚度为5μm,而初始凸起的厚度约为15μm。因此保护层242的厚度也大约为15μm。
(2)将保护层242剥离,再形成厚约5μm的保护层244。图形由包围着已经形成的初始凸起243的部分和覆盖着初始凸起243的中央部的部分构成。
(3)在此状态下,用以(NH4)2S2O5和NH4I为主要成分的铜的
腐蚀液,将初始凸起243的一部分腐蚀掉。腐蚀作用不仅沿与掩膜垂直的方向进行,而且沿与掩膜面平行的方向进行。结果,初始凸起243的形状由基座24501和下凸起部24502合成。
(4)将保护层244除去,再形成厚约20μm厚的保护层246。在此状态下进行电解镀铜。结果形成上凸起部24503及前端部24504。
(5)将保护层246除去,以基座24501作掩膜,将电镀基底膜241腐蚀掉。与其它实施例一样,用I和NH4I的水溶液腐蚀金后,再用K3Fe(CN)6和NaOH水溶液腐蚀铬。
本变形例的特征是下凸起部24502和基座24501之间没有交界。而且在下凸起部24502和基座24501的交界处形成曲率。在其它实施例中,形成这一部分的曲率是困难的,因此这是本实施例的很大优点。另外,凸起呈细长状,采用电镀法时会产生电镀液侵入不良的问题,但是这一点对于用电镀法只形成凸起部的上半部分的本方法来说是有利的。
但是也有缺点。首先是下凸起部24502的宽度不容易稳定。下凸起部24502的宽度是一个重要尺寸,而采用本方法时,只能依赖停止腐蚀的时间,这就是问题之所在。另外,本方法是在由腐蚀决定的下凸起部24502上,再通过电镀继续形成上凸起部24503,所以存在要使两者的宽度一致的问题,另外还有必须竭力防止两者位置偏移的问题。应力集中的结果,有时会在上凸起24503和下凸起部24502的界面处断裂。
本发明的第6个实施例是用电镀和腐蚀的方法形成基座的例子。参照图18A及18B来说明。图18A表示工序,图18B表示各工序之间的剖面情况,图中将电镀基底膜251作为一层膜表示,这样表示是为了简化,与其它实施例一样,它这是由铬膜和金膜构成的两层结构。另外,将包含铝配线及表面保护膜的电镀基底膜251以外的其它结构省略,总括起来作为硅基板250。
(1)用电解电镀法形成铜的全面电镀膜252。膜厚约为5μm。
(2)涂敷感光性树脂,再盖上玻璃掩膜253。被掩膜的黑色部分25301遮住的部分不被曝光,而作为保护层253留下来,被掩膜的透明部分25302遮住的部分,形成曝光后的保护层255。
(3)因使用正性保护层,所以显影后只留下曝过光的保护层255。在此状态下,用以(NH4)2S2O5和NH4I为主要成分的铜的腐蚀液,对电镀膜252全面进行腐蚀。结果留下凸起的基座25601。已经讲过,湿法腐蚀不仅会沿垂直于掩膜的方向进行,而且还沿平行于掩膜面的方向进行。因此如图所示,在基座25601周边形成光滑的斜面,有助于缓解应力。
(4)形成厚约20μm的保护层257,往其孔中注入铜的腐蚀液,将基座25601的一部分腐蚀掉。
(5)进行铜的电解电镀。结果形成凸起部25602及前端部25603。
(6)除去保护层257,以基座25601作掩膜,将电镀基座膜251
腐蚀掉。
在本实施例中,是用腐蚀法形成基座,因此像已经说过的那样,基座的下部宽,这是一个特征。另外,在制作非常细的凸起时,采用通过掩膜上的孔进行电镀的方法,会使电镀液注入不完全,容易产生电镀不良的问题,但即使是这样,本方法也是有利的。
下面参照图19说明本发明的第7个实施例。
现以在液晶显示元件用的玻璃基板上直接安装激发液晶用的半导体元件的COG(玻璃载板)实际安装方式为例进行说明。
图19示出了液晶显示元件的外观简图。在玻璃基板260的中央部位形成液晶显示部分261,从液晶显示部分261沿纵横方向引出配线。在个人计算机用的彩色液晶显示元件的情况下,配线262的条数为纵向480条,横向为640个光点×3原色计1920条。利用这些配线262,将激发液晶用的半层体元件263、一个一个地按比例安装在驱动液晶显示部分261用的160根扫描线上。
玻璃基板260上的配线用ITO(铟-锡的复合氧化物)形成,连接用的电极基板排列配置在半导体元件外周部分。半导体元件263的电极基板的间距约为50微米。
连接间距这样微小的电极基板的方法,通常是使用各向异性导电的薄膜的方法。
这种方法是将其中含有分散的导电性粒子的各向异性导电的薄膜插入半导体元件和玻璃基板之间,通过加压、加热进行连接。连接
时通过加压,将插在半导体元件一侧的电极基板和玻璃基板一侧的电极之间的导电性粒子挤紧,将上下电极连接起来。其它部分中的导电性粒子在薄膜中处于悬浮状态,不会导通。
这种方法是连接微小间距的行之有效的方法。但是当温度周期性变化时,可靠性等方面会出现问题。
现说明本实施例中使用的凸起。
该凸起电极具有与半导体元件连接面相平行的剖面,呈椭圆形,剖面的长边和短边之比大于1,呈板状。由于将凸起电极作成这种形状,则沿与剖面的长边平行的方向施加负载时,刚性大,不易变形。可是若沿与剖面的短边平行的方向施加负载时,刚性小,易变形。另外,由于作成这种形状,在确保必要的刚性和柔软性之后,可使凸起电极的导电剖面积最大,因此用导体(例如铜)制作凸起电极时,可使导通电阻小。
由于将凸起电极前端设计成蘑菇状的头部,所以容易与玻璃基板侧电极基板连接,可提高连接后的强度。
现说明使用这种凸起电极的实际装配结构。
在本半导体元件实际装配结构中,在将排列在半导体元件连接面的内外周部分的半导体元件一侧电极焊区和与其相对设置的玻璃基板侧电极基板连接起来时,在两者之间使用凸起电极。该凸起电极一个一个地配置在全部半导体元件一侧电极焊区上,且使全部凸起电极中与半导体连接面平行的剖面的短边相平行的方向朝向接头中心。
由于这样配置,使液晶显示元件工作时由于半导体元件发热,以及半导体元件与玻璃基板之间的热膨胀的差异而产生位移,利用凸起电极的形变,就能抵消止述位移。而对半导体元件施加外力时,作为整体具有很大的刚性,所以不易变形,可靠性高。
再者,即使玻璃底板和半导体元件的热膨胀的差异变化时,也能因这种凸起电极形状的变化,使半导体元件的大小和凸起电极的高度相适应。
说明本发明的第8个实施例。
在一个电极基板上形成多个凸起电极,用它来连接半导体元件旁边的焊区和玻璃底板旁边的焊区,可获得可靠性高的连接结构。
作为在单一电极焊区上配置许多凸起电极的形态,可列举出格子状配置形态、沿着朝向基片中心方向排成一排的配置形态、以及沿着朝向基片中心方向并排配置形态等。
上述各种情况,都是这样配置各凸起电极,即使其与半导体元件侧连接面平行的剖面的长边方向指向基片中心。这许多凸起电极都能分别地形成蘑菇状的头部。另外,将许多凸起电极的头部汇合成一个单一头部,容易与玻璃基板旁边的焊区连接。而且对于将凸起电极配置成格子状、以及朝向基片中心方向排成一排的配置结构来说,由于形成单一的头部,则当因热膨胀而产生位移时,因头部与半导体元件旁边的焊区平行移动,减小了加在头部与电极焊区间的连接部位上的剥离方向的应力。
凸起电极的材料是导电性的,只要具有能最低限度地保持半导体元件的强度,什么材料都可以。从导电性、强度、易形成等方面来看,可以认为用铜形成凸起电极最好。可是,利用其本身无导电性能的材料(例如树脂)形成凸起电极,在其外面镀一层导电性物质,也可以导电。另外,用树脂形成凸起电极,再在凸起电极内部开一个从半导体元件旁边的电极焊区通向玻璃板基板旁边的电极焊区的通孔,将金属等导电性物质涂敷在通孔内部,也可以导通。
还可以将导电性粒子分散在树脂中,再用这种导电性树脂形成凸起电极。
说明本发明的第9个实施例。
现说明将在半导体元件旁边的电极焊区上形成的凸起电极与玻璃基板旁边的电极焊区连接起来的方法。
一种方法是将各向异性导电的薄膜张贴在玻璃底板侧连接面上。然后将半导体元件旁边的电极焊区上形成的凸起电极置于上述薄膜
上,挤压玻璃底板侧,使各向异性导电膜中的导电粒子变形,得以导通。在此状态下加热,使薄膜固化。
再一种方法是,首先用印刷方法将导电糊剂(如:银糊剂或金糊剂)涂敷在玻璃基板旁边的电极焊区上。然后在它上面配置好半导体元件旁边的电极焊区上形成的凸起电极,连接起来。然后加热,使导电糊剂固化。
如果凸起电极采用耐蚀性差的材料时,可在安装后的玻璃基板上涂敷粘附性好的树脂,将凸起电极周边全面包住,作为耐蚀被膜,可提高凸起电极的耐蚀性能。
参照图20说明本发明的第10个实施例。
本实施例是用腐蚀法制作由导电性树脂构成的凸起电极。
前一半工序与第6实施例相同,这里从略。以下从图18A之(3)的工序终了状态开始往下说明。
(1)涂敷混入了导电粒子的树脂330,厚约20μm。用光刻法或其它方法,在基座33101的正上面形成厚约1μm的椭圆图形332。
(2)用波长为258nm的紫外线激光(强度:约0.6J/cm2)照射。利用光的衍射现象,形成如图所示的凸起部33102及前端部33103。然后将电镀基底膜333腐蚀掉,完成凸起电极331。
在本实施例中,与第6实施例相同,是用腐蚀方法形成基座33101,所以基座33101的下部宽,是它的一个特征。另外制作非常细的凸起时,采用通过掩膜上的孔进行电镀的方法,虽然容易产生树脂注入不完全、形成不了凸起的问题,但即使这样,本方法也是有利的。
参照图21说明本发明的第11个实施例。
(1)在用聚酰亚胺制成的可挠性薄膜340上形成由厚约20μm的铜箔构成的配线图形341。为了增大粘接力,在铜箔34101和可挠性薄膜340之间插入厚约3μm的铬膜34102。
(2)与第6实施例相同,使用阳性保护层,用玻璃掩膜(图中未示出)形成腐蚀图形342。在此状态下,用铜的腐蚀液腐蚀铜箔34101。结果留下铬膜34102,形成同时用作凸起的基座34301和配线层344的构件。同时形成下凸起部34302。
(3)形成厚约20μm的保护层345,往其孔中注入铜的腐蚀液,腐蚀基座下凸起部34302的前端。这是为了确保粘接力。然后进行铜的电解电镀。结果形成上凸起部34303及前端部34304。
(4)除去保护层345。
本实施例不是在半导体元件上、而是在可挠性薄膜上形成凸起电极,不需要对半导体元件作任何的加工处理,这一点是有利的。如前所述,采用原有的技术时,铜箔的加工精度自然会受到间距的限制。
第12个实施例是将第5实施例中所述的形成曲率在的凸起电极的半导体元件351安装在树脂底板或印刷底板上的一种结构。
图22示出了外观。因印刷板350的热膨胀系数大,所以必须采用连接部位的应力缓和效果大的结构。采用第5实施例的凸起电极时,能充分地确保可靠性。最后将印刷板收入组件中,作成IC插件。
说明本发明的第13个实施例。
图23A及23B是从斜下方看到的本发明的第13实施例的斜视图。
在本实施例中,说明省略了基座402的凸起电极结构。
在前面所述的实施例中,如图23A所示,已讲过有关在基座402上设置一个或多个凸起电极403的实际装配结构。然而这种实际装配结构要进行两次以上的光学处理,因此凸起电极的制作工序复杂,制作成本高。
可是在本实施例中,如图23B所示,将基座402省略。由于采用这种结构,基底上的铝配线的终端部401和凸起电极403的结合面积减小了,因而两者的结合强度也减小了。但是,由于省略了基座402,而凸起电极的头部4032没有变,凸起部4031的长度增加了,所以能使碰撞时产生的应力小。再者,在本实施例的凸起电极结构的制作工序中,能减少光学处理的次数,所以工序可以简化,还可降低成本。
下面说明本实施例的制作方法。
图24是本发明的第13实施例的制作方法说明图。
为了制作这种凸起电极,首先在硅基板410表面上涂敷厚约5μm的保护层411。将具有比欲制作的凸起电极尺寸大的透明部4121的玻璃掩膜412配置在硅基板410上的连接电极部位,并曝光。被光照射的那部分保护层形成曝过光的保护层413。在它上面再涂敷厚15μm的曝光前的保护层414,再放上具有与欲制作的凸起电极的缩颈部大小一致的透明部4151的玻璃掩膜415,并曝光,在相当于凸起电极的缩颈部位形成曝过光的保护层416。
对保护层进行显影及烘烤。显影时,对两个阶段曝过光的保护层413、416同时显影。烘烤时保护层稍有流动,保护层的端部曲率417变大。再进行热处理,使保护层端部的曲率418加大。
利用该保护层的积层体进行电解电镀,形成凸起电极419。
将保护层的积层剥离,以凸起电极下表面作掩膜,将电镀基底膜腐蚀掉。
这样就形成了本实施例的凸起电极419。
如果采用本发明,则能缓解因电子零件与配线底板之间的热膨胀差异而引起的应力,因此能获得寿命长、可靠性高的电子零件装配模件。
Claims (11)
1、电子零件装配模件,具有一布线底板以及通过多个在其两端之间有缩颈部的凸起电极互相连接的电子零件,其特征在于:所述凸起电极的缩颈部在其与所述布线底板的连接面平行的横截面中各方向上具有不同尺寸,所述横截面最窄部分的方向大致平行于该凸起电极连接部分附近的布线底板中产生最大热应力的方向,该热应力是由于所述电子零件和所述布线底板之间热膨胀系数的不同而产生的。
2、如权利要求1的电子零件装配模件,其中,所述凸起电极的缩颈部在热应力最大的方向上的宽度比与之相垂直的方向上的小。
3、如权利要求2的电子零件装配模件,其中,所述缩颈部在与所述布线底板表面平行的方向上的横截面大致呈矩形。
4、如权利要求3的电子元件装配模件,其中,所述凸起电极与所述电子零件或所述布线底板之间的连接部分的横截面大致呈正方形。
5、如权利要求2的电子零件装配模件,其中,所述缩颈部在与所述布线底板表面平行的方向上的横截面大致呈椭圆形。
6、如权利要求5的电子零件装配模件,其中,所述凸起电极与所述零件或所述布线板之间的连接部分的横截面大致呈圆形。
7、如权利要求1的电子零件装配模件,其中,所述多个凸起电极沿所述电子零件的周边或侧边配置。
8、如权利要求1的电子零件装配模件,其中所述多个凸起电极大致配置在所述电子零件安装表面的中心的周围。
9、如权利要求1的电子零件装配模件,其中所述电子零件是半导体元件。
10、如权利要求1的电子零件装配模件,其中,所述布线底板是一玻璃基底。
11、如权利要求1的电子零件装配模件,其中,所述多个凸起电极沿所述电子零件的周边或侧边排成两列或更多列。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP10411791 | 1991-05-09 | ||
JP104117/91 | 1991-05-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1067138A CN1067138A (zh) | 1992-12-16 |
CN1027945C true CN1027945C (zh) | 1995-03-15 |
Family
ID=14372186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN92103441A Expired - Fee Related CN1027945C (zh) | 1991-05-09 | 1992-05-09 | 电子零件装配模件 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5422516A (zh) |
EP (1) | EP0514723A1 (zh) |
KR (1) | KR920022482A (zh) |
CN (1) | CN1027945C (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103748679A (zh) * | 2011-07-21 | 2014-04-23 | 高通股份有限公司 | 具有取决于在裸片上的位置的定向或几何形状或在支柱与裸片垫片之间形成有图案化结构以用于减少热应力的顺应互连支柱 |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5476211A (en) | 1993-11-16 | 1995-12-19 | Form Factor, Inc. | Method of manufacturing electrical contacts, using a sacrificial member |
US5334804A (en) * | 1992-11-17 | 1994-08-02 | Fujitsu Limited | Wire interconnect structures for connecting an integrated circuit to a substrate |
US20020053734A1 (en) | 1993-11-16 | 2002-05-09 | Formfactor, Inc. | Probe card assembly and kit, and methods of making same |
EP0657932B1 (en) * | 1993-12-13 | 2001-09-05 | Matsushita Electric Industrial Co., Ltd. | Chip package assembly and method of production |
JP3377867B2 (ja) * | 1994-08-12 | 2003-02-17 | 京セラ株式会社 | 半導体素子収納用パッケージ |
US8033838B2 (en) | 1996-02-21 | 2011-10-11 | Formfactor, Inc. | Microelectronic contact structure |
US5889326A (en) * | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
US5912510A (en) * | 1996-05-29 | 1999-06-15 | Motorola, Inc. | Bonding structure for an electronic device |
JPH10209210A (ja) | 1997-01-20 | 1998-08-07 | Sharp Corp | 半導体装置及びその製造方法並びにその検査方法 |
JP3328157B2 (ja) * | 1997-03-06 | 2002-09-24 | シャープ株式会社 | 液晶表示装置 |
FR2768859B1 (fr) * | 1997-09-23 | 2003-03-07 | Commissariat Energie Atomique | Systeme de composants a hybrider autorisant un defaut de planeite |
JPH11186688A (ja) * | 1997-10-14 | 1999-07-09 | Murata Mfg Co Ltd | ハイブリッドicおよびそれを用いた電子装置 |
DE69820477T2 (de) | 1997-10-23 | 2004-10-07 | Texas Instruments Inc | Vorrichtung zur Druckmessung in einem Raum mit einem Halbleiterchip |
US6002590A (en) * | 1998-03-24 | 1999-12-14 | Micron Technology, Inc. | Flexible trace surface circuit board and method for making flexible trace surface circuit board |
US6181011B1 (en) * | 1998-12-29 | 2001-01-30 | Kawasaki Steel Corporation | Method of controlling critical dimension of features in integrated circuits (ICS), ICS formed by the method, and systems utilizing same |
US6388335B1 (en) * | 1999-12-14 | 2002-05-14 | Atmel Corporation | Integrated circuit package formed at a wafer level |
DE10017746B4 (de) * | 2000-04-10 | 2005-10-13 | Infineon Technologies Ag | Verfahren zur Herstellung eines elektronischen Bauteils mit mikroskopisch kleinen Kontaktflächen |
US6750396B2 (en) | 2000-12-15 | 2004-06-15 | Di/Dt, Inc. | I-channel surface-mount connector |
US6503088B2 (en) * | 2000-12-15 | 2003-01-07 | Di/Dt, Inc. | I-channel surface-mount connector with extended flanges |
DE10065748A1 (de) * | 2000-12-29 | 2002-07-18 | Infineon Technologies Ag | Datenträgeranordnung mit einer Anzeigeeinrichtung |
JP2004014854A (ja) * | 2002-06-07 | 2004-01-15 | Shinko Electric Ind Co Ltd | 半導体装置 |
JP2006189484A (ja) * | 2004-12-28 | 2006-07-20 | Toshiba Matsushita Display Technology Co Ltd | 配線構造及び部品実装構造 |
JP4305667B2 (ja) * | 2005-11-07 | 2009-07-29 | セイコーエプソン株式会社 | 半導体装置 |
JP2008130803A (ja) * | 2006-11-21 | 2008-06-05 | Toshiba Matsushita Display Technology Co Ltd | 基板装置および基板 |
SG152101A1 (en) * | 2007-11-06 | 2009-05-29 | Agency Science Tech & Res | An interconnect structure and a method of fabricating the same |
KR101059970B1 (ko) * | 2008-03-26 | 2011-08-26 | 가부시키가이샤후지쿠라 | 전자부품 실장용 기판 및 그 제조방법과 전자 회로 부품 |
US8536458B1 (en) | 2009-03-30 | 2013-09-17 | Amkor Technology, Inc. | Fine pitch copper pillar package and method |
JP2011258837A (ja) * | 2010-06-10 | 2011-12-22 | Fujitsu Ltd | 実装構造、電子機器、応力緩和部材及びその製造方法 |
US8492893B1 (en) | 2011-03-16 | 2013-07-23 | Amkor Technology, Inc. | Semiconductor device capable of preventing dielectric layer from cracking |
JP5834461B2 (ja) * | 2011-04-14 | 2015-12-24 | 日本電気株式会社 | 半導体レーザモジュール及びその製造方法 |
TWI495074B (zh) * | 2012-11-30 | 2015-08-01 | Ind Tech Res Inst | 減能結構 |
JP2015177116A (ja) * | 2014-03-17 | 2015-10-05 | 株式会社東芝 | 半導体装置 |
TWI632626B (zh) * | 2016-01-06 | 2018-08-11 | 日商新川股份有限公司 | Electronic parts processing unit |
JP7002263B2 (ja) | 2017-09-25 | 2022-01-20 | 新光電気工業株式会社 | 配線基板装置 |
US11652036B2 (en) * | 2018-04-02 | 2023-05-16 | Santa Clara | Via-trace structures |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3373481A (en) * | 1965-06-22 | 1968-03-19 | Sperry Rand Corp | Method of electrically interconnecting conductors |
US4173768A (en) * | 1978-01-16 | 1979-11-06 | Rca Corporation | Contact for semiconductor devices |
US4250520A (en) * | 1979-03-14 | 1981-02-10 | Rca Corporation | Flip chip mounted diode |
US4545610A (en) * | 1983-11-25 | 1985-10-08 | International Business Machines Corporation | Method for forming elongated solder connections between a semiconductor device and a supporting substrate |
JPS6187396A (ja) * | 1984-10-05 | 1986-05-02 | 株式会社日立製作所 | 電子回路装置とその製造方法 |
JPH07112041B2 (ja) * | 1986-12-03 | 1995-11-29 | シャープ株式会社 | 半導体装置の製造方法 |
US5189507A (en) * | 1986-12-17 | 1993-02-23 | Raychem Corporation | Interconnection of electronic components |
US4845542A (en) * | 1987-03-19 | 1989-07-04 | Unisys Corporation | Interconnect for layered integrated circuit assembly |
FR2622741A1 (fr) * | 1987-11-04 | 1989-05-05 | Nec Corp | Structure pour connexion de substrats a coefficients de dilatation thermique differents |
JPH02168640A (ja) * | 1987-11-04 | 1990-06-28 | Nec Corp | 異なる基板間の接続構造 |
JPH027592A (ja) * | 1988-06-27 | 1990-01-11 | Toyo Metaraijingu Kk | 成形同時一体化プリント基板成形品 |
JPH02170548A (ja) * | 1988-12-23 | 1990-07-02 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置 |
US4930001A (en) * | 1989-03-23 | 1990-05-29 | Hughes Aircraft Company | Alloy bonded indium bumps and methods of processing same |
CA2017743C (en) * | 1989-06-30 | 1996-02-06 | William C. Hu | Ultra-tall indium or alloy bump array for ir detector hybrids and micro-electronics |
US5151773A (en) * | 1990-03-30 | 1992-09-29 | Hitachi, Ltd. | Electronic circuit apparatus comprising a structure for sealing an electronic circuit |
-
1992
- 1992-05-04 KR KR1019920007576A patent/KR920022482A/ko not_active Application Discontinuation
- 1992-05-08 US US07/880,520 patent/US5422516A/en not_active Expired - Fee Related
- 1992-05-08 EP EP92107779A patent/EP0514723A1/en not_active Withdrawn
- 1992-05-09 CN CN92103441A patent/CN1027945C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103748679A (zh) * | 2011-07-21 | 2014-04-23 | 高通股份有限公司 | 具有取决于在裸片上的位置的定向或几何形状或在支柱与裸片垫片之间形成有图案化结构以用于减少热应力的顺应互连支柱 |
CN103748679B (zh) * | 2011-07-21 | 2018-01-30 | 高通股份有限公司 | 具有取决于在裸片上的位置的定向或几何形状或在支柱与裸片垫片之间形成有图案化结构以用于减少热应力的顺应互连支柱 |
Also Published As
Publication number | Publication date |
---|---|
US5422516A (en) | 1995-06-06 |
CN1067138A (zh) | 1992-12-16 |
KR920022482A (ko) | 1992-12-19 |
EP0514723A1 (en) | 1992-11-25 |
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