CN102789987A - 低米勒电容的超级接面功率晶体管制造方法 - Google Patents

低米勒电容的超级接面功率晶体管制造方法 Download PDF

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CN102789987A
CN102789987A CN2011102381396A CN201110238139A CN102789987A CN 102789987 A CN102789987 A CN 102789987A CN 2011102381396 A CN2011102381396 A CN 2011102381396A CN 201110238139 A CN201110238139 A CN 201110238139A CN 102789987 A CN102789987 A CN 102789987A
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power transistor
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miller capacitance
transistor manufacturing
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CN102789987B (zh
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林永发
徐守一
吴孟韦
陈面国
石逸群
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Anpec Electronics Corp
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Abstract

本发明公开了一种低米勒电容的超级接面功率晶体管制造方法。首先提供一N型漏极基底，并在N型漏极基底形成一P型外延层。接着，在一晶胞区域内的P型外延层中形成至少一沟槽，并且在沟槽的表面形成一缓冲层。填入一N型掺质来源层到沟槽内，并且回蚀刻N型掺质来源层，以在沟槽的上部形成一凹陷结构。在凹陷结构的表面形成一栅极氧化层，同时，使N型掺质来源层内的N型掺质经由缓冲层扩散到P型外延层，而形成一N型基体掺杂区。接着，在凹陷结构内填入一栅极导体，并且在栅极导体周围的P型外延层内形成一N+型源极掺杂区。

Description

低米勒电容的超级接面功率晶体管制造方法
技术领域
本发明涉及功率半导体装置技术领域，特别是涉及一种具有低米勒电容的超级接面(super-junction)功率金氧半场效晶体管(power MOSFET)装置的制作方法。
背景技术
功率半导体装置常应用在电源管理的部分，例如，切换式电源供应器、计算机中心或周边电源管理IC、背光板电源供应器或马达控制等等用途，其种类包含有绝缘栅双极性晶体管(insulated gate bipolar transistor，IGBT)、金氧半场效晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)与双载子接面晶体管(bipolar junction transistor，BJT)等装置。其中，由在MOSFET可节省电能且可提供较快的装置切换速度，因此被广泛地应用各领域中。
在现今的功率装置中，有一种类型是在基底中设置成交替的P型外延层与N型外延层，如此在基底中形成多个垂直在基底表面的PN接面，并且这些PN接面互相平行，这样的功率装置又叫做超级接面功率MOSFET装置。通常，在超级接面功率MOSFET装置上会设置栅极结构，用以控制装置的电流开关。但是，上述现今技术仍有缺点需要进一步改进，例如，晶体管的信道长度不易控制，造成较低的临界电压(threshold voltage，Vt)。除此之外，过去的超级接面功率MOSFET装置具有较高的米勒电容，导致较高的切换损失(switching loss)，影响装置效能。
所以，目前业界仍需一种改良的超级接面的功率半导体装置的制作方法，以克服先前技艺的缺点与不足。
发明内容
本发明的主要目的即在提供一种功率半导体装置的制作方法，能够简化低米勒电容的超级接面功率晶体管的制造步骤。
本发明提供一种低米勒电容的超级接面功率晶体管制造方法。首先提供一N型漏极基底，并在N型漏极基底形成一P型外延层。接着，在一晶胞区域内的P型外延层中形成至少一沟槽，并在沟槽的表面形成一缓冲层。填入一N型掺质来源层在沟槽内，并回蚀刻N型掺质来源层，以在沟槽的上端形成一凹陷结构。在凹陷结构的表面形成一栅极氧化层，同时，使N型掺质来源层内的N型掺质经由缓冲层扩散至P型外延层，以形成一N型基体掺杂区。接着，在凹陷结构内填入一栅极导体，并在栅极导体周围的P型外延层内形成一N型源极掺杂区。
本发明还提供一种低米勒电容的超级接面功率晶体管制造方法，首先提供一N型漏极基底，并在N型漏极基底内形成一P型外延层。接着，在一外围耐压区域内的P型外延层中形成至少一沟槽，并在沟槽的表面形成一缓冲层。填入一N型掺质来源层在沟槽内，并回蚀刻N型掺质来源层，以在沟槽的上端形成一凹陷结构。在凹陷结构的表面形成一栅极氧化层，同时，使N型掺质来源层内的N型掺质经由缓冲层扩散到P型外延层，形成一N型基体掺杂区。接着，去除外围耐压区域内的栅极氧化层并且在凹陷结构内填入一栅极导体。
为了让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图，作详细说明。但是下述的优选实施方式与附图仅用来参考与说明，不是用来对本发明加以限制。
附图说明
图1到图8是低米勒电容的超级接面功率晶体管制造方法示意图。
图9到图11是低米勒电容的超级接面功率晶体管制造方法示意图。
其中，附图标记说明如下：
120     N型漏极基底           140     晶胞区域
160     外围耐压区域          180     P型外延层
180a    P型井                 180b    P型井
240     硬掩模层              250     缓冲层
260     沟槽                  260a    沟槽
260b    沟槽                  270N    型掺质来源层
280     凹陷结构              280a    凹陷结构
280b    凹陷结构              290N    型基体掺杂区
360     栅极氧化层            370     栅极导体
370a    栅极导体              370b    栅极导体
380     有源区域              390     光致抗蚀剂图案
400     N+型源极掺杂区        410     垂直晶体管
420     信道                  430     介电层
440     接触洞                540     P型重掺杂区
550     金属层                550a    源极图案
560     源极导体              570     阻挡层
580     保护层
具体实施方式
图1至图11是低米勒电容的超级接面功率晶体管的制造方法示意图，其中附图中相同的装置或部位会用相同的符号来表示。需注意的是，附图是以说明作为目的，并未依照原尺寸作图。
首先，在图1，提供一N型漏极基底120。N型漏极基底120上定义有一晶胞区域(cell region)140和一外围耐压区域(termination region)160，其中晶胞区域140是用来设置具有开关功能的晶体管装置，而外围耐压区域160是用来延缓晶胞区域140的高强度电场向外扩散的耐压结构。接着，根据本发明的優選具体实施例中，在晶胞区域140和一外围耐压区域160内，可以利用一外延工艺在第一导电型基材120上形成一P型外延层180。其中，在完成P型外延层180后，可选择继续进行一离子注入工艺，使P型外延层180上方的特定区域形成一P型井180a。且较佳者，P型井180a的掺杂浓度大于所述的P型外延层180的掺杂浓度。上述外延工艺可以利用一化学气相沉积工艺或其它合适方法形成。接着，在P型外延层180上形成一硬掩模层240，此硬掩模层240的组成可以包含氮化硅(Si3N4)或二氧化硅(SiO2)。
参考图2，接着，分别在晶胞区域140和外围耐压区160进行一光刻蚀刻工艺，在硬掩模层240和P型外延层180中形成至少一沟槽260，包括沟槽260a及沟槽260b，其中沟槽260a设置在晶胞区域140内，而沟槽260b设置在外围耐压区域160内，而且这些沟槽260会深入到N型漏极基底120。接着，在沟槽260的表面形成一缓冲层250，其中缓冲层250是藉由热氧化法形成，且其组成包含有氧化硅。
如图3，接着沉积一N型掺质来源层270，例如砷掺杂硅玻璃(arsenicsilicateglass，ASG)，使N型掺质来源层270填满沟渠260，然后再进行回蚀刻，以去除硬掩模层240(图未示)表面上的N型掺质来源层270，并在沟槽260的上端形成一凹陷结构280，包括位在晶胞区域140内的凹陷结构280a，和位在外围耐压区域160内的凹陷结构280b。其中，所述的凹陷结构280的深度约略等在P型井180a的接面深度。接着，进行一光刻蚀刻工艺，并可在晶胞区域140进行一斜向离子注入工艺，以在凹陷结构280a的表面形成一离子掺杂区，可藉由离子掺杂区调整位在P型井180a内的垂直通道(图未示)的临界电压(threshold voltage，Vt)。继续，去除硬掩模层240(图未示)，以暴露出P型外延层180的上表面。
如图4所示，接着，在凹陷结构280的表面形成一栅极氧化层360，同时，使N型掺质来源层270的N型掺质经由缓冲层250扩散至P型外延层180，以形成一N型基体掺杂区290。其中N型基体掺杂区290包围各沟渠260。接着，进行一蚀刻工艺，以去除凹陷结构280b内的栅极氧化层360。接着，在晶胞区域140和外围耐压区域160全面沉积一栅极导体370，使栅极导体370填入凹陷结构280中，其中，栅极导体370可包含多晶硅。
接着，如图5所示，进行一化学机械抛光工艺(chemical mechanicalpolishing，CMP)，将位在P型外延层180上方的栅极导体370去除，并且可以继续进行回蚀刻工艺，以完全去除P型外延层180上的栅极导体370，所以会形成栅极导体370a及栅极导体370b。值得注意的是，这个时候填入凹陷结构280a内的栅极导体370a会直接接触N型掺质来源层270，而且被栅极氧化层360包围，并与P型外延层180或P型井180a隔离，而凹陷结构280b内的栅极导体370b是直接接触P型外延层180或P型井180a。栅极导体370b可作是一耦合导体(coupling conductor)，使外围耐压区域160的电压维持平缓下降的趋势，并且使电压截止在特定区域。
随后，如图6，进行一光刻工艺，形成光致抗蚀剂图案390，在晶胞区域140内暴露出一有源区域380。接着，在此有源区域380进行一离子注入工艺，以在栅极导体370a周围的所述P型外延层180或P型井180a内形成一N+型源极掺杂区400，其中所述的源极导体370a直接接触N型掺质来源层270。到目前为止，已经完成垂直晶体管410结构，所述的结构包含栅极导体370a、栅极氧化层360、N+型源极掺杂区400和N型基体掺杂区290。而且所述的垂直晶体管410具有一信道(channel)420，信道420位在N+型源极掺杂区400和N型基体掺杂区290间。
接着，如图7所示，去除光致抗蚀剂图案390，暴露出P型外延层180的上表面。接着在晶胞区域140和外围耐压区域160覆盖一介电层430，介电层430覆盖住外围耐压区域160内的P型外延层180和栅极导体370b，并进行一光刻，蚀刻工艺，在晶胞区域140定义出至少一接触洞440，并且使部分的P型外延层180或P型井180a暴露出于接触洞440的底部。再进行一离子注入工艺，在接触洞440的底部形成一P型重掺杂区540。接着进行退火(anneal)处理，以活化P型重掺杂区540的掺质。其中，上述P型重掺杂区540可提升金属与半导体层接面的导电性，以利电流在接面的传输。
接着，如图8，在晶胞区域140和外围耐压区域160沉积一金属层550，此沉积工艺可以是等离子体溅镀或电子束沉积等等。同时，金属层550会填入接触洞440内，而形成一源极导体560，其中，金属层550可包含钛(Ti)、氮化钛(TiN)、铝、钨等金属或金属化合物。此外，在金属层550沉积前，可先行形成一阻挡层570，其组成可包含钛、氮化钛、钽、氮化钽等金属或金属化合物。阻挡层570乃用以避免接触洞440内的金属层550电迁移(electromigration)或扩散至P型外延层180。接着，进行一光刻蚀刻工艺，以定义出一源极图案550a，并继续在外围耐压区域160内形成一保护层580。到目前为止，已经完成低米勒电容的超级接面功率晶体管的制造方法。
图9到图11是另一优选实施例的低米勒电容的超级接面功率晶体管的制造方法示意图。第二优选实施例与第一优选实施例的差别在：在第二优选实施例中，P型井180b并非形成在P型外延层180内，而是通过另一外延工艺，使P型井180b形成在P型外延层180上方。而其它装置位置和特性，大致与图1至图3中所描述的功率装置相同，所以，下文指针对不同的装置符号作说明，其它装置的描述，请参阅图1至图3的实施例。
如图9，首先，提供一N型漏极基底120。N型漏极基底120上定义有一晶胞区域140和一外围耐压区域160，其中晶胞区域140是用来设置具有开关功能的晶体管装置，而外围耐压区域160是具有阻挡晶胞区域140的高强度电场向外扩散的耐压结构。接着，在晶胞区域140和外围耐压区域160内，利用一外延工艺在N型漏极基底120上形成一P型外延层180，其中，所述的外延工艺可以利用一化学气相沉积工艺或其它合适方法形成。接着全面沉积一硬掩模层240在P型外延层180表面。
如图10所示，接着，分别在晶胞区域140和外围耐压区160进行一光刻蚀刻工艺，在硬掩模层240和P型外延层180中形成至少一沟槽260，包括沟槽260a及沟槽260b，其中，沟槽260a设置在晶胞区域140内，而沟槽260b设置在外围耐压区域160内，且所述的这些沟槽260深入至N型漏极基底120。接着，同样在沟槽260的表面形成一缓冲层250，其中缓冲层250是以热氧化法形成，且其组成包含有氧化硅。接着沉积一N型掺质来源层270，例如，砷掺杂硅玻璃，使N型掺质来源层270填入沟渠260。再进行一回蚀刻工艺，以去除硬掩模层240上方的N型掺质来源层270(图未示)，并使N型掺质来源层270的上表面略高在P型外延层180但略低在硬掩模层240的表面。
如图11所示，去除硬掩模层240，以暴露出P型外延层180的表面，然后再进行回蚀刻或化学机械抛光工艺，用以去除凸出P型外延层180表面的N型掺质来源层270，以使N型掺质来源层270的表面大概与P型外延层180的表面位在同一高度。接着，进行一外延工艺，以在P型外延层180上方形成一P型井180b。接着，可以再利用光刻及蚀刻工艺在P型井180b形成一凹陷结构280，暴露出N型掺质来源层270，其中，凹陷结构280的底部大概与P型外延层180的表面位在同一高度。根据本优选实施例，N型掺质来源层270的表面可几乎与P型外延层180的表面切齐，因此可以提供较佳的临界电压特性。图11后的步骤会和图4到图8相同，所以不再重复。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (23)

1.一种低米勒电容的超级接面功率晶体管制造方法，其特征在于包含有：
提供一N型漏极基底；
在所述的N型漏极基底形成一P型外延层；
在一晶胞区域内的所述的P型外延层中形成至少一沟槽；
在所述沟槽的表面形成一缓冲层；
在所述沟槽内填入一N型掺质来源层；
回蚀刻所述的N型掺质来源层，以在所述沟槽的上部形成一凹陷结构；
在所述凹陷结构的表面形成一栅极氧化层，同时，使所述的N型掺质来源层内的N型掺质经由所述的缓冲层扩散至所述的P型外延层，以形成一N型基体掺杂区；
在所述的凹陷结构内填入一栅极导体；以及
在所述的栅极导体周围的所述的P型外延层内形成一N+型源极掺杂区。
2.根据权利要求1所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的栅极导体、所述的栅极氧化层、所述的N+型源极掺杂区和所述的N型基体掺杂区构成一垂直晶体管。
3.根据权利要求2所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的垂直晶体管具有一信道，其位在所述N+型源极掺杂区和所述N型基体掺杂区间。
4.根据权利要求1所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述沟槽深入至所述N型漏极基底。
5.根据权利要求1所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的缓冲层是以热氧化法形成。
6.根据权利要求1所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的缓冲层包含有氧化硅。
7.根据权利要求1所述的低米勒电容的超级接面功率晶体管制造方法，其中所述的N型掺质层包含砷掺杂硅玻璃。
8.根据权利要求1所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于还包含在所述的P型外延层内形成一P型井。
9.根据权利要求8所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述P型井的掺杂浓度大于所述P型外延层的掺杂浓度。
10.根据权利要求8所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的凹陷结构的深度约略等于所述的P型井的一接面深度。
11.根据权利要求1所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的栅极导体包含有多晶硅。
12.根据权利要求1所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的栅极导体直接接触所述的N型掺质来源层。
13.一种低米勒电容的超级接面功率晶体管制造方法，其特征在于包含有：
提供一N型漏极基底；
在所述的N型漏极基底形成一P型外延层；
在一外围耐压区域内的所述的P型外延层中形成至少一沟槽；
在所述沟槽的表面形成一缓冲层；
在所述的沟槽内填入一N型掺质来源层；
回蚀刻所述的N型掺质来源层，以在所述的沟槽的上端形成一凹陷结构；
在所述的凹陷结构的表面形成一栅极氧化层，同时，使所述的N型掺质来源层内的N型掺质经由所述的缓冲层扩散至所述的P型外延层，形成一N型基体掺杂区；
去除所述的边耐压区域内的所述栅极氧化层；以及
在所述的凹陷结构内填入一栅极导体。
14.根据权利要求13所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的栅极导体直接接触所述的P型外延层。
15.根据权利要求13所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于另包含在所述的P型外延层内形成一P型井。
16.根据权利要求15所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的栅极导体直接接触所述的P型井。
17.根据权利要求13所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的栅极导体包含有多晶硅。
18.根据权利要求13所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的栅极导体直接接触所述的N型掺质来源层。
19.根据权利要求13所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的缓冲层是以热氧化法形成者。
20.根据权利要求13所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的缓冲层包含有氧化硅。
21.根据权利要求13所述的低米勒电容的超级接面功率晶体管制造方法，其中所述的N型掺质层包含砷掺杂硅玻璃。
22.根据权利要求13所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于所述的沟槽深入至所述的N型漏极基底。
23.根据权利要求13所述的低米勒电容的超级接面功率晶体管制造方法，其特征在于还包含在所述的外围耐压区域形成一介电层，覆盖住所述的P型外延层和所述的栅极导体。
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