CN102751191A - 功率半导体装置的制作方法 - Google Patents

功率半导体装置的制作方法 Download PDF

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CN102751191A
CN102751191A CN2011102262310A CN201110226231A CN102751191A CN 102751191 A CN102751191 A CN 102751191A CN 2011102262310 A CN2011102262310 A CN 2011102262310A CN 201110226231 A CN201110226231 A CN 201110226231A CN 102751191 A CN102751191 A CN 102751191A
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power semiconductor
manufacture method
semiconductor arrangement
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林永发
徐守一
吴孟韦
陈面国
詹景晴
石逸群
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Anpec Electronics Corp
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Abstract

本发明公开了一种功率装置的制作方法。首先提供一第一导电型基底，并于第一导电型基底上形成一第一导电型外延层。接着，于所述的第一导电型外延层上形成一衬垫层，并于衬垫层上形成一硬掩模层。蚀刻硬掩模层、衬垫层和第一导电型外延层，形成至少一沟槽。接着，去除硬掩模层，并于沟槽的表面形成一缓冲层，填入一掺质来源层于沟槽内，其中掺质来源层包含有多个第二导电型掺质。然后进行一热驱入工艺，将第二导电型掺质经由缓冲层扩散到第一导电型基底中，形成第二导电型的基体掺杂区。

Description

功率半导体装置的制作方法
技术领域
本发明涉及功率半导体装置的技术领域，特别是涉及一种具有超级接面(super-junction)的功率金氧半场效晶体管(power MOSFET)装置的制作方法。
背景技术
功率半导体装置常常应用于电源管理，例如，切换式电源供应器、计算机中心或周边电源管理IC、背光板电源供应器或马达控制等等用途，其种类包含有绝缘栅双极性晶体管(insulated gate bipolar transistor，IGBT)、金氧半场效晶体管(metal-oxide-semiconductor field effect transistor，MOSFET)与双载子接面晶体管(bipolar junction transistor，BJT)等装置。其中，因为MOSFET可以节省电能且可以提供较快的装置切换速度，因此被广泛地应用各领域中。
在功率装置中，基底的设计是P型外延层和N型外延层交替设置，因此在基底中会存在有多个垂直在基底表面的PN接面，而且这些PN接面互相平行，又被叫做超级接面结构。在现有制作超级接面结构的技术中，是先在一第一导电型基材(如：N型基材)上成长一第一导电型外延层(如：N型外延层)，然后利用一第一掩模在第一导电型外延层上蚀刻出多个沟渠，接着在各沟渠内形成一第二导电型外延层(例如：P型外延层)，并使第二导电型外延层的上表面和第一导电型外延层的上表面对齐，到这个时候，各沟渠内已经填满了第二导电型外延层并且被第一导电型外延层包围。而多个第二导电型外延层和第一导电型外延层的接触面即形成超级接面结构。
但是，上述技术还有许多问题需要进一步解决。举例来说，藉由上述蚀刻外延层的方式，无法在沟渠侧壁产生平整的表面，因此第一导电型外延层和第二导电型外延层的接触面亦无法是平整表面，甚至第一导电型外延层和第二导电型外延层的接触面会发生接触不完全的情形。造成第一导电型外延层和第二导电型外延层所产生的空乏区接面不平整，进一步地降低超级界面的耐压能力。所以，仍然需一种超级接面的功率半导体装置的制作方法，用以制作具有平整PN接面的功率半导体装置，进一步地提升功率半导体装置的耐压能力。
发明内容
本发明的主要目的在提供一种功率半导体装置的制作方法，能够提升功率半导体装置的耐压能力。
本发明提供一种功率半导体装置的制作方法。首先提供一第一导电型基底，并在第一导电型基底上形成一第一导电型外延层。接着，在所述的第一导电型外延层上形成一衬垫层，并在衬垫层上形成一硬掩模层。蚀刻硬掩模层、衬垫层及第一导电型外延层，以形成到少一沟槽。接着，去除所述的硬掩模层，并在沟槽的表面形成一缓冲层(buffer layer)，填入一掺质来源层在沟槽内，其特征在在掺质来源层包含有多个第二导电型掺质。后来进行一热驱入(drive-in)工艺，将第二导电型掺质经由缓冲层扩散到第一导电型基底中，形成具有一第二导电型基体掺杂区。
本发明提供一位在掺质来源层和沟槽侧壁间的缓冲层，使热驱入后的掺质浓度在沟渠周围的梯度分布较是均匀，并使沟渠内不同深度的掺质能在第一导电型外延层内扩散到大约相同的深度，而形成平整的PN接面。因此，本发明可以提供平整的PN接面，进一步地提升功率装置的耐压能力。
附图说明
图1到图16是一种功率半导体装置的制作方法。
其中，附图标记说明如下：
12         第一导电型基底      14       晶胞区域
15         过渡区              16       外围耐压区
18         第一导电型外延层    20       衬垫层
20a        上层衬垫层          20b      下层衬垫层
20c        牺牲氧化层          22       硬掩模层
24、25、26 沟槽                27       凹陷结构
28         缓冲层              30       掺质来源层
32         氧化物盖层          34       第二导电型基体掺杂区
36         第一绝缘层          37       光致抗蚀剂层
38         多晶硅层            40       场氧化层
42、51     光致抗蚀剂图案      44       孔洞
46         重掺杂区            48       栅极氧化层
50         栅极导电层          50a      栅极图案
50b        栅极图案            51a      开口
52         第二导电型离子井    53       光致抗蚀剂层
53a        开口                54       第一导电型源极掺杂区
56         衬垫层              58       第二绝缘层
60、62     接触洞开口          64、66   第二导电型掺杂区
68         接触插塞            74a      栅极导线
74b        源极电极            76       保护层
具体实施方式
请参考图1到图16，其特征在在所制作的功率装置可以包含沟槽式的功率MOSFET，而附图中相同的装置或部位使用相同的符号来表示。需注意的是，附图只是用来说明，而且并没有按照原来的尺寸。
请参考图1，首先提供一第一导电型基底12，第一导电型基底12是N+型掺杂硅基底，可以当作是功率MOSFET的一漏极。第一导电型基底12上定义有一晶胞区(cell region)14、一围绕晶胞区14的外围耐压区(terminationregion)16、和一设置在晶胞区14和外围耐压区16间的过渡区(transitionregion)15，其特征在在晶胞区14是用在设置具有开关功能的晶体管装置，而外围耐压区16是包括用在延缓晶胞区14的高强度电场向外扩散的耐压结构。接着，可以利用外延工艺在第一导电型基底12上形成一第一导电型外延层18。根据本发明的优选实施例，第一导电型外延层18可以是一N-型外延层，例如其可以利用一化学气相沉积工艺或其它合适方法形成，而第一导电型外延层18同时可以当作是所欲形成的功率装置的飘移层(drift layer)。接着，在第一导电型外延层18上形成一衬垫层20，此衬垫层20可以分是上、下两部分，上层衬垫层20a的组成可以是氮化硅(Si3N4)，而下层衬垫层20b的组成可以是二氧化硅(SiO2)。接着，以沉积工艺在衬垫层20表面形成一硬掩模层22，例如硅氧层。
接着，参考图2，利用光刻及蚀刻工艺，在硬掩模层22、衬垫层20和第一导电型外延层18中形成沟槽24、25、26，其中，沟槽24位在晶胞区域14内，沟槽26位在过渡区15，和沟槽25位在外围耐压区16内，且依据不同工艺需求，所述的些沟槽24、25、26的底部可以仅被蚀刻到第一导电型外延层18内或被蚀刻到第一导电型基底12内。举例来说，沟槽24、25、26的形成方式可以先在一硬掩模层22上涂布一光致抗蚀剂层(图未示)，接着利用具有沟槽图案的光掩模当作是曝光掩模对光致抗蚀剂层(图未示)进行一曝光及显影工艺，再利用图案化的光致抗蚀剂层当作是蚀刻掩模而对硬掩模层22和衬垫层20进行一各向异性蚀刻工艺，将光掩模上的沟槽图案转移到硬掩模层22和衬垫层20，然后去除图案化的光致抗蚀剂层，再进行干蚀刻工艺，将沟槽图案转移到第一导电型外延层18中。当然，上述形成沟槽的方法仅是例示，沟槽24、25、26亦可以利用其它方法形成。本发明的沟槽的形状、位置、深度、宽度、长度和数量等特征不受到图2的沟槽24、25、26所限制，而可以根据实际的产品设计需求或工艺特性而调整，例如沟槽24、25、26的布局可以以具有条状(strip)、六边形(hexagonal)或螺旋状(spiral)等图案。
如图3所示，接着去除硬掩模层22，并在沟槽24、25、26的表面以热氧化的方式形成一缓冲层(buffer layer)28，其中缓冲层28的组成包含硅氧层，且其厚度優選小於30納米。除此之外，缓冲层的组成并不建议采用氧氮化合物(oxynitride)或是氮化物(nitride)，这是因是氧氮化合物会产生电子捕捉缺陷，而氮化物会有应力问题。接着，沉积一掺质来源层30在衬垫层20表面，并且使掺质来源层30填满沟渠24、25、26，其特征在于掺质来源层30具有一第二导电型，例如P型，且掺质来源层30的材料包含硼硅玻璃(borosilicate glass，BSG)，但不限于此。然后，全面形成一氧化物盖层32在掺质来源层30的表面，并且进行一热驱入工艺，使沟渠内掺质来源层30的掺质扩散到第一导电型外延层18中，在沟渠24、25、26周围的第一导电型外延层18内形成具有一第二导电型基体掺质区34，其特征在于第二导电型基体掺质区34和第一导电型外延层18的间形成垂直PN接面，也就是超级接面。
要注意的是，缓冲层28能够修补蚀刻后的沟渠24、25、26的侧壁，使得掺质来源层30和沟渠24、25、26的侧壁接触完全，使得掺质能在热驱入的过程中均匀地扩散到第一导电型外延层18内，根据此，掺质会在沟渠24、25、26周围形成均匀的浓度梯度分布，而且在缓冲层28的帮助下，掺质来源层30的掺质能向外扩散到第一导电型外延层18的大约相同深度，而形成平整的PN接面。总而言之，缓冲层28可以增进掺质在第一导电型外延层18内的浓度梯度分布的均匀性，并有效解决在先前技术中PN接面不平整的困难。
根据图4，接着将氧化物盖层32、掺质来源层30和缓冲层28去除，暴露出衬垫层20的上表面和沟渠24、25、26的侧壁。另外，根据本发明的另一优选实施例，在完成第二导电型基体掺质区34后，可以只去除氧化物盖层32和掺质来源层30，而留下缓冲层28，或只去除氧化物盖层32而留下掺质来源层30和缓冲层28。将缓冲层28去除可以避免因为掺质来源层30去除不完全而遗留下来的残留物。
然后，根据图5，在衬垫层20的表面全面形成一第一绝缘层36，并使第一绝缘层36填入沟渠24、25、26内，然后进行一化学机械抛光工艺(chemicalmechanical polishing，CMP)，直到暴露出衬垫层20的上表面，根据图6，再进行一光刻工艺，以一光致抗蚀剂层37覆盖住晶胞区14，接着对未被光致抗蚀剂层37覆盖住的过渡区15和外围耐压区16进行蚀刻工艺。这个时候，位在过渡区15的沟渠25和外围耐压区16内的沟渠26内的部分第一绝缘层36会被移除，暴露出沟渠25、26的上半部，形成一凹陷结构27。
如图7，然后移除晶胞区14内的光致抗蚀剂层37(图未示)，再全面进行一多晶硅沉积工艺，在晶胞区14、过渡区15和外围耐压区16形成一多晶硅层38，并使多晶硅层38填入位在过渡区15和外围耐压区16内的凹陷结构27。接着，进行一离子注入工艺，将掺质注入到多晶硅层38中，以增进多晶硅层38的导电度，此离子注入工艺可以使多晶硅层38具有第二导电型。除此之外，在另一优选实施例中，多晶硅层38亦可以由钛/氮化钛(Ti/TiN)/铝等金属所取代。
根据图8所示，接着，进行一化学机械抛光工艺，直到暴露出衬垫层20的上表面。再分别对晶胞区14内的第一绝缘层36和对过渡区15、外围耐压区16内的多晶硅层38进行蚀刻工艺，直到晶胞区14内的第一绝缘层36和过渡区15、外围耐压区16的多晶硅层38的上表面大概和第一导电型外延层18的上表面切齐。
根据图9，接着，移除位在第一导电型外延层18表面的上层衬垫层20a，暴露出下层衬垫层20b。在外围耐压区16内的第一导电型外延层18的上表面形成一场氧化层40，并且在第一导电型外延层18的表面形成一牺牲氧化层20c，场氧化层40的组成可以包含氧硅化物。
参考图10，进行一光刻工艺，形成一光致抗蚀剂图案42，其包括一开口44，暴露出部分的牺牲氧化层20c。开口44定义出预定形成保护封环(guard ring)的位置。然后，进行一离子注入工艺，经由开口44将掺质注入第一导电型外延层18，形成一重掺杂区46。
根据图11，接着，去除光致抗蚀剂图案42，并进行一热驱入工艺，活化重掺杂区46内的掺质。在本发明的优选实施例中，重掺杂区46具有第二导电型，例如P型。随后，移除牺牲氧化层20c，暴露出第一导电型外延层18的上表面。然后，在暴露出于晶胞区14和过渡区15的第一导电型外延层18的表面形成一栅极氧化层48，再全面沉积一栅极导电层50，根据本发明的优选实施例，栅极导电层50可以包含掺杂多晶硅(doped poly-silicon)。并进行一光刻工艺，形成一光致蚀刻停止图案51，其包含多个开口50a，暴露出部分的栅极导电层50。所述的光致抗蚀剂图案51的用途是转移其图形到栅极导电层50
根据图12所示，接着进行一蚀刻工艺，经由开口51a蚀刻掉部分的栅极导电层50，形成栅极图案50a、50b，其中栅极图案50b位在外围耐压区16内的场氧化层40上方。然后，去除光致蚀刻停止图案51。接下来，进行一自对准离子注入工艺，在沟槽24、25旁的第一导电型外延层18中形成一第二导电型离子井52，例如P型井。接着，可以继续进行一热驱入工艺。
根据图13所示，接着进行一光刻工艺，形成一光致抗蚀剂图案53，其包括一开口53a，暴露出晶胞区14。再进行一离子注入工艺，在晶胞区14内的第二导电型离子井52内形成一第一导电型源极掺杂区54。在此离子注入工艺中，过渡区15和外围耐压区16受到光致抗蚀剂图案53保护，因此不会产生掺杂区。然后，去除光致抗蚀剂图案53。接着，可以继续进行一热驱入工艺。
根据图14所示，在晶胞区14、过渡区15和外围耐压区16的上表面全面沉积一衬垫层56和一第二绝缘层58。根据本发明的优选实施例，此第二绝缘层58的组成可以包含硼磷硅玻璃(BPSG)。然后，可以继续进行一回流(reflow)工艺和/或回蚀刻工艺，使得第二绝缘层58表面平坦化。
参考图15，蚀刻晶胞区14、过渡区15和外围耐压区16内的部分第二绝缘层58和衬垫层56，在晶胞区14内的各沟渠24上方形成一接触洞开口60，暴露出沟渠24内的第一绝缘层36和部分的第一导电型源极掺杂区54。同时，在过渡区15的第二导电型离子井52上，和在外围耐压区16的栅极图案50b上方，分别形成一接触洞开口62。接下来，进行一离子注入工艺，以在第一导电型源极掺杂区54下方形成一第二导电型掺杂区64，其中第二导电型掺杂区64和第一导电型源极掺杂区54是端接接触(butted contact)。此离子注入工艺同时在暴露出于过渡区15的部分第二导电型井52内形成一第二导电型掺杂区66。经由离子注入工艺，也可以增加栅极图案50b的导电性，降低后续和金属接触产生的电阻。
根据图16所示，在各接触洞开口60、62中形成接触插塞68，其中，接触插塞68可以包含金属材料，例如钨(tungsten，W)或铜(copper，Cu)等，且填入金属材料前可以在接触洞开口60、62中先形成黏合层(glue layer)或/和阻挡层(barrier layer)。然后，全面形成一金属层(图未示)，例根据，钛、铝等，覆盖在接触插塞68和第二绝缘层58上方。再利用另一道光刻蚀刻工艺而去除过渡区15内部分的金属层，以形成至少一栅极导线74a和至少一源极电极74b。其中，栅极导线74a和源极导线74b分别直接接触并覆盖在外围耐压区16和晶胞区域14的接触插塞68上。接着，在过渡区15和外围耐压区16内形成一层保护层76，其覆盖住栅极导线74a，但是暴露出源极电极74b，以形成本发明超级接面功率MOSFET装置。
综上所述，本发明的掺质来源层和沟槽侧壁间含有一缓冲层，掺质层除可以增进沟渠侧壁的平整性，使得掺质能在热驱入的过程中均匀地扩散到第一导电型外延层内，在沟渠周围形成一均匀的浓度梯度分布，也能使掺质来源层中不同深度的掺质扩散约略相同的距离。因此，PN接面的平整性可以大幅提升，有效克服在先前技术中PN接面不平整的困难，进而加强功率装置的耐压能力。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (18)

1.一种功率半导体装置的制作方法，其特征在于包含有：
提供一第一导电型基底；
于所述的第一导电型基底上形成一第一导电型外延层；
于所述的第一导电型外延层上形成一衬垫层；
于所述的衬垫层上形成一硬掩模层；
蚀刻所述的硬掩模层、所述的衬垫层及所述的第一导电型外延层，用以形成至少一沟槽；
去除所述的硬掩模层；
于所述的沟槽的表面形成一缓冲层；
于所述的沟槽中填入掺质来源层，其中所述的掺质来源层包含多个第二导电型掺质；和
进行一热驱入工艺，将所述的第二导电型掺质经由所述的缓冲层扩散到所述的第一导电型基底中，形成具有一第二导电型的基体掺杂区。
2.根据权利要求1所述的功率半导体装置的制作方法，其特征在于所述的第一导电型基底是N+掺杂硅基底，并且当作是所述的功率半导体装置的漏极。
3.根据权利要求2所述的功率半导体装置的制作方法，其特征在于所述的第一导电型外延层是一N-掺杂外延硅层。
4.根据权利要求1所述的功率半导体装置的制作方法，其特征在于形成所述的缓冲层是通过热氧化方法形成。
5.根据权利要求1所述的功率半导体装置的制作方法，其特征在于所述的缓冲层包含硅氧层。
6.根据权利要求1所述的功率半导体装置的制作方法，其特征在于所述的缓冲层的厚度小于300埃。
7.根据权利要求1所述的功率半导体装置的制作方法，其特征在于将所述的第二导电型掺质经由所述的缓冲层扩散到所述的第一导电型基底后，还包含有以下步骤：
去除所述的掺质来源层；
去除所述的缓冲层；
于所述的沟槽中填入一第一绝缘层；
去除所述的衬垫层，暴露出所述的第一导电型外延层的一上表面；以及
于所述的第一导电型外延层的所述的上表面形成一栅极结构。
8.根据权利要求7所述的功率半导体装置的制作方法，其特征在于所述的掺质来源层包含硼掺杂硅玻璃。
9.根据权利要求7所述的功率半导体装置的制作方法，其特征在于所述的第一绝缘层包含硅氧层。
10.根据权利要求7所述的功率半导体装置的制作方法，其特征在于形成所述的栅极结构后，还包含有以下步骤：
进行一第一离子注入工艺，于所述的第一导电型外延层形成一第二导电型离子井；和
进行第二离子注入工艺，于所述的第二导电型离子井内形成一第一导电型源极掺杂区。
11.根据权利要求10所述的功率半导体装置的制作方法，其特征在于进行所述的第二离子注入工艺后，还包含有以下步骤：
于所述的第一导电型外延层的所述的上表面覆盖一第二绝缘层；和
蚀刻掉部分的所述的第二绝缘层，以于所述的沟槽上形成一接触洞开口，暴露出所述的第一绝缘层及部分的所述的第一导电型源极掺杂区。
12.根据权利要求11所述的功率半导体装置的制作方法，其特征在于形成所述的接触洞开口后，还包含有以下步骤：
进行一第三离子注入工艺，于所述的第一导电型源极掺杂区下方形成一第二导电型掺杂区；以及
于所述的接触洞开口内形成一接触插塞。
13.根据权利要求12所述的功率半导体装置的制作方法，其特征在于所述的第二导电型掺杂区的掺杂浓度大于所述的第二导电型基体掺杂区的掺杂浓度。
14.根据权利要求12所述的功率半导体装置的制作方法，其特征在于所述的第二导电型掺杂区与所述的第一导电型源极掺杂区是端接接触。
15.根据权利要求12所述的功率半导体装置的制作方法，其特征在于所述的接触洞开口内形成所述的接触插塞后，还包含有：
于所述的第二绝缘层和所述的接触插塞上形成一导电层，并使所述的导电层直接接触所述的接触插塞。
16.根据权利要求15所述的功率半导体装置的制作方法，其特征在于所述的导电层是当作源极电极。
17.根据权利要求1所述的功率半导体装置的制作方法，其特征在于所述的第一导电型是N型，而所述的第二导电型是P型。
18.根据权利要求1所述的功率半导体装置的制作方法，其特征在于将所述的第二导电型掺质经由所述的缓冲层扩散到所述的第一导电型基底后，还包含有以下步骤：
去除所述的衬垫层，暴露出所述的第一导电型外延层的一上表面；以及
于所述的第一导电型外延层的所述的上表面形成一栅极结构。
CN2011102262310A 2011-04-21 2011-08-08 功率半导体装置的制作方法 Pending CN102751191A (zh)

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TWI446459B (zh) * 2012-02-14 2014-07-21 Anpec Electronics Corp 具有超級介面之功率電晶體元件之製作方法
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6700175B1 (en) * 1999-07-02 2004-03-02 Kabushiki Kaisha Toyota Chuo Kenkyusho Vertical semiconductor device having alternating conductivity semiconductor regions
CN1610974A (zh) * 2001-12-31 2005-04-27 通用半导体公司 具有电压维持区域并从相反掺杂的多晶硅区域扩散的高电压功率mosfet
JP2005317828A (ja) * 2004-04-30 2005-11-10 Sumitomo Electric Ind Ltd 高電圧車載電力変換用半導体装置の製造方法と高電圧車載電力変換用半導体装置
US20070114599A1 (en) * 2005-11-23 2007-05-24 M-Mos Sdn. Bhd. High density trench MOSFET with reduced on-resistance
US20110006304A1 (en) * 2009-07-09 2011-01-13 Shanghai Hua Hong Nec Electronics Company, Limited Semiconductor device with alternately arranged p-type and n-type thin semiconductor layers and method for manufacturing the same
CN101982873A (zh) * 2009-10-08 2011-03-02 成都芯源系统有限公司 具有超结结构的功率器件及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6090661A (en) * 1998-03-19 2000-07-18 Lsi Logic Corporation Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6700175B1 (en) * 1999-07-02 2004-03-02 Kabushiki Kaisha Toyota Chuo Kenkyusho Vertical semiconductor device having alternating conductivity semiconductor regions
CN1610974A (zh) * 2001-12-31 2005-04-27 通用半导体公司 具有电压维持区域并从相反掺杂的多晶硅区域扩散的高电压功率mosfet
JP2005317828A (ja) * 2004-04-30 2005-11-10 Sumitomo Electric Ind Ltd 高電圧車載電力変換用半導体装置の製造方法と高電圧車載電力変換用半導体装置
US20070114599A1 (en) * 2005-11-23 2007-05-24 M-Mos Sdn. Bhd. High density trench MOSFET with reduced on-resistance
US20110006304A1 (en) * 2009-07-09 2011-01-13 Shanghai Hua Hong Nec Electronics Company, Limited Semiconductor device with alternately arranged p-type and n-type thin semiconductor layers and method for manufacturing the same
CN101982873A (zh) * 2009-10-08 2011-03-02 成都芯源系统有限公司 具有超结结构的功率器件及其制造方法

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