CN102768994B - 在功率mosfet内集成肖特基二极管 - Google Patents

在功率mosfet内集成肖特基二极管 Download PDF

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CN102768994B
CN102768994B CN201210138850.9A CN201210138850A CN102768994B CN 102768994 B CN102768994 B CN 102768994B CN 201210138850 A CN201210138850 A CN 201210138850A CN 102768994 B CN102768994 B CN 102768994B
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mesa structure
groove
cut
active
region
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CN102768994A (zh
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苏毅
伍时谦
安荷·叭剌
常虹
金钟五
陈军
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明涉及一种在功率MOSFET内集成肖特基二极管。半导体器件包括多个沟槽，多个沟槽含有在有源区中的有源栅极沟槽，以及在有源区外部的截止区中的栅极滑道/截止沟槽和屏蔽电极吸引沟槽。栅极滑道/截止沟槽包括限定位于有源区外部的台面结构的一个或多个沟槽。第一导电区形成于多个沟槽中。中间电介质区和截止保护区形成于限定台面结构的沟槽中。第二导电区形成于限定台面结构的那部分沟槽中。第二导电区通过中间电介质区，与第一导电区电绝缘。到第二导电区形成第一电接触，到屏蔽电极吸引沟槽中第一导电区形成第二电接触。一个或多个肖特基二极管形成于台面结构中。

Description

在功率MOSFET内集成肖特基二极管
技术领域
本发明主要涉及半导体器件，更确切地说，是涉及在截止区内带有集成肖特基二极管的屏蔽栅极沟槽MOS的制备方法。
背景技术
于2010年3月11日存档的美国专利申请号为12/722,384，题为《带有增强型源极吸引布局的屏蔽栅极沟槽MOS》的专利，提出了一种仅利用四个掩膜制备半导体器件的方法，特此引用其全文以作参考。该方法包括利用第一掩膜制备多个沟槽，在多个沟槽中制备第一导电区，利用第二掩膜制备中间电介质区以及截止保护区，至少在某些沟槽中制备第二导电区，利用第三掩膜形成到第二导电区的第一电接触以及到第一导电区的第二电接触，沉积金属层，利用第四掩膜形成源极金属区和栅极金属区。
这种集成结构含有功率MOSFET器件，功率MOSFET中配置了体二极管。然而，典型的P-N面结型二极管在运行时具有不良特性。这些不良特性包括：巨大的正向传导损耗、在正向配置状态下本体-外延结之间的电荷储存、当功率MOSFET从正向偏压切换至反向偏压时过量的储存少子电荷导致巨大的恢复电流以及电压过冲、以及在直流-直流转换应用中开关节点电压过冲/环绕。
另一方面，肖特基二极管具有一些优于P-N结二极管的优良特性，尤其是配置在功率MOSFET中时。肖特基二极管在正向传导时正向压降很低，会降低器件的功率耗散，从而使传导损耗更低。由于肖特基的传导是通过多子进行的，因此在器件开关时不会发生少子电荷储存效应。
正是在这一前提下，提出了本发明的各种实施例。
发明内容
本发明的目的是提供一种在功率MOSFET内集成肖特基二极管的方法，用于制备半导体器件，该方法在集成结构中引入了肖特基二极管，但是其制备工艺仍然沿用自对准接触体系，并且同样仅仅需要四个掩膜。该集成结构的制备成本更低，而且增强了器件的性能。
为了达到上述目的，本发明提供了一种用于制备半导体器件的方法，包括：
a)利用第一掩膜，在衬底上制备若干沟槽，所述若干沟槽包括位于有源区中的有源栅极沟槽，位于含有有源栅极沟槽的有源区之外的截止区中的栅极滑道/截止沟槽以及屏蔽电极拾取沟槽，栅极滑道/截止沟槽包括一个或多个沟槽，所述一个或多个沟槽限定了位于含有有源栅极沟槽的有源区之外的区域中的台面结构；
b)在限定台面结构的一个或多个沟槽中，制备第一导电区；
c)利用第二掩膜，在限定台面结构的一个或多个沟槽中，制备一个中间电介质区以及一个截止保护区；
d)在限定台面结构的一个或多个沟槽中，制备第二导电区；
e)形成到第二导电区的第一电接触，在位于截止区中的屏蔽电极拾取沟槽中，形成到第一导电区的第二电接触，并且利用第三掩膜，在含有有源栅极沟槽的有源区外部的区域中，在截止沟槽之间形成的台面结构内，制备一个或多个肖特基二极管。
上述的方法，其中，该方法还包括：
f)在器件上沉积一个金属层；并且
g)利用第四掩膜，用金属层制备源极金属区和栅极金属区。
上述的方法，其中，该方法还包括在一个或多个截止沟槽中，制备非对称的侧壁。
上述的方法，其中，制备非对称的侧壁包括切口刻蚀至少部分被第二掩膜覆盖的那部分氧化层。
上述的方法，其中，非对称的侧壁包括第一侧壁和第二侧壁，第一侧壁具有比第二侧壁更厚的氧化层，第一侧壁更靠近肖特基二极管。
上述的方法，其中，制备肖特基二极管包括在截止沟槽之间形成的台面结构的裸露表面上，沉积势垒金属。
上述的方法，其中，台面结构的裸露表面是台面结构中所形成的势阱的裸露表面。
上述的方法，其中，制备肖特基二极管包括进行深孔穴植入，以便在肖特基二极管有关的肖特基结下方，形成掺杂屏蔽区。
本发明还提供了一种半导体器件，包括：
a)衬底上的若干沟槽，其包括位于有源区中的一个或多个有源栅极沟槽，以及位于含有有源栅极沟槽的有源区外部的截止区中的一个或多个栅极滑道/截止沟槽以及屏蔽栅极拾取沟槽，栅极滑道/截止沟槽包括一个或多个沟槽，所述一个或多个沟槽限定了位于含有有源栅极沟槽的有源区之外的区域中的台面结构；
b)形成于所述若干沟槽中的第一导电区；
c)形成于限定台面结构的一个或多个沟槽的至少一部分中的一个中间电介质区以及一个截止保护区；
d)形成于限定台面结构的一个或多个沟槽的至少一部分中的第二导电区，其中，第二导电区通过中间电介质区，与第一导电区电绝缘；以及
e)到第二导电区的第一电接触，在位于截止区中的屏蔽电极拾取沟槽中，到第一导电区的第二电接触，以及在台面结构内，形成的一个或多个肖特基二极管。
上述的半导体器件，其中，该器件还包括连接到第一电接触的栅极金属区，以及连接到第二电接触的源极金属区，其中栅极金属区域与源极金属区电绝缘。
上述的半导体器件，其中，所述肖特基二极管包括位于台面结构的裸露表面上的势垒金属。
上述的半导体器件，其中，所述台面结构的裸露表面是在台面结构中所形成的势阱的裸露表面。
上述的半导体器件，其中，所述肖特基二极管包括深孔穴植入，以便在肖特基二极管有关的肖特基结下方，形成掺杂屏蔽区。
上述的半导体器件，其中，一个或多个肖特基二极管位于有源器件的第一和第二邻近组之间的封闭晶胞结构中。
上述的半导体器件，其中，一个或多个肖特基二极管形成在比有源器件的台面结构更宽的肖特基台面结构上，一个或多个有源器件就形成在有源器件台面结构上。
上述的半导体器件，其中，一个或多个肖特基二极管位于有源器件的第一和第二邻近组之间的带状晶胞结构中。
上述的半导体器件，其中，一个或多个肖特基二极管形成在比有源器件的台面结构更宽的肖特基台面结构上，一个或多个有源器件就形成在有源器件台面结构上。
本发明提出了含有配置了肖特基二极管的功率MOSFET器件的集成结构的技术方案；虽然在集成结构中引入了肖特基二极管，但是其制备工艺仍然沿用自对准接触体系，并且同样仅仅需要四个掩膜。该集成结构的制备成本更低，而且增强了器件的性能。
附图说明
图1A是依据本发明的实施例而制作的一种集成结构的俯视图。
图1B是依据本发明的实施例，将肖特基二极管配置在封闭晶胞布局中的集成结构的俯视图。
图1C是依据本发明的实施例，将肖特基二极管配置在带状晶胞布局中的集成结构的俯视图。
图1D是图1A所示类型的集成结构的制备工艺流程图。
图2是在用于制备图1A所示类型的集成结构的制备工艺中使用第一掩膜的示例。
图3是在用于制备图1A所示类型的集成结构的制备工艺中使用第二掩膜的示例。
图4是在用于制备图1A所示类型的集成结构的制备工艺中使用第三掩膜的示例。
图5是在用于制备图1A所示类型的集成结构的制备工艺中使用第四掩膜的示例。
图6SS’-34SS’所示的剖面图，表示制备图1A所示类型的集成结构沿线SS’的步骤。
具体实施方式
下文详细介绍了本发明的一个或多个实施例以及附图，并对本发明的原理进行解释说明。虽然本发明与这些实施例有关，但是本发明并不局限于任意实施例。本发明的范围仅由权利要求书限定，并且本发明含有各种可选、修正以及等效方案。下文中提出的各具体细节是为了全面解释本发明。这些细节仅用于举例说明，无需某些或全部具体细节，可以根据权利要求书来实现本发明。为了简便，文中没有详细介绍关于本发明的技术领域中已知的技术材料，以免对本发明产生不必要的混淆。
本发明提出了含有配置了肖特基二极管的功率MOSFET器件的集成结构的实施例。虽然在集成结构中引入了肖特基二极管，但是其制备工艺仍然沿用自对准接触体系，并且同样仅仅需要四个掩膜。该集成结构的制备成本更低，而且增强了器件的性能。
图1A是依据我们当前发明的实施例，制作的一种集成结构的俯视图。在本例中，集成结构100内建于半导体基底102上。结构的有源区含有有源栅极沟槽(例如104)，栅极就在栅极沟槽中形成。有源区还包括源极/本体接触开口(例如106)，在接触开口中形成接头，将源极区和本体区电连接到源极金属116。有源区还包括屏蔽接头(例如108)，该接头可能由类似多晶硅之类的传导物质构成。屏蔽电极沉积在屏蔽拾取沟槽118中，并且通过屏蔽拾取接触开口108电连接到源极金属116，源极金属116依次电连接到器件的源极和本体区。有源区被沟槽(例如110)包围着，其目的在于：作为截止沟槽，将高势能区(例如漏极)和低势能区(例如源极)分开；作为栅极滑道，在有源栅极沟槽中形成带有栅极电极的电连接。截止/栅极滑道沟槽110还包括构成栅极滑道延伸沟槽120的部分。栅极滑道延伸沟槽延伸到栅极金属区114中，用作栅极滑道沟槽，栅极拾取接触开口112就沉积在栅极拾取沟槽中，用于将栅极滑道电连接到栅极金属114。
上述可选件与美国专利申请号为12/722,384的专利中所述的集成结构的可选件完全相同。提出的方法含有附加的可选件。台面结构122形成于两个截止沟槽之间，一个或多个肖特基二极管接头124形成于台面结构122中。引入这些肖特基二极管为功率MOSFET器件带来了上述良好的性能。
在本发明的具体实施例中，需要将肖特基二极管或二极管组置于邻近的有源器件晶胞或这种晶胞组之间。有许多不同可能的布局，可以将肖特基二极管置于有源晶胞之间。作为示例，但不作为局限，图1B表示第一种可能的肖特基布局，此处称为“封闭晶胞”肖特基布局。在这类布局中，肖特基二极管区141位于有源器件晶胞的第一和第二组142A、142B之间。每组有源晶胞142A、142B都被对应的截止结构143A、143B包围。肖特基二极管结构141形成在有源晶胞的第一和第二组的截止结构之间的空间中。每个肖特基二极管结构都含有到源极金属层(图中没有表示出)的垂直连接。肖特基二极管结构141作为一系列肖特基晶胞，沿附近的截止结构143A、143B的平行线分布。两个邻近的有源晶胞组的截止结构通过横向截止结构144连接起来，横向截止结构144垂直于二极管结构141。因此，每个肖特基二极管晶胞结构都被截止结构包围着。
图1C表示另一种可能的肖特基布局，此处称为“带状晶胞”肖特基布局。在该布局中，带状肖特基二极管区145位于有源器件晶胞的第一和第二组142A、142B之间，142A、142B被对应的截止结构143A、143B包围。带状肖特基二极管结构145沿附近的截止结构143A、143B的平行线分布。两个邻近的有源晶胞组的截止结构通过横向截止结构144连接起来，横向截止结构144在肖特基二极管结构144的每个末端垂直于二极管结构141。因此，肖特基二极管晶胞结构144是连续的，并且都被截止结构包围着。
图1D所示的流程图表示集成结构(例如100)的制备工艺的实施例。工艺150含有四个掩膜。在152处，利用第一掩膜形成多个沟槽。在154处，在所述多个沟槽中形成第一组多晶硅区。在156处，利用第二掩膜形成一个或多个中间-多晶硅电介质区，以及一个或多个截止保护区。在158处，在一些沟槽中沉积多晶硅，形成第二组多晶硅区。在160处，利用第三掩膜，制成到栅极多晶硅的第一电接触开口，到源极多晶硅的第二电接触开口，并且在截止沟槽之间的台面结构中形成一个或多个肖特基二极管，截止沟槽在含有有源栅极沟槽的有源区外部的区域中。在162处，沉积一个金属层。在164处，利用第四掩膜，形成源极金属区和栅极金属区。
下文还将详细介绍制备工艺150。但是，为了简便，将仅就在集成结构内制备肖特基二极管进行讨论。图2-5表示制备工艺中所用的四个掩膜的俯视图，图6SS’-36SS’表示沿SS’的剖面图。SS’穿过肖特基二极管延伸，两个截止沟槽用于截止并包围有源区，以及有源区中两个源极/本体接头的边缘。
在下文的讨论中，以N型器件为例进行解释说明。P型器件也可利用类似的工艺进行制备。在图6SS’中，N型基底602(即N-外延层生长在N+硅晶圆上)用作器件的漏极。在某些实施例中，外延层掺杂浓度为2×1016掺杂物/cm3，厚度为1.4μm。在其他实施例中，对于重掺杂的N++基底而言，使用双外延层，包括一个掺杂浓度为2×1016掺杂物/cm3，厚度为1.4μm的外延层，以及一个掺杂浓度为1017掺杂物/cm3，厚度为2.4μm的缓冲层。
氧化硅层604通过沉积或热氧化形成在衬底602上。氮化层606沉积在氧化硅层上方。在某些实施例中，氧化硅层的厚度约为500至氮化层的厚度约为氧化层必须很厚，以便阻止肖特基区在制备过程中随后掺杂本体/源极。
然后，在氮化层上方使用光致抗蚀剂(PR)层，并利用第一掩膜制图。图2表示第一掩膜示例的俯视图，也称为沟槽掩膜。沟槽掩膜含有开口，使器件的沟槽和截止沟槽为刻蚀工艺裸露出来。利用沟槽掩膜200绘制PR层的图案。对应掩膜阴影区的PR区不会裸露出来，对应掩膜非阴影区的PR区裸露出来。在以下讨论中，为了解释说明，假设使用的是正性PR，则保留未裸露的区域，除去裸露区域。也可以使用负性PR，不过需要相应地修改掩膜。沟槽掩膜200限定有源栅极沟槽204、源极多晶硅拾取沟槽(例如208)以及栅极滑道/截止沟槽210。在某些实施例中，有源栅极沟槽、源极多晶硅拾取沟槽以及栅极滑道/截止沟槽的宽度分别约为0.45μm、1.0μm和2.0μm。可以使用低级掩膜，例如临界尺寸为0.35μm的掩膜来制备器件，从而降低所需掩膜的成本。
在图7SS’中，剩余的PR层704形成截止沟槽开口702。
随后，通过硬掩膜(HM)刻蚀，除去氮化层和氧化硅层的裸露部分。刻蚀在硅表面停止。然后除去剩余的PR。在图8SS’中，在裸露区域中形成沟槽开口802。
在HM刻蚀之后进行沟槽刻蚀。在图9SS’中，将截止沟槽开口902刻蚀得更深。在某些实施例中，沟槽的目标深度约为0.3μm至0.5μm。截止沟槽开口902之间的区域形成一个台面结构906，肖特基二极管就形成在台面结构906上。对于具有在主晶片中的晶胞间距为1μm的带状晶胞的封闭晶胞肖特基布局设计而言，肖特基台面结构906要比承载有源器件的有源器件台面结构更宽，这是由于较宽的肖特基台面结构906能承受较大的击穿电压。然而，当肖特基台面结构906的宽度过大时，将不再承受很大的击穿电压。作为示例，但不作为局限，1.2μm至1.4μm的肖特基台面结构宽度可以承受30V的器件。对于在1μm间距的带状晶胞主晶片中的封闭晶胞肖特基布局设计而言，肖特基台面结构的宽度应为0.6μm至0.8μm。当肖特基台面结构的宽度小于0.6μm或大于0.8μm时，击穿电压会下降。肖特基台面结构的宽度取决于衬底的掺杂浓度。与有源器件的台面结构宽度有关的肖特基台面结构的宽度，是衬底的外延掺杂浓度(例如生长在衬底上的外延层的掺杂浓度)
在沟槽开口902中沉积或热生长着一薄层氧化物，布满沟槽底部和沟槽壁(图中没有表示出)。在某些实施例中，氧化层的厚度约为一旦形成了氧化物，就又沉积一层氮化物，并沿水平面回刻。在某些实施例中，氮化层的厚度约为全面回刻之后，沿沟槽壁形成氮化物垫片1000，如图10SS’所示。
接下来，除去沟槽开口底部的任意裸露的衬里氧化层，通过全面的硅刻蚀进一步加深图11SS’中的截止沟槽1102。所制成的沟槽深度约为1.5μm至2.5μm，沟槽壁的倾斜角约为87-88°。氮化物垫片1000使自对准刻蚀工艺不需要额外的对准工艺，例如额外的对准掩膜，从而实现了沟槽倾斜刻蚀。由于硅刻蚀负载因素的特性，较宽的沟槽开口制成的沟槽深度大于窄沟槽开口制成的沟槽深度。截止沟槽1102的深度约在1微米至2.5微米之间。通过至的圆孔(R/H)刻蚀，使沟槽的拐角更加圆滑，以避免尖锐的拐角所带来的高电场。
在图12SS’中，沉积或热生长着一个或多个氧化层1201。在某些实施例中，可以选择生长一层左右的牺牲性氧化层，并除去，以改善硅表面。生长一层左右的氧化层，随后生长一层左右的高温沉积氧化物(HTO)或热氧化物。
沉积多晶硅1301如图13SS’所示。在某些实施例中，多晶硅的厚度约为大于最宽的沟槽宽度的一半。因此，侧壁上的多晶硅层合并起来，并且完全填满所有的沟槽。这层多晶硅有时也称为源极多晶硅、屏蔽多晶硅或多晶硅1。
然后，如图14SS’所示，利用干刻蚀，回刻源极多晶硅。在本例中，截止沟槽中剩余的多晶硅1401的厚度约为
然后沉积高密度等离子(HDP)氧化物1501，并增稠。在某些实施例中，增稠大约在高温1150℃下进行，持续大约30秒。沟槽侧壁上的氧化物在整个器件上的厚度基本一致(在图15SS’中标记为t1)。在某些实施例中，t1的范围约从至左右，部分填充较宽的沟槽(例如截止沟槽)。因此，较宽的沟槽没有被完全填满，使栅极电极在接下来的步骤中，可以沉积在未被这种较宽沟槽中的HDP1501氧化物完全填充的空间中。
然后，进行氧化物化学机械抛光(CMP)。如图16SS’所示，利用CMP工艺抛光HDP氧化物1501，直到氧化物的顶面与氮化物表面606相平，以此作为刻蚀终点。
图17SS’表示沉积一个额外的氧化层1701。在某些实施例中，额外氧化层1701的厚度约为至额外氧化层1701的厚度控制在后续进行的第二掩膜下方的湿刻蚀的切角。氧化物薄膜1701也保护器件非有源区中的氮化物606。受保护的氮化物606在稍后的处理工艺中，有助于硅衬底的无掩膜全面刻蚀。
然后，在该结构的表面上旋涂一层光致抗蚀剂，并使用第二掩膜。图3是第二掩膜300的俯视图。上一个掩膜(沟槽掩膜)的轮廓如图中虚线所示。第二掩膜300(也称为多晶硅覆盖掩膜)的轮廓如图中虚线所示。使用多晶硅覆盖掩膜300有助于形成中间-多晶硅区以及截止保护区。多晶硅覆盖掩膜300的区域302(阴影区)中的PR没有裸露，被保留下来，从而保护下方区域不受氧化物湿刻蚀的影响。掩膜300的区域，例如304(非阴影区)中的PR，裸露出来会被除去。没有被PR保护的区域将被刻蚀。在开口(例如304)中形成有源MOSFET晶胞。正如下文将要详细介绍的那样，开口的边缘靠近截止沟槽(例如306和308)，有利于这些沟槽的非对称刻蚀。
图18SS’表示PR覆层的裸露部分除去后的图案。PR1801覆盖了整个肖特基台面结构906，在1804、1804’处填充截止沟槽，在1806处延伸到有源区中。正如图19SS’所示，在PR1801下面的部分氧化物将通过刻蚀除去。掩膜覆盖以及湿或干刻蚀切口共同决定了最终结构。因此，PR覆层1801在有源区中延伸的距离部分决定了将有多少氧化物被刻蚀除去。氧化物切口的深度约在0.6μm至1.5μm之间。PR覆层1801也保护肖特基台面结构906处的氧化物不被刻蚀。
随后进行湿或干刻蚀。最终结果如图19SS’所示。区域中未被PR1801覆盖的氧化物被除去，使剩余的氧化物保持在所需的高度。PR边缘附近的氧化物也被除去。在图19SS’中，截止沟槽1902中的一部分氧化物，位于PR下方以及PR边缘附近，也被除去。刻蚀掉的氧化物的量可以通过调节PR层边缘1904的位置来控制。将边缘1904向靠近有源区的地方延伸，会使更少的氧化物被刻蚀，将边缘远离有源区延伸则会有相反的效果。在不同的实施例中，刻蚀掉的氧化物的量有所不同。在本例中，刻蚀掉足够的氧化物，使沟槽壁内衬的剩余氧化物在垂直方向上的厚度大致相同。多晶硅1401上方的氧化层1906称为中间-多晶硅电介质(IPD)，其范围约在几百只几千埃之间。
然后，除去PR，沉积或热生长一层栅极氧化物。在某些实施例中，增加的氧化层厚度约为因此，在图20SS’中，沟槽壁2002和2004布满了氧化物。结构沟槽2006具有不对称的侧壁，侧壁2004的氧化物比侧壁2002的氧化层更厚。
再一次进行多晶硅沉积和回刻。在图21SS’中，在不同的沟槽中沉积大约至左右的多晶硅。回刻沉积的多晶硅，形成栅极多晶硅2102。在本例中，多晶硅表面比氮化物垫片1000底部参考平面大约低至沉积一层钛或钴的金属层，并退火。在金属与多晶硅相接触的地方，形成多晶硅层2110。氧化物或氮化物上方的钛或钴金属不会形成硅化物，将被除去。
在图22SS’中，截止沟槽中裸露的氮化物垫片通过湿刻蚀工艺除去。然而，位于肖特基台面结构上的氮化物2200不受湿刻蚀的影响。
在图23SS’中，进行本体植入。用掺杂物离子以一定的角度轰击器件。在未被氮化物保护的有源区中，植入形成本体区(例如2304)。在某些实施例中，利用剂量能级约为1013/cm3，植入能量从60KeV至180KeV左右的硼离子，形成N-通道器件。也可以使用其他类型的离子。例如，用磷离子制备P-通道器件。
在图24SS’中，用零倾斜角进行源极植入。再次用掺杂物离子轰击器件。在某些实施例中，利用剂量能级为4×1015，植入能量从40KeV至80KeV左右的砷离子。在本体区(例如2304)中形成源极区(例如2402)。
植入器件的本体和源极不需要额外的掩膜。在肖特基台面结构处，氧化物-氮化物-氧化物势垒阻挡植入离子，防止形成源极和本体区，从而在该区域中继续植入肖特基二极管。
在图25SS’中，沉积至左右的氧化物2500，填充沟槽开口，闭锁栅极多晶硅2102和多晶硅1区1401。在某些实施例中，利用化学气相沉积(CVD)工艺，沉积厚度约为的低温氧化物(LTO)以及含有硼酸的硅玻璃(BPSG)。
在图26SS’中，通过干刻蚀工艺回刻氧化物，向下刻蚀氧化物，并在有源晶胞硅表面上的终点刻蚀停止。在这个过程中，除去在肖特基台面结构处的氮化层上方的氧化层。
进行硅全面刻蚀，刻蚀后如图27SS’所示。硅刻蚀的深度取决于图9SS’中的沟槽902的初始沟槽刻蚀深度，大约从0.6μm至0.8μm。刻蚀裸露的硅区域，但被氧化物和/或氮化物保护的区域不会被刻蚀。由于刻蚀过程不需要额外的掩膜，因此称为自对准的接触工艺。
使用另一层PR以及第三掩膜。图4表示第三掩膜400的一个示例。第三掩膜400也称为多晶硅拾取掩膜或接触掩膜。在本例中，掩膜覆盖的可选件包括栅极多晶硅拾取接头(例如402)、源极多晶硅拾取接头(例如404)以及肖特基接头(例如408)。
在图28SS’中，除去裸露的PR2800后形成接触图案。接触开口形成在肖特基接头上方，如图28SS’所示。
接下来，通过湿或干刻蚀，除去接触开口中所形成的裸露的氮化层。此外，接触开口中裸露的氧化层也被除去，以便形成肖特基二极管。图29SS’表示除去裸露的氮化层和氧化层之后的肖特基接触开口2900。
肖特基二极管可以形成在肖特基台面结构的表面上，或者还可选择形成在肖特基台面结构906中的势阱中。图30SS’表示在肖特基台面结构906的表面上进行硅刻蚀的可选步骤，以制成势阱3000，肖特基二极管就形成在势阱3000中。必须指出的是，无需该步骤，肖特基二极管就可以形成在集成结构内。
在制备肖特基二极管之前，要在肖特基接触开口处进行深孔穴植入，使掺杂屏蔽区3100形成在势阱3000下方，如图31SS’所示。可以调节掺杂离子的能量和剂量，确保掺杂屏蔽区3100形成在势阱3000的裸露表面下方。作为示例，但不作为局限，掺杂屏蔽区可以是p-型。掺杂屏蔽区3100用于在器件开关时抑制反向漏电流。
然后，除去PR。如图32SS’所示，沉积势垒金属3200(例如Ti和TiN)。在势阱3000的裸露表面上形成肖特基结。势垒金属3200构成肖特基二极管的阳极，衬底602构成肖特基二极管的阴极。所使用的Ti和TiN的厚度根据器件的不同而不同。然后，在势垒金属上方沉积W。在某些实施例中，沉积大约至的W。将沉积的W回刻到氧化物表面，形成单独的W插头3202。钨插头3202作为导体，用于接下来沉积源极金属层和栅极金属层。
利用第四掩膜制备源极金属区和栅极金属区，并且在适当的位置接触。图5表示第四掩膜500的一个示例，该掩膜也称为金属掩膜500。阴影区502和504分别对应源极金属和栅极金属。非阴影部分对应刻蚀掉的金属部分，以分离源极金属区和栅极金属区。
在图33SS’中，沉积金属层3300。在某些实施例中，利用AlCu制备大约3μm至8μm厚的金属层。然后，沉积PR 3304，并利用金属掩膜裸露出来。刻蚀掉裸露区域(例如3302)中的金属3300。
除去剩余的PR层，并使金属3304退火。在某些实施例中，金属退火是在450℃下进行30分钟。图34SS’表示肖特基二极管位于两个截止沟槽之间的最终结构的剖面图。
尽管上述内容已经对本发明的较佳实施例进行了完整说明，但是仍然可能存在各种可选、修正和等价方案。因此，本发明的范围不应局限于上述说明，相反地，本发明的范围应由所附的权利要求书及其全部等效内容决定。任何可选件(无论首选与否)，都可与其他任何可选件(无论首选与否)组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。任何没有用“意思是”明确指出限定功能的特定的权利要求，都不应认为局限于意思-加-功能。

Claims (15)

1.一种用于制备半导体器件的方法，包括：
a)利用第一掩膜，在衬底上制备若干沟槽，所述若干沟槽包括位于有源区中的有源栅极沟槽，位于含有有源栅极沟槽的有源区之外的截止区中的栅极滑道/截止沟槽以及屏蔽电极拾取沟槽，栅极滑道/截止沟槽包括一个或多个沟槽，所述一个或多个沟槽限定了位于含有有源栅极沟槽的有源区之外的区域中的台面结构；
b)在限定台面结构的一个或多个沟槽中，制备第一导电区；
c)利用第二掩膜，在限定台面结构的一个或多个沟槽中，制备一个中间电介质区以及一个截止保护区；
d)在限定台面结构的一个或多个沟槽中，制备第二导电区；
e)形成到第二导电区的第一电接触，在位于截止区中的屏蔽电极拾取沟槽中，形成到第一导电区的第二电接触，并且利用第三掩膜，在含有有源栅极沟槽的有源区外部的区域中，在截止沟槽之间形成的台面结构内，制备一个或多个肖特基二极管；
其中，该方法还包括在一个或多个截止沟槽中，制备非对称的侧壁；制备非对称的侧壁包括切口刻蚀至少部分被第二掩膜覆盖的那部分氧化层。
2.如权利要求1所述的方法，其特征在于，该方法还包括：
f)在器件上沉积一个金属层；并且
g)利用第四掩膜，用金属层制备源极金属区和栅极金属区。
3.如权利要求1所述的方法，其特征在于，非对称的侧壁包括第一侧壁和第二侧壁，第一侧壁具有比第二侧壁更厚的氧化层，第一侧壁更靠近肖特基二极管。
4.如权利要求1所述的方法，其特征在于，制备肖特基二极管包括在截止沟槽之间形成的台面结构的裸露表面上，沉积势垒金属。
5.如权利要求4所述的方法，其特征在于，台面结构的裸露表面是台面结构中所形成的势阱的裸露表面。
6.如权利要求1所述的方法，其特征在于，制备肖特基二极管包括进行深孔穴植入，以便在肖特基二极管有关的肖特基结下方，形成掺杂屏蔽区。
7.一种半导体器件，包括：
a)衬底上的若干沟槽，其包括位于有源区中的一个或多个有源栅极沟槽，以及位于含有有源栅极沟槽的有源区外部的截止区中的一个或多个栅极滑道/截止沟槽以及屏蔽栅极拾取沟槽，栅极滑道/截止沟槽包括一个或多个沟槽，所述一个或多个沟槽限定了位于含有有源栅极沟槽的有源区之外的区域中的台面结构；
b)形成于所述若干沟槽中的第一导电区；
c)形成于限定台面结构的一个或多个沟槽的至少一部分中的一个中间电介质区以及一个截止保护区；
d)形成于限定台面结构的一个或多个沟槽的至少一部分中的第二导电区，其中，第二导电区通过中间电介质区，与第一导电区电绝缘；以及
e)到第二导电区的第一电接触，在位于截止区中的屏蔽电极拾取沟槽中，到第一导电区的第二电接触，以及在台面结构内，形成的一个或多个肖特基二极管；
其中，所述限定台面结构的一个或多个截止沟槽具有非对称的侧壁厚度。
8.如权利要求7所述的半导体器件，其特征在于，该器件还包括连接到第一电接触的栅极金属区，以及连接到第二电接触的源极金属区，其中栅极金属区域与源极金属区电绝缘。
9.如权利要求7所述的半导体器件，其特征在于，所述肖特基二极管包括位于台面结构的裸露表面上的势垒金属。
10.如权利要求9所述的半导体器件，其特征在于，所述台面结构的裸露表面是在台面结构中所形成的势阱的裸露表面。
11.如权利要求7所述的半导体器件，其特征在于，所述肖特基二极管包括深孔穴植入，以便在肖特基二极管有关的肖特基结下方，形成掺杂屏蔽区。
12.如权利要求7所述的半导体器件，其特征在于，一个或多个肖特基二极管位于有源器件的第一和第二邻近组之间的封闭晶胞结构中。
13.如权利要求12所述的半导体器件，其特征在于，一个或多个肖特基二极管形成在比有源器件的台面结构更宽的肖特基台面结构上，一个或多个有源器件就形成在有源器件台面结构上。
14.如权利要求7所述的半导体器件，其特征在于，一个或多个肖特基二极管位于有源器件的第一和第二邻近组之间的带状晶胞结构中。
15.如权利要求14所述的半导体器件，其特征在于，一个或多个肖特基二极管形成在比有源器件的台面结构更宽的肖特基台面结构上，一个或多个有源器件就形成在有源器件台面结构上。
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