CN102891169A - 具有新型结构的高压(hv)器件端接及其制备方法 - Google Patents

具有新型结构的高压(hv)器件端接及其制备方法 Download PDF

Info

Publication number
CN102891169A
CN102891169A CN2012102449196A CN201210244919A CN102891169A CN 102891169 A CN102891169 A CN 102891169A CN 2012102449196 A CN2012102449196 A CN 2012102449196A CN 201210244919 A CN201210244919 A CN 201210244919A CN 102891169 A CN102891169 A CN 102891169A
Authority
CN
China
Prior art keywords
terminating
groove
doped region
burying
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012102449196A
Other languages
English (en)
Other versions
CN102891169B (zh
Inventor
李亦衡
马督儿·博德
丁永平
金钟五
安荷·叭剌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alpha and Omega Semiconductor Cayman Ltd
Original Assignee
Alpha and Omega Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Inc filed Critical Alpha and Omega Semiconductor Inc
Publication of CN102891169A publication Critical patent/CN102891169A/zh
Application granted granted Critical
Publication of CN102891169B publication Critical patent/CN102891169B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明为具有新型结构的高压(HV)器件端接及其制备方法，公开了一种设置在半导体衬底中的半导体功率器件，含有一个形成在轻掺杂区上的重掺杂区，并且具有一个有源器件元区和一个边缘终接区。边缘终接区包括多个终接沟槽，形成在重掺杂区中，终接沟槽内衬电介质层，并且用导电材料填充。边缘终接还包括多个掩埋保护环，作为掺杂区，在半导体衬底的轻掺杂区中，紧靠终接沟槽。

Description

具有新型结构的高压(HV)器件端接及其制备方法
技术领域
本发明主要关于半导体功率器件。更确切的说，本发明是关于用于高压（HV）器件的新型改良型边缘终接的结构及制备方法，以便增强可靠性，减少终接区所占的面积，同时保持高击穿电压。
背景技术
终接区中传统的浮动保护环不足以承受高压（HV）器件的高击穿电压，如图1所示，高压（HV）器件具有重掺杂的N区110（例如掺杂浓度达1016掺杂物/cm3），在衬底105的顶面以下2至5微米的深度。重掺杂区110中的N-电荷过高，浮动保护环为植入在重掺杂N区中的P型掺杂区，为了承受终接区中较高的击穿电压，浮动保护环需要电荷补偿。传统的边缘终接带有氧化物内衬沟槽中的电压降，并不能有效解决由于这种边缘终接仅可以承受高达100伏的击穿电压而造成的问题。100伏以下的击穿电压是由于沟槽下方的显著的场拥挤效应而引起的。当需要较高的电压运行时，边缘终接处的低击穿电压会限制高压（HV）器件的应用。
因此，在功率半导体器件设计和制备领域中，有必要提出一种新型改良的边缘终接，从而解决上述难题与局限。
发明内容
因此，本发明的一个方面在于，提出了一种新型、改良的边缘端接结构，以降低在器件边缘终接区中的电场拥挤效应，并且提出了一种对表面电荷较不敏感，表面电场较低的紧凑的终接。它的形成是通过在重掺杂区中形成多个终接沟槽，并且在重掺杂区中终接沟槽的底部形成掺杂区，作为边缘终接的掩埋保护环。
确切地说，本发明的一个方面在于，提出了一种半导体功率器件的新型改良型边缘终接结构，通过在边缘终接区中开启的多个终接沟槽附近的区域下方或周围，形成多个掩埋的保护环。理论上，浮动保护环的夹断限制两个沟槽之间的每个台面结构上的电压降。因此，本发明的一个重要方面在于，设计两个沟槽之间的台面结构的宽度以及间距的增量，获得适宜高压器件应用的击穿电压，而掩埋的保护环对于表面电荷不敏感。
本发明的另一个方面在于，提出了一种半导体功率器件的新型改良型边缘终接结构，通过在交替沟槽的侧壁附近和底部，形成多个终接沟槽和保护环，从而克服当台面结构轻掺杂时，相邻保护环短接的电势问题。每两个保护环形成在两个终接沟槽底部，保护环掺杂区没有包围中间的终接沟槽。不带保护环掺杂区的终接沟槽，不具有沿侧壁的P-区，因此能够承受掩埋的保护环夹断所限制的高击穿电压。
本发明的一个较佳实施例主要提出了一种沉积设置在半导体衬底中的半导体功率器件，该半导体功率器件具有一个有源晶胞器件元区和一个边缘终接区。边缘终接区包含多个终接沟槽，终接沟槽内衬一个绝缘层，并用栅极材料填充。边缘终接还包括多个掩埋的保护环，作为半导体衬底中的掺杂区，位于终接沟槽附近。在本发明的一个实施例中，多个掩埋的保护环作为半导体衬底中的掺杂区，位于终接沟槽的底面下方。在另一个实施例中，多个掩埋的保护环作为半导体衬底中的掺杂区，位于终接沟槽的底面下方以及下部周围。在另一个实施例中，多个掩埋的保护环作为半导体衬底中的掺杂区，位于终接沟槽的底面下方以及终接沟槽的侧壁附近，其中掩埋的保护环沉积设置在交替的终接沟槽附近，每两个保护环都被中间终接沟槽分开，下方没有掩埋的保护环。
阅读以下较佳实施例的详细说明并参照多种附图后，本发明的这样和那样的特点和优势，对于本领域的技术人员而言，无疑是显而易见的。
附图说明
图1表示HV器件结构传统的边缘终接结构的剖面图。
图2A表示本发明所述的用于高压（HV）器件，带有掩埋保护环的边缘终接结构的剖面图。
图2B表示带有掩埋保护环的边缘终接的一种可选结构的剖面图，其中沟槽多晶硅电极不是浮动的，而是连接到相邻的外围台面结构P区。
图3表示本发明的一个可选实施例，与另一种可选结构一同制备的带有掩埋保护环的另一种边缘终接结构的剖面图。
图4A-4N表示用于图2所示类型的带有掩埋保护环的边缘终接的制备工艺的剖面图。
图5A-5I表示用于图2所示类型的带有掩埋保护环的边缘终接的另一种制备工艺的剖面图。
具体实施方式
图2A表示本发明所述的用于高压（HV）器件，带有掩埋保护环的边缘终接100结构的剖面图，其中含有一个重掺杂的N区110，形成在轻掺杂N-型衬底105上。P-型本体区112也形成在重掺杂的N区110上方。边缘终接100包括多个边缘终接沟槽120，内衬电介质层125（例如氧化层），在沟槽的侧壁和底面上，然后用导电材料（例如多晶硅）填充。掺杂P-型区130的掩埋保护环，形成在衬底105中，在每个边缘终接沟槽120的底面下方。通过边缘终接沟槽120的植入，制备掩埋保护环掺杂区130，这还将在下文中详细介绍。掩埋保护环130的夹断局限了边缘终接沟槽之间的整个台面结构区W台面结构上的电压降。因此，提高功率器件的击穿电压的关键设计参数就是台面结构的宽度W台面结构以及沟槽120之间的间距增量W台面结构。由于利用顶部植入，保护环直接形成在沟槽下方，台面结构宽度W台面结构决定了保护环间距。保护环间距决定了它们之间的夹断电压。对于位于有源区边缘的环，间距通常很小，并且随着距离的增加，而增大。参数决定了保护环间距的变化梯度，并且是终接的一个重要优化参数。由于衬底105中的掩埋保护环很深，因此，随着间距的增大，掩埋保护环对表面电荷较不敏感。这使得终接更加耐受钝化薄膜的电荷，在高温反向偏压可靠性测试时，成型混料偏移。
图2B表示一种可选的边缘终接100-1的剖面图，其中如图2A所示，沟槽多晶硅电极不是浮动的，而是通过形成在沟槽多晶硅电极的顶面和相邻的P区之间的导电接头，连接到附近的外围台面结构P区。这是为了断开形成在边缘终接中的寄生PMOS。
图3表示本发明的一个可选实施例，与另一种可选结构一同制备的带有掩埋保护环的另一种边缘终接结构100’的剖面图。同图2所示的边缘终接类似，掩埋保护环要求高压（HV）器件具有一个重掺杂的N区110，形成在轻掺杂的N-型衬底105上。边缘终接100’形成在有源器件元区99附近，边缘终接100’包括多个边缘终接沟槽120，在沟槽的侧壁和底面上内衬电介质层125，并用导电材料填充。掩埋保护环作为掺杂区130’，包围着交替沟槽120，也就是说，两个沟槽被掺杂区130’包围着，同时被掺杂区130’不包围的中间沟槽隔开。交替的掩埋保护环结构，是为了防止沿相邻沟槽侧壁的保护环130’的P型掺杂区短路，从而显著降低了保护环可承受的最大的击穿电压。当保护环通过表面P区和侧壁P表层短路时，它们将无法在两者之间产生电压。因此，相邻保护环之间的电压降将远低于JFET夹断电压，从而削弱边缘终接的整体电压闭锁能力。当台面结构掺杂很轻时，在交替沟槽上的保护环掺杂就变得非常有必要。不带掩埋保护环的终接沟槽没有沿侧壁的P型掺杂区。因此，通过作为掺杂区130’的掩埋保护环，包围着沟槽120，就在边缘终接中获得了可承受的高压，并且仅仅受到保护环之间的夹断的限制。
图4A至4N表示用于带有图2所示类型的掩埋保护环的边缘终接的制备过程的剖面图。如图4A所示，制备过程从用硬掩膜201覆盖N型衬底205开始，在硬掩膜层201（图4B）上方制备一个沟槽掩膜202（可以是光致抗蚀剂掩膜）并形成图案，在硬掩膜201上，形成多个开口207。然后，除去沟槽掩膜202，通过硬掩膜201的开口207刻蚀衬底205，形成终接沟槽210，沟槽深度约为5至8μm。然后除去硬掩膜201（图4C）。在图4D中，衬里氧化层215形成在每个沟槽210的侧壁和底部，随后在衬里氧化层215上方设置一个氮化层217。氧化层215可以利用热氧化或化学气相设置（CVD）形成。在图4E中，氧化物218填充在终接沟槽中，避免在沟槽内形成空洞，只要根据沟槽形状，使它们处于氮化层表面217以下就行。利用CVD工艺，完成氧化物218的设置。通过化学机械平整化（CMP）工艺（图4F），除去氧化层218的顶部，并且在氮化层217处停止。在图4G中，使用植入掩膜219，然后通过湿/干刻蚀工艺，除去未被植入掩膜覆盖的终接沟槽210中的氧化层218，氧化物刻蚀终止在氮化层217上。然后，进行P型植入，在终接沟槽210的底部的衬底205中制备掩埋保护环区220，刻蚀掉氧化层218（图4H）。在图4I中，除去植入掩膜219。所有终接沟槽210中剩余的氧化层218和氮化层217也除去。在图4J中，在终接沟槽210中设置第一导电材料225（例如多晶硅），随后回刻第一导电材料225，终点在氧化物215的表面上（图4K）。第一导电材料可以称为源极多晶硅，并且可以接地到器件的源极。还可选择，回刻导电材料225，终点在衬底205的表面上，或者甚至低于衬底205的表面。然后，回刻氧化物215，除去硅衬底205顶面的氧化层215（图4L）。在图4M-4N中，在导电材料225和衬底205上方，生长一个热氧化层230，随后在氧化层230上方，设置第二导电材料240（例如多晶硅）。第二导电材料240可以称为栅极多晶硅，将连接到器件的栅极。
图5A-5I表示图2所示类型的带有掩埋保护环的边缘终接的另一种制备方法的剖面图。如图5A所示，制备工艺从硬掩膜301覆盖N型衬底305开始，在硬掩膜301上方，制备沟槽掩埋302并形成图案（图5B），以便在硬掩膜301中形成多个开口307。然后，除去沟槽掩埋302，通过硬掩膜301的开口307，刻蚀衬底305，形成多个终接沟槽310。然后，除去硬掩膜301（图5C）。在图5D中，在衬底305上方，形成光致抗蚀剂材料312，覆盖衬底305的顶面，并且填充终接沟槽310。在图5E中，在光致抗蚀剂层312上方，使用植入掩埋314，通过光刻，暴露植入掩埋314，除去裸露终接沟槽310的光致抗蚀剂层312（图5F）。在图5G中，通过打开的终接沟槽310，进行P型植入，在终接沟槽310的底面下方的衬底305中，形成掩埋保护环掺杂区310（图5H）。在图5I中，利用热氧化或化学气相设置（CVD）工艺，在终接沟槽310的侧壁和底部形成衬里氧化层325。继续进行与上述图4J至4N所述相同的工艺，制成图2所示类型的带有掩埋保护环的边缘终接。
尽管本发明已经详细说明了现有的较佳实施例，但应理解这些说明不应作为本发明的局限。本领域的技术人员阅读上述详细说明后，各种变化和修正无疑是显而易见的。因此，应认为所附的权利要求书涵盖本发明的真实意图和范围内的全部变化和修正。

Claims (9)

1.一种半导体功率器件，其设置在半导体衬底中，包括一个形成在轻掺杂区上方的重掺杂区，并且具有一个有源器件元区和一个边缘终接区，其特征在于，所述的边缘终接区包括多个终接沟槽，形成在所述的重掺杂区上，内衬电介质层，并且填充导电材料；以及
多个掩埋保护环，作为掺杂区，形成在所述的半导体衬底的所述的轻掺杂区中，位于终接沟槽附近。
2.如权利要求1所述的半导体功率器件，其特征在于，
多个所述的掩埋保护环，作为掺杂区，形成在所述的半导体衬底的所述的轻掺杂区中，紧挨着终接沟槽的底面下方。
3.如权利要求1所述的半导体功率器件，其特征在于，
多个所述的掩埋保护环，作为掺杂区，形成在所述的半导体衬底的所述的轻掺杂区中，紧挨着终接沟槽的底面下方，并且包围着终接沟槽的下部。
4.如权利要求1所述的半导体功率器件，其特征在于，
多个所述的掩埋保护环，作为掺杂区，形成在所述的半导体衬底的所述的轻掺杂区中，紧挨着终接沟槽的底面下方，并且包围着终接沟槽的下部，其中所述的掩埋保护环设置在相间的终接沟槽周围，每两个所述的掩埋保护环都被一个中间终接沟槽隔开，所述的掺杂区不包围所述的中间终接沟槽。
5.如权利要求1所述的半导体功率器件，其特征在于，
多个所述的终接沟槽在半导体衬底中打开的深度为5至8微米。
6.一种用于在半导体衬底中制备半导体功率器件的方法，该半导体功率器件含有一个形成在轻掺杂区上方的重掺杂区，并且具有一个有源器件元区和一个边缘终接区，其特征在于，该方法包括：
在边缘终接区中所述的重掺杂区上，打开多个终接沟槽；
通过终接沟槽，植入多个掺杂区，作为掩埋保护环，在所述的半导体衬底的所述的轻掺杂区中，紧靠终接沟槽；并且
用导电填充物，填充所述的终接沟槽，并将所述的导电填充物电连接到所述的半导体功率器件的源极电极。
7.如权利要求6所述的方法，其特征在于，
所述的通过终接沟槽植入多个掺杂区的步骤，还包括利用植入掩膜，以便在所选的终接沟槽下方，选择性地植入掺杂区。
8.如权利要求6所述的方法，其特征在于，
所述的通过终接沟槽植入多个掺杂区的步骤，还包括用光致抗蚀剂材料填充终接沟槽，随后利用掩膜，在所选的终接沟槽中，选择性地裸露出光致抗蚀剂材料，用于光刻辐射，然后除去所选的终接沟槽上的掩膜和光致抗蚀剂材料，在所选的终接沟槽下方，选择性地植入掺杂区。
9.如权利要求7所述的方法，其特征在于，
所述的通过终接沟槽植入多个掺杂区的步骤，还包括在所述的终接沟槽中，制备一个刻蚀终止层，然后用电介质材料填充终接沟槽，随后利用掩膜，在所选的终接沟槽中，选择性地刻蚀电介质材料，在所选的终接沟槽下方，选择性地植入掺杂区。
CN201210244919.6A 2011-07-19 2012-07-16 具有新型结构的高压(hv)器件端接及其制备方法 Active CN102891169B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/135,982 US8803251B2 (en) 2011-07-19 2011-07-19 Termination of high voltage (HV) devices with new configurations and methods
US13/135,982 2011-07-19

Publications (2)

Publication Number Publication Date
CN102891169A true CN102891169A (zh) 2013-01-23
CN102891169B CN102891169B (zh) 2015-04-08

Family

ID=47534627

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210244919.6A Active CN102891169B (zh) 2011-07-19 2012-07-16 具有新型结构的高压(hv)器件端接及其制备方法

Country Status (3)

Country Link
US (1) US8803251B2 (zh)
CN (1) CN102891169B (zh)
TW (1) TWI511270B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681785A (zh) * 2012-09-19 2014-03-26 株式会社东芝 半导体装置
CN107251198A (zh) * 2015-01-27 2017-10-13 Abb瑞士股份有限公司 绝缘栅功率半导体装置以及用于制造这种装置的方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160372542A9 (en) * 2011-07-19 2016-12-22 Yeeheng Lee Termination of high voltage (hv) devices with new configurations and methods
US8575685B2 (en) * 2011-08-25 2013-11-05 Alpha And Omega Semiconductor Incorporated Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path
US8809948B1 (en) 2012-12-21 2014-08-19 Alpha And Omega Semiconductor Incorporated Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
US8951867B2 (en) 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
US8753935B1 (en) 2012-12-21 2014-06-17 Alpha And Omega Semiconductor Incorporated High frequency switching MOSFETs with low output capacitance using a depletable P-shield
US9105494B2 (en) 2013-02-25 2015-08-11 Alpha and Omega Semiconductors, Incorporated Termination trench for power MOSFET applications
JP6135364B2 (ja) * 2013-07-26 2017-05-31 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
US20150118810A1 (en) * 2013-10-24 2015-04-30 Madhur Bobde Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path
US10395970B2 (en) * 2013-12-05 2019-08-27 Vishay-Siliconix Dual trench structure
US9899477B2 (en) * 2014-07-18 2018-02-20 Infineon Technologies Americas Corp. Edge termination structure having a termination charge region below a recessed field oxide region
US9281368B1 (en) 2014-12-12 2016-03-08 Alpha And Omega Semiconductor Incorporated Split-gate trench power MOSFET with protected shield oxide
US9673314B2 (en) 2015-07-08 2017-06-06 Vishay-Siliconix Semiconductor device with non-uniform trench oxide layer
US10388781B2 (en) 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
CN108288641A (zh) * 2018-04-08 2018-07-17 无锡新洁能股份有限公司 一种功率半导体器件终端结构及其制造方法
DE102019103899A1 (de) 2019-02-15 2020-08-20 Infineon Technologies Ag Leistungshalbleiterbauelement und Verfahren zur Verarbeitung eines Leistungshalbleiterbauelements
CN111725292A (zh) * 2019-03-19 2020-09-29 比亚迪股份有限公司 功率器件终端结构及其制作方法以及功率器件
JP6648331B1 (ja) 2019-06-07 2020-02-14 新電元工業株式会社 半導体装置及び半導体装置の製造方法
CN114864704B (zh) * 2022-07-11 2022-09-27 成都功成半导体有限公司 具有终端保护装置的碳化硅jbs及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462376B1 (en) * 1999-01-11 2002-10-08 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Power MOS element and method for producing the same
US20060214242A1 (en) * 2005-03-04 2006-09-28 International Rectifier Corporation Termination for SiC trench devices
US20070202650A1 (en) * 2000-04-04 2007-08-30 International Rectifier Corporation Low voltage power MOSFET device and process for its manufacture
US20080001217A1 (en) * 2006-07-03 2008-01-03 Nec Electronics Corporation Semiconductor device having superjunction structure and method for manufacturing the same
CN101371337A (zh) * 2005-01-14 2009-02-18 国际整流器公司 具有不同的氧化物厚度的沟槽肖特基势垒二极管
CN101421832A (zh) * 2004-03-01 2009-04-29 国际整流器公司 沟槽器件的自对准接触结构
US20100038675A1 (en) * 2008-08-14 2010-02-18 Fuji Electric Device Technology Co., Ltd. Power semiconductor devices and methods for manufacturing the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7186609B2 (en) * 1999-12-30 2007-03-06 Siliconix Incorporated Method of fabricating trench junction barrier rectifier
JP4357753B2 (ja) * 2001-01-26 2009-11-04 株式会社東芝 高耐圧半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462376B1 (en) * 1999-01-11 2002-10-08 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Power MOS element and method for producing the same
US20070202650A1 (en) * 2000-04-04 2007-08-30 International Rectifier Corporation Low voltage power MOSFET device and process for its manufacture
CN101421832A (zh) * 2004-03-01 2009-04-29 国际整流器公司 沟槽器件的自对准接触结构
CN101371337A (zh) * 2005-01-14 2009-02-18 国际整流器公司 具有不同的氧化物厚度的沟槽肖特基势垒二极管
US20060214242A1 (en) * 2005-03-04 2006-09-28 International Rectifier Corporation Termination for SiC trench devices
US20080001217A1 (en) * 2006-07-03 2008-01-03 Nec Electronics Corporation Semiconductor device having superjunction structure and method for manufacturing the same
US20100038675A1 (en) * 2008-08-14 2010-02-18 Fuji Electric Device Technology Co., Ltd. Power semiconductor devices and methods for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681785A (zh) * 2012-09-19 2014-03-26 株式会社东芝 半导体装置
CN107251198A (zh) * 2015-01-27 2017-10-13 Abb瑞士股份有限公司 绝缘栅功率半导体装置以及用于制造这种装置的方法
CN107251198B (zh) * 2015-01-27 2020-08-14 Abb电网瑞士股份公司 绝缘栅功率半导体装置以及用于制造这种装置的方法

Also Published As

Publication number Publication date
TWI511270B (zh) 2015-12-01
US8803251B2 (en) 2014-08-12
CN102891169B (zh) 2015-04-08
TW201308575A (zh) 2013-02-16
US20130020671A1 (en) 2013-01-24

Similar Documents

Publication Publication Date Title
CN102891169B (zh) 具有新型结构的高压(hv)器件端接及其制备方法
US7915155B2 (en) Double trench for isolation of semiconductor devices
US7410891B2 (en) Method of manufacturing a superjunction device
JP5154347B2 (ja) 超接合半導体ディバイスおよび超接合半導体ディバイスの製造方法
EP2613357B1 (en) Field-effect transistor and manufacturing method thereof
US8836017B2 (en) Semiconductor device and fabricating method thereof
US20100244125A1 (en) Power semiconductor device structure for integrated circuit and method of fabrication thereof
KR100731141B1 (ko) 반도체소자 및 그의 제조방법
US20130307060A1 (en) Trench semiconductor devices with edge termination structures, and methods of manufacture thereof
US8378445B2 (en) Trench structures in direct contact
TW201246390A (en) Semiconductor device and manufacturing method thereof
CN105321824B (zh) 半导体装置的制造方法
TW200302575A (en) High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon
JP5298565B2 (ja) 半導体装置およびその製造方法
JP2010177373A (ja) 半導体装置及び半導体装置の製造方法
JP2018046251A (ja) 半導体装置およびその製造方法
US20160013267A1 (en) Termination of high voltage (hv) devices with new configurations and methods
JP6391136B2 (ja) 高電圧ダイオード
US20200098857A1 (en) Narrow-mesa super-junction mosfet
JP2011018764A (ja) 半導体装置
CN104103518A (zh) 半导体功率器件的制作方法
KR100853799B1 (ko) 트렌치 게이트 반도체 소자 및 그의 제조 방법
US20200279912A1 (en) Super junction semiconductor device and method of manufacturing the same
US20140015040A1 (en) Power semiconductor device and fabrication method thereof
CN216871979U (zh) 三栅极mos晶体管以及电子电路

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20200424

Address after: Ontario, Canada

Patentee after: World semiconductor International Limited Partnership

Address before: 475 oakmead Park Road, Sunnyvale, California, USA

Patentee before: Alpha and Omega Semiconductor Inc.