TW201308575A - 半導體功率元件及其製備方法 - Google Patents

半導體功率元件及其製備方法 Download PDF

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TW201308575A
TW201308575A TW101125971A TW101125971A TW201308575A TW 201308575 A TW201308575 A TW 201308575A TW 101125971 A TW101125971 A TW 101125971A TW 101125971 A TW101125971 A TW 101125971A TW 201308575 A TW201308575 A TW 201308575A
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termination trench
doped region
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Yee-Hang Lee
Madhur Bobde
Yongping Ding
Jong-Oh Kim
Anup Bhalla
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Alpha & Omega Semiconductor
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Abstract

本發明揭露了一種設置在半導體基板中的半導體功率元件，含有一個形成在輕摻雜區上的重摻雜區，並且具有一個主動元件元區和一個邊緣終接區。邊緣終接區包括複數個終接溝槽，形成在重摻雜區中，終接溝槽內襯有電介質層，並且用導電材料填充。邊緣終接還包括複數個掩埋保護環，作為摻雜區，在半導體基板的輕摻雜區中，緊靠終接溝槽。

Description

半導體功率元件及其製備方法
本發明主要關於半導體功率元件。更確切的說，本發明是關於用於高壓（High Voltage, HV）元件的改良型邊緣終接的結構及製備方法，以便增強可靠性，減少終接區所占的面積，同時保持高擊穿電壓。
終接區中傳統的浮動保護環不足以承受高壓（HV）元件的高擊穿電壓，如第1圖所示，高壓（HV）元件具有重摻雜N區110（例如摻雜濃度達1016摻雜物/cm3），在基板105的頂面以下2至5微米的深度。重摻雜N區110中的N-電荷過高，浮動保護環為植入在重摻雜N區110中的P型摻雜區，為了承受終接區中較高的擊穿電壓，浮動保護環需要電荷補償。傳統的邊緣終接帶有氧化物內襯溝槽中的電壓降，並不能有效解決由於這種邊緣終接僅可以承受高達100伏的擊穿電壓而造成的問題。100伏以下的擊穿電壓是由於溝槽下方的顯著的場擁擠效應而引起的。當需要較高的電壓運行時，邊緣終接處的低擊穿電壓會限制高壓（HV）元件的應用。
因此，在功率半導體元件設計和製備領域中，有必要提出一種改良的邊緣終接，從而解決上述難題與局限。
因此，本發明的一個方面在於，提出了一種改良的邊緣端接結構，以降低在元件邊緣終接區中的電場擁擠效應，並且提出了一種對表面電荷較不敏感，表面電場較低的緊湊的終接。它的形成是通過在重摻雜區中形成多個終接溝槽，並且在重摻雜區中終接溝槽的底部形成摻雜區，作為邊緣終接的掩埋保護環。
確切地說，本發明的一個方面在於，提出了一種半導體功率元件的改良型邊緣終接結構，通過在邊緣終接區中開啟的多個終接溝槽附近的區域下方或周圍，形成多個掩埋的保護環。理論上，浮動保護環的夾斷限制兩個溝槽之間的每個臺面結構上的電壓降。因此，本發明的一個重要方面在於，設計兩個溝槽之間的臺面結構的寬度以及間距的增量，獲得適宜高壓元件應用的擊穿電壓，而掩埋的保護環對於表面電荷不敏感。
本發明的另一個方面在於，提出了一種半導體功率元件的改良型邊緣終接結構，通過在交替溝槽的側壁附近和底部，形成多個終接溝槽和保護環，從而克服當臺面結構輕摻雜時，相鄰保護環短接的電勢問題。每兩個保護環形成在兩個終接溝槽底部，保護環摻雜區沒有包圍中間的終接溝槽。不帶保護環摻雜區的終接溝槽，不具有沿側壁的P-區，因此能夠承受掩埋的保護環夾斷所限制的高擊穿電壓。
本發明的一個較佳實施例主要提出了一種沉積設置在半導體基底中的半導體功率元件，該半導體功率元件具有一個主動元件元區和一個邊緣終接區。邊緣終接區包含多個終接溝槽，終接溝槽內襯一個絕緣層，並用柵極材料填充。邊緣終接還包括多個掩埋的保護環，作為半導體基板中的摻雜區，位於終接溝槽附近。在本發明的一個實施例中，多個掩埋的保護環作為半導體基板中的摻雜區，位於終接溝槽的底面下方。在另一個實施例中，多個掩埋的保護環作為半導體基板中的摻雜區，位於終接溝槽的底面下方以及下部周圍。在另一個實施例中，多個掩埋的保護環作為半導體基板中的摻雜區，位於終接溝槽的底面下方以及終接溝槽的側壁附近，其中掩埋的保護環沉積設置在交替的終接溝槽附近，每兩個保護環都被中間終接溝槽分開，下方沒有掩埋的保護環。
閱讀以下較佳實施例的詳細說明並參照多種圖式後，本發明的這樣和那樣的特點和優勢，對於本領域的通常知識者而言，無疑是容易理解的。
第2A圖表示本發明所述的用於高壓（HV）元件，帶有掩埋保護環的邊緣終接100結構的剖面圖，其中含有一個重摻雜N區110，形成在輕摻雜N-型基板105上。P-型本體區112也形成在重摻雜N區110上方。邊緣終接100包括多個邊緣終接溝槽120，內襯電介質層（例如氧化層），在溝槽的側壁和底面上，然後用導電材料（例如多晶矽）填充。P-型掩埋保護環摻雜區130，形成在基板105中，在每個邊緣終接溝槽120的底面下方。通過邊緣終接溝槽120的植入，製備掩埋保護環摻雜區130，這還將在下文中詳細介紹。掩埋保護環的夾斷局限了邊緣終接溝槽120之間的整個臺面結構區臺面結構W上的電壓降。因此，提高功率元件的擊穿電壓的關鍵設計參數就是臺面結構寬度δW臺面結構W以及邊緣終接溝槽120之間的間距增量臺面結構W。由於利用頂部植入，掩埋保護環直接形成在邊緣終接溝槽120下方，臺面結構寬度δW臺面結構W決定了掩埋保護環間距。掩埋保護環間距決定了它們之間的夾斷電壓。對於位於主動區邊緣的環，間距通常很小，並且隨著距離的增加，而增大。參數決定了掩埋保護環間距的變化梯度，並且是終接的一個重要優化參數。由於基板105中的掩埋保護環很深，因此，隨著間距的增大，掩埋保護環對表面電荷較不敏感。這使得終接更加耐受鈍化薄膜的電荷，在高溫反向偏壓可靠性測試時，成型混料偏移。
第2B圖表示一種可選的邊緣終接100-1的剖面圖，其中如第2A圖所示，溝槽多晶矽電極不是浮動的，而是通過形成在溝槽多晶矽電極的頂面和相鄰的P區之間的導電接頭，連接到附近的週邊臺面結構P區。這是為了斷開形成在邊緣終接中的寄生PMOS。
第3圖表示本發明的一個可選實施例，與另一種可選結構一同製備的帶有掩埋保護環的另一種邊緣終接100’結構的剖面圖。同第2A、2B圖所示的邊緣終接類似，掩埋保護環要求高壓（HV）元件具有一個重摻雜N區110，形成在輕摻雜的N-型基板105上。邊緣終接100’形成在主動元件元區99附近，邊緣終接100’包括多個邊緣終接溝槽120，在邊緣終接溝槽120的側壁和底面上內襯電介質層125，並用導電材料填充。掩埋保護環作為摻雜區130’，包圍著交替邊緣終接溝槽120，也就是說，兩個邊緣終接溝槽120被摻雜區130’包圍著，同時被摻雜區130’不包圍的中間邊緣終接溝槽120隔開。交替的掩埋保護環結構，是為了防止沿相鄰邊緣終接溝槽120側壁的摻雜區130’的P型摻雜區短路，從而顯著降低了掩埋保護環可承受的最大的擊穿電壓。當掩埋保護環通過表面P區和側壁P表層短路時，它們將無法在兩者之間產生電壓。因此，相鄰掩埋保護環之間的電壓降將遠低於JFET夾斷電壓，從而削弱邊緣終接的整體電壓閉鎖能力。當臺面結構摻雜很輕時，在交替邊緣終接溝槽12上的掩埋保護環摻雜就變得非常有必要。不帶掩埋保護環的邊緣終接溝槽120沒有沿側壁的P型摻雜區。因此，通過作為摻雜區130’的掩埋保護環，包圍著邊緣終接溝槽120，就在邊緣終接中獲得了可承受的高壓，並且僅僅受到掩埋保護環之間的夾斷的限制。
第4A圖至第4N圖表示用於帶有第2A、2B圖所示類型的掩埋保護環的邊緣終接的製備過程的剖面圖。如第4A圖所示，製備過程從用硬掩膜201覆蓋N型基板205開始，在硬掩膜201層（第4B圖）上方製備一個溝槽掩膜202（可以是光致抗蝕劑掩膜）並形成圖案，在硬掩膜201上，形成多個開口207。然後，除去溝槽掩膜202，通過硬掩膜201的開口207刻蝕基板205，形成終接溝槽210，溝槽深度約為5至8μm。然後除去硬掩膜201（第4C圖）。在第4D圖中，襯裏氧化層215形成在每個終接溝槽210的側壁和底部，隨後在襯裏氧化層215上方設置一個氮化層217。襯裏氧化層215可以利用熱氧化或化學氣相設置（CVD）形成。在第4E圖中，氧化物218填充在終接溝槽中，避免在溝槽內形成空洞，只要根據溝槽形狀，使它們處於氮化層217表面以下就行。利用CVD製程，完成氧化物218的設置。通過化學機械平整化（CMP）製程（第4F圖），除去氧化物218的頂部，並且在氮化層217處停止。在第4G圖中，使用植入掩膜219，然後通過濕/幹刻蝕製程，除去未被植入掩膜219覆蓋的終接溝槽210中的氧化物218，氧化物218刻蝕終止在氮化層217上。然後，進行P型植入，在終接溝槽210的底部的基板205中製備掩埋保護環區220，刻蝕掉氧化物218（第4H圖）。在第4I圖中，除去植入掩膜219。所有終接溝槽210中剩餘的氧化物218和氮化層217也除去。在第4J圖中，在終接溝槽210中設置第一導電材料225（例如多晶矽），隨後回刻第一導電材料225，終點在襯裏氧化層215的表面上（第4K圖）。第一導電材料225可以稱為源極多晶矽，並且可以接地到元件的源極。還可選擇，回刻第一導電材料225，終點在基板205的表面上，或者甚至低於基板205的表面。然後，回刻襯裏氧化層215，除去矽基板205頂面的襯裏氧化層215（第4L圖）。在第4M- 4N圖中，在第一導電材料225和基板205上方，生長一個熱氧化層230，隨後在熱氧化層230上方，設置第二導電材料240（例如多晶矽）。第二導電材料240可以稱為柵極多晶矽，將連接到元件的柵極。
第5A-5I圖表示第2A、B圖所示類型的帶有掩埋保護環的邊緣終接的另一種製備方法的剖面圖。如第5A圖所示，製備技術從硬掩膜301覆蓋N型基板305開始，在硬掩膜301上方，製備溝槽掩埋302並形成圖案（第5B圖），以便在硬掩膜301中形成多個開口307。然後，除去溝槽掩埋302，通過硬掩膜301的開口307，刻蝕基板305，形成多個終接溝槽310。然後，除去硬掩膜301（第5C圖）。在第5D圖中，在基板305上方，形成光致抗蝕劑材料，覆蓋基板305的頂面，並且填充終接溝槽310。在第5E圖中，在光致抗蝕劑層312上方，使用植入掩埋314，通過光刻，暴露植入掩埋314，除去裸露終接溝槽310的光致抗蝕劑層312（第5F圖）。在第5G圖中，通過打開的終接溝槽310，進行P型植入，在終接溝槽310的底面下方的基板305中，形成掩埋保護環摻雜區320（第5H圖）。在第5I圖中，利用熱氧化或化學氣相設置（CVD）製程，在終接溝槽310的側壁和底部形成襯裏氧化層325。繼續進行與上述第4J至4N圖所述相同的製程，製成第2A、B圖所示類型的帶有掩埋保護環的邊緣終接。
儘管本發明已經詳細說明了現有的較佳實施例，但應理解這些說明不應作為本發明的局限。本領域的通常知識者閱讀上述詳細說明後，各種變化和修正無疑是容易理解的。因此，應認為所附的申請專利範圍涵蓋本發明的真實意圖和範圍內的全部變化和修正。
100、100-1、100’．．．邊緣終接
105、205、305．．．基板
110．．．重摻雜N區
112．．．P-型本體區
120．．．邊緣終接溝槽
130、320．．．掩埋保護環摻雜區
W．．．臺面結構
δW．．．臺面結構寬度
125．．．電介質層
130’．．．摻雜區
99．．．主動元件元區
201、301．．．硬掩膜
202．．．溝槽掩膜
207、307．．．開口
210、310．．．終接溝槽
215、325．．．襯裏氧化層
217．．．氮化層
218．．．氧化物
219．．．掩膜
220．．．掩埋保護環區
225．．．第一導電材料
230．．．熱氧化層
240．．．第二導電材料
302．．．溝槽掩埋
312．．．光致抗蝕劑層
314．．．植入掩埋
第1圖 表示HV元件結構傳統的邊緣終接結構的剖面圖。
第2A圖 表示本發明所述的用於高壓（HV）元件，帶有掩埋保護環的邊緣終接結構的剖面圖。
第2B圖 表示帶有掩埋保護環的邊緣終接的一種可選結構的剖面圖，其中溝槽多晶矽電極不是浮動的，而是連接到相鄰的週邊臺面結構P區。
第3圖 表示本發明的一個可選實施例，與另一種可選結構一同製備的帶有掩埋保護環的另一種邊緣終接結構的剖面圖。
第4A-4N圖 表示用於第2圖所示類型的帶有掩埋保護環的邊緣終接的製備技術的剖面圖。
第5A-5I圖 表示用於第2圖所示類型的帶有掩埋保護環的邊緣終接的另一種製備技術的剖面圖。
100．．．邊緣終接
105．．．基板
110．．．重摻雜N區
112．．．P-型本體區
120．．．邊緣終接溝槽
130．．．掩埋保護環摻雜區
W．．．臺面結構
δW．．．臺面結構寬度

Claims (9)

  1. 一種半導體功率元件，其設置在一半導體基板中，包括一形成在一輕摻雜區上方的重摻雜區，並且具有一主動元件元區和一邊緣終接區，該邊緣終接區包括複數個終接溝槽，形成在該重摻雜區上，該終接溝槽內襯有一電介質層，並且填充導電材料；以及
    複數個掩埋保護環，作為一摻雜區，形成在該半導體基板的該輕摻雜區中，位於該終接溝槽附近。
  2. 如申請專利範圍第1項所述之半導體功率元件，其中該複數個掩埋保護環，作為一摻雜區，形成在該半導體基板的該輕摻雜區中，緊靠著該終接溝槽的底面下方。
  3. 如申請專利範圍第1項所述之半導體功率元件，其中該複數個掩埋保護環，作為一摻雜區，形成在該半導體基板的該輕摻雜區中，緊靠著該終接溝槽的底面下方，並且包圍著該終接溝槽的下部。
  4. 如申請專利範圍第1項所述之半導體功率元件，其中該複數個掩埋保護環，作為一摻雜區，形成在該半導體基板的該輕摻雜區中，緊靠著該終接溝槽的底面下方，並且包圍著該終接溝槽的下部，其中該掩埋保護環設置在相間的該終接溝槽周圍，每兩個該掩埋保護環都被一中間終接溝槽隔開，該摻雜區不包圍該中間終接溝槽。
  5. 如申請專利範圍第1項所述之半導體功率元件，其中該複數個終接溝槽在該半導體基板中打開的深度為5至8微米。
  6. 一種用於在半導體基板中製備半導體功率元件的方法，該半導體功率元件含有形成在一輕摻雜區上方的一重摻雜區，並且具有一主動元件元區和一邊緣終接區，該方法包括：
    在該邊緣終接區中之該重摻雜區上，打開複數個終接溝槽；
    通過該終接溝槽，植入複數個摻雜區，作為複數個掩埋保護環，在該半導體基板的該輕摻雜區中，緊靠該終接溝槽；以及
    用一導電填充物，填充該終接溝槽，並將該導電填充物電連接到該半導體功率元件的源極電極。
  7. 如申請專利範圍第6項所述之方法，其中通過該終接溝槽植入該複數個摻雜區的步驟，還包括：利用植入掩膜，以便在所選的該終接溝槽下方，選擇性地植入該摻雜區。
  8. 如申請專利範圍第6項所述之方法，其中通過該終接溝槽植入該複數個摻雜區的步驟，還包括：用光致抗蝕劑材料填充該終接溝槽，隨後利用掩膜，在所選的該終接溝槽中，選擇性地裸露出光致抗蝕劑材料，用於光刻輻射，然後除去所選的該終接溝槽上的掩膜和光致抗蝕劑材料，在所選的該終接溝槽下方，選擇性地植入該摻雜區。
  9. 如申請專利範圍第7項所述之方法，其中通過該終接溝槽植入該複數個摻雜區的步驟，還包括：在該終接溝槽中，製備一刻蝕終止層，然後用電介質材料填充該終接溝槽，隨後利用掩膜，在所選的該終接溝槽中，選擇性地刻蝕電介質材料，在所選的該終接溝槽下方，選擇性地植入該摻雜區。
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