CN102754196A - 利用传输电介质的板化封装 - Google Patents

利用传输电介质的板化封装 Download PDF

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CN102754196A
CN102754196A CN201180008475XA CN201180008475A CN102754196A CN 102754196 A CN102754196 A CN 102754196A CN 201180008475X A CN201180008475X A CN 201180008475XA CN 201180008475 A CN201180008475 A CN 201180008475A CN 102754196 A CN102754196 A CN 102754196A
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dielectric film
layer
curing
wafer
patterning
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CN102754196B (zh
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克里斯多佛·斯坎伦
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Decca Technology Inc
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Cypress Semiconductor Corp
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Abstract

描述了一种板化封装方法，在该方法中多个晶片单元被放置在介电薄膜上。随后，该介电薄膜被固化以将所述多个晶片单元固定在正确位置，然后这些晶片单元被密封。随后，固化的介电薄膜利用无掩膜图案化技术被图案化。

Description

利用传输电介质的板化封装
相关申请
本申请要求已于2010年2月16日提交的第61/305,122号美国临时申请的利益，在此通过引用将其并入。
技术领域
本发明的实施方式涉及板化（panelized）封装的领域。
背景
一种在工业中获得认可的板化封装的常用实施是扇出晶圆级封装（WLP），其中多个晶片单元被朝下放置在一个临时的带状载体上。多个晶片单元和临时的带状载体使用压缩成型工艺以模塑料进行超模压（overmolded）。在模压之后，带状载体被去掉，留下暴露在俗称重组晶圆的结构上的多个晶片单元的有效表面。随后，晶圆级芯片规模封装（WLCSP）积层（build-up）结构在重组晶圆的上部处形成。球栅阵列（BGA）的球状物被附着到重组晶圆上，然后重组晶圆被锯断分割以形成单独的封装件。已观察到晶片单元的放置和超模压工艺可能会造成晶片单元的移位和/或旋转，这导致了有缺陷的封装件和产量损失。
附图简述
图1A到图1N示出一种根据本发明的实施方式的、形成扇出WLP的方法。
图2A到图2L示出一种根据本发明的实施方式的、形成扇出WLP的方法。
详述
本发明的实施方式公开了用以改进板化封装（例如扇出WLCSP）的方法和结构。在以下描述中，关于单晶片应用描述了具体的实施方式。本发明的实施方式也可用在多晶片模块中或者用在晶片和位于模块内的无源器件（如电容器、电感器或电阻器）和/或其他器件（如光学元件、连接器或其它电子器件）的一些组合当中。
以下描述中，阐述了许多具体细节，如具体的配置、组成部分和工艺，等等，以便提供对本发明的透彻的理解。在其他情况下，为了不会不必要地使得本发明难以理解，众所周知的工艺和制造技术未被特别详细地描述。此外，应了解，附图所示的各种实施方式是说明性的代表而且不必按比例绘制。
在此使用的词语“在以上”、“在中间”和“在上”指的是到一个层到其它层的相对位置。一个被沉积或布置在另外一个层以上或以下的层，其可直接接触该另外的层或者可具有一个或多个中间层。一个被沉积或布置在一些层中间的层，其可直接接触这些层或者可有一个或多个中间层。相比之下，在第二层“上”的第一层接触该第二层。
在一种实施方式中，板化封装件通过将多个晶片单元朝下放置在介电薄膜上来创建，所述介电薄膜可被层压在一个临时的载体基板上。然后介电薄膜被固化（cured）用以将多个晶片单元固定在正确位置，致使介电薄膜非感光。固化期间，在介电薄膜材料中发生在分子水平上的改变，其中介电薄膜的力学性能实质上完全形成而且晶片单元永久地附着在生成的刚性介电薄膜上。根据使用的特殊材料，固化可与交联联系在一起。然后多个晶片单元被密封在介电薄膜上。在一实施方式中，密封可通过超模压工艺例如压缩成型来实现。在一实施方式中，密封可通过层压工艺例如真空层压来执行。因为在密封之前，多个晶片单元已被固定到位，所以密封期间，在由于个别晶片单元上所施加的压力会导致个别晶片单元移位和/或旋转的问题的位置处，可减少个别晶片单元的移位和/或旋转。然后临时的载体基板可被从介电薄膜中被释放。然后包括刚性的、固化的、连续的介电薄膜的晶圆级晶片规模封装（WLCSP）积层结构被形成，其中介电薄膜可利用无掩膜图案化技术被图案化。
已观察到，晶片单元的放置和传统加工技术的密封过程可能会导致位于临时带状载体上的多个晶片单元中任何一个的移位和/或方向旋转。这可能是由于晶片单元未被牢固地附着在临时带状载体上、由于带状载体的变形、以及由于密封材料固化期间密封材料的收缩。利用临时带状载体的传统方法的影响或者是归因于第一过孔到晶片单元焊盘的不重合造成的产量损失，或者由于增加了中间形式的焊盘，所述中间形式的焊盘在原晶圆形式上重新选择路径（板化之前）以便以产生大的焊盘为目标来确保第一过孔形成连接而不管晶片单元是否移动。因此，传统的加工工艺要求晶片单元上的焊盘比需要的大，以避免面板的产量损失，因而减少了WLP技术的应用空间。
根据本发明的实施方式，连续的介电薄膜（比如层压的环氧树脂薄膜）可取代临时的牺牲性的带和积层结构中的第一介电层。这有可能降低成本和工艺步骤。在密封之前将多个晶片单元固定在连续的介电薄膜上的正确位置处可减少在面板或网状晶圆内的个别晶片单元的移位和/或方向旋转，从而消除或减少由板化期间晶片单元的不重合所导致的封装组件的产量损失而且允许在晶片单元上的较小的焊盘开口。环氧树脂是一种适合用来形成介电薄膜的材料，因为它可被固化以将多个晶片单元固定到正确位置，还因为类似的环氧树脂可被利用作为超模压或者层压密封的材料。根据本发明的实施方式其他具有合适的粘接性能用于固定到位的多个晶片单元的材料也可被考虑，例如但不限于，聚酰亚胺和硅树脂。
在另一个方面，本发明的实施方式公开了可利用层压技术的板化封装方法。例如，层压可提供穿过临时的载体基板的、相同厚度的层压的介电薄膜。随后，层压的介电薄膜也可从临时的载体基板上去除。在一特定的实施方式中，B阶固化的介电薄膜材料例如B阶固化的环氧树脂材料被层压到临时的载体基板。B阶固化的材料一般是在其中已发生了树脂和固化剂之间的有限反应的材料，从而使得该材料处于一种带有部分形成的网状物的固体状态（半固化）。在该状态下，B阶固化的材料仍可能是易熔的。B阶固化的材料可被另外暴露到高温和/或辐射下而最终固化，在此网状物可变成是充分形成的（例如交联的）、刚性的和非感光的。最终的固化也可能伴随着中度流量（moderate f1ow）。
这样一个B阶固化的介电薄膜材料可以保持粘附性能（粘性），在介电薄膜上的多个晶片单元移位的时候此种粘附性能帮助保持该多个晶片单元的位置，并且在最终固化的时候只经历中度流量，以将多个晶片单元固定到正确位置。因此，由B阶固化的材料制成的层压介电薄膜在固化后整个面板可显示出令人满意的平面度。此外，由于在其上放置了多个晶片单元的介电薄膜表面的平面度，在毗邻晶片单元边缘的介电薄膜中不存在中断。因此，晶片单元的有效表面和其上放置了晶片单元的介电薄膜表面都在相同的平面上，这对于设备的可靠性指标（比如在湿度敏感性测试期间的或者在安装到主板或其他产品上时的脱层）是有益的。
层压也可被利用以密封在介电薄膜上的多个晶片单元。例如，真空封装可被利用带有与介电薄膜相似或相同成分的B阶固化的环氧树脂。因此，物理特性（比如热膨胀系数（CTE）、硬度和弹性模量或在层压密封材料层和介电薄膜中的填料的重量百分比）可以是近似匹配或完全相同的，从而改进了最终封装件的完整性。此外，具有用于介电薄膜和密封材料的相似或相同成分的封装件分割可与层之间减少的脱落或脱层相关联。
图1A-1N和图2A-2L示出用于形成扇出WLCSP的方法，其中根据本发明的实施方式，永久性的介电薄膜在形成可供选择的积层结构期间被图案化。图1A-1N示出一实施方式，其中积层结构的重分布层（RDL）走线被形成在介电薄膜以上。图2A-2L示出一实施方式，其中积层结构的RDL走线被形成在介电薄膜以内。可对所示特殊的积层结构做出的各种修改和变化，包括但不限于具有多个介电层和设备互连走线的积层结构，其可以或者不可以与RDL走线相关联。这样的多层积层结构可利用在单晶片封装应用以及多设备模块中。因此，图1A-1N和图2A-2L示出的具体的实施方式被认为是阐述性的而非限制性的。
参照图1A，在一实施方式中，过程以将介电薄膜102附着到临时载体基板104上开始。在一实施方式中，介电薄膜102被层压到临时载体基板104。这样一个被层压的介电薄膜102可被均匀地应用到整个临时载体基板104上而且在稍后的阶段也可以很容易地从临时载体基板104释放。例如，层压可通过在高温和压力条件下滚动来执行。也可考虑将介电薄膜102附着到临时载体基板104上的其它方法，例如旋涂、印刷和喷涂。
在一实施方式中，介电薄膜102由一种材料例如环氧树脂、聚酰亚胺或硅树脂形成，其中该材料的机械性能通过固化被基本上完全地形成。介电薄膜102可由印制电路板（PCB）聚酯胶片材料形成。例如，介电薄膜102可由被部分固化的、B阶固化的环氧树脂形成，而且可包括额外的填料。在一实施方式中，有可能在明显低于所得完全固化的介电薄膜102的玻璃态转变温度（Tg）的温度对介电薄膜102进行层压。例如，包括了具有大约140-190℃的产物薄膜Tg的B阶固化的环氧树脂的介电薄膜102，其可在大约100-130℃被真空层压。介电薄膜102可以是不透明的，或者可选择地至少部分半透明的。临时载体基板104可由多种材料，例如但不限于钢铁、玻璃和蓝宝石形成，这些材料有足够刚性，在随后的模压操作期间不会移动，而且模压操作之后可从介电薄膜102被释放。在一实施方式中，介电薄膜有5到50微米厚，而临时载体基板104有大约2mm厚。
参照图1B，多个晶片单元可被放置在介电薄膜102的表面上，例如通过利用拾放晶片粘接机，而且介电薄膜102可被固化用以将多个晶片单元固定到固化的、刚性的介电薄膜102上的正确位置，通过固化技术可使得介电薄膜102为非感光的。固化可在放置期间或之后被执行，而且可通过各种方法例如热、紫外线（UV）或微波的固化循环来执行直到介电薄膜102是刚性的而且实质上被交联为止。在一实施方式中，介电薄膜102包括B阶环氧树脂材料，而且在足够使材料充分交联的温度下被最终固化，所述温度一般在最终固化的介电薄膜102的产物Tg以上。例如，包括具有大约140-160℃的最终固化Tg的B阶环氧树脂的介电薄膜可在大约170℃被固化。在一实施方式中，介电薄膜102具有大于或等于190℃的最终固化Tg。在一实施方式中，介电薄膜102包括按重量计算大于50%的颗粒状陶瓷填料（例如二氧化硅）。在一实施方式中，介电薄膜102包括按重量计算60-90%的陶瓷填料。在一实施方式中，介电薄膜102可具有在室温下11-18ppm/℃的CTE，例如在室温下大约12ppm/℃的CTE。在一实施方式中，固化实现了在介电薄膜102和多个晶片单元106之间足够的粘附，以便满足第一级封装可靠性指标，例如在湿度敏感性检测期间的或者在安装到主板或其他产品上时的脱层。
在固化介电薄膜102之后，介电薄膜102上的多个晶片单元106以图1C所示的密封材料层108密封，从而使得多个晶片单元被密封材料层108以及介电薄膜102密封。在密封期间，临时载体基板104防止固化的介电薄膜102弯曲或移动，而且固化的介电薄膜102将多个个别晶片单元保持在正确位置，从而改进了在板内或者网状晶圆内的对齐。如图1C所示，在一实施方式中，多个晶片单元106的有效表面与介电薄膜102上的密封材料层108的表面实质上是齐平的。
在一实施方式中，密封通过超模压工艺（例如压缩成型）使用模塑料来执行。模塑料可以是包括环氧树脂和填料的粉末。例如，压缩成型可在大约170℃被执行，以便完全融化包括在密封材料层108内的、具有大约140-160℃的最终Tg的粉末环氧树脂。在一实施方式中，模塑料包括按重量计算大于50%的颗粒状陶瓷填料（例如二氧化硅）。在一实施方式中，模塑料包括按重量计算60-90%的陶瓷填料。在一实施方式中，最终固化的模塑料可具有室温下11-18ppm/℃的CTE，例如室温下大约12ppm/℃的CTE。还可预期的是，根据本发明的实施方式的超模压可使用其他方法例如液体环氧树脂成型、传递模塑成型、丝网印刷、注塑法来完成。
在一实施方式中，密封通过真空层压被执行，其中最终固化可在层压期间或者之后被执行。与介电薄膜102类似，密封材料层108可包括B阶固化的材料和额外的填料。在一实施方式中，介电薄膜102和密封材料层108可由相同的材料或者具有类似物理特性的材料制成。密封材料层108的层压可考虑使用印制电路板（PCB）预浸渍处理材料片（prepreg materialsheet），而且与注塑法材料相比可有相对低的成本。在高温以及真空条件下执行的层压可利用B阶固化材料的易熔（顺从性的）特性以密封多个晶片单元106。另外，因为密封材料层108元件是B阶固化的，所以在远低于密封材料层108的最终固化Tg的温度下进行密封是可能的，而且在密封材料层108被形成/成形在多个晶片单元106周围之后执行最终的固化是可能的。在一实施方式中，层压可包括将半固化的密封材料薄膜（例如包括B阶固化的环氧树脂的密封材料薄膜）放置在位于固化的介电薄膜102上的多个晶片单元106以上，并且在真空条件下将热量和压力应用到半固化的密封材料薄膜上以形成/成形密封材料层108。例如，针对具有大约为140-215℃的最终固化Tg的密封材料层108，层压可在大约130℃和30kg/cm2条件下执行。在一实施方式中，被层压的密封材料层108是由具有大于或等于190℃的最终固化Tg的材料制成的。在一实施方式中，层压薄膜包括按重量计算，大于50%的（例如60-90%的）颗粒状陶瓷材料（例如二氧化硅）。在一实施方式中，最终固化的层压后的密封材料层108可具有在室温下11-18ppm/℃的CTE，例如在室温下大约12ppm/℃的CTE。随后，最终固化可在层压之后在足够充分交联密封材料的温度下执行，该温度通常在最终固化的密封材料层108的产物Tg之上。
然后临时载体基板104可从介电薄膜102被释放，如图1D所示，离开附着在包括多个晶片单元106和密封材料108的通常被称为板或重组晶圆的介电薄膜102。释放可通过多种技术例如紫外线照射、剥落（peeling）、激光释放、蚀刻及研磨来完成。
参照图1E，第一级过孔110可随后利用无掩膜图案化技术例如激光烧蚀来形成在介电薄膜102内。在一实施方式中，第一级过孔110的形成暴露出了形成在晶片单元106上的焊盘（未示出）。例如，第一级过孔110可具有约25至50微米的直径。在一实施方式中，介电薄膜102是至少部分半透明的。根据本发明的实施方式，在图1D中的临时载体基板104被去除之后并且在图1E示出的第一级过孔110形成之前，光学检测操作被可选择地执行以便测量任何的或全部的晶片单元106的实际位置。如果实际位置与名义上的参考位置不匹配，那么可为个别晶片单元中任何一个调整第一级过孔110的x-y位置和/或方向，或者调整积层结构中的任何其它特征，如共同待决的第12/876,915号美国专利申请所述，在此以引用方式将其并入。
然后一屏障层和/或籽晶层112可被形成于整个表面上和第一级过孔110内部，如图1F所示。例如，层112可包括大约500到1500埃厚的Ti、Ti/W或者Ti/TiN双层障碍层，以及大约1500到4000埃厚的铜籽晶层。在一实施方式中，层112可通过喷涂形成。
参照图1G，光阻层114随后可通过合适的方法，如层压或旋转涂覆形成到层112上。光阻层114随后可被图案化以形成如图1H所示的RDL走线图形开口116。随后可电镀，以使用第一级过孔金属118和重分布层（RDL）走线120来填充开口110、116，其分别可与晶片单元106的有效表面电气通信。在一实施方式中，第一级过孔金属118和RDL走线120是铜。例如，电镀层可以是大于或等于2微米厚。图案化的光阻层114和下层的部分屏障/籽晶层112随后被去除，如图1H所示。屏障/籽晶层112的去除也可稍微减少电镀层的厚度。
参照图1J，第二聚合物层122被形成于图案化的介电薄膜102和RDL走线120上。在一实施方式中，第二聚合物层122由感光材料例如聚酰亚胺、苯环丁烯（BCB）、聚苯并恶唑（PBO）等等制成。如图1K所示，第二聚合物层122然后可被图案化以形成开口124以暴露RDL走线120。开口126也可被形成以暴露出部分介电薄膜102以帮助分割。开口124、126的图案化可利用合适的光刻技术来执行。层122不限于高分子材料而且可由其它具有合适的绝缘和密封性能的材料制成。
如图1L所示，焊球128接着可被应用到暴露出的部分RDL走线120上。参照图1M，个别封装件随后可被分割。如图1M所示，分割可包括在第二聚合物层122的外侧边缘未延伸到的位置处仅切割介电薄膜102和密封材料108，对于个别封装件所述第二聚合物层122的外侧边缘与介电薄膜102和密封材料108的外侧边缘不是齐平的。在分割期间，这样的结构可与层之间减少的脱落和/或脱层相关联。在密封材料108和晶片粘接薄膜102均由环氧树脂材料制成而且第二聚合物层122由聚酰亚胺制成的实施方式中，在分割期间，切割仅要求是透过由类似的组成、特点组成的层，并因此减少了脱落和/或脱层。
应了解，在应用焊球128之前，可形成额外的层（例如球栅阵列捕获垫）。例如，如图1N所示，图1G-1H的过程可在附着焊球128之前被重复以形成屏障/籽晶层132和球栅阵列捕获垫134。
参照图2A-2L，在第二实施方式中，可形成供选择的WLCSP积层结构。如图2A-2D所示，介电薄膜202可被层压到临时载体基板上。多个晶片单元206被附着到介电薄膜202上。介电薄膜202然后被固化以将多个晶片单元206固定到正确位。多个晶片单元206随后以密封材料208超模压或者层压。然后临时载体基板204被去除。
参照图2E，第一级过孔210和RDL走线图案211可利用无掩膜图案化技术，例如激光烧蚀形成于介电薄膜202内。在一实施方式中，介电薄膜202至少是部分半透明的。根据本发明的实施方式，光学检测操作可有选择地被执行以在图2D中的临时载体基板204去除之后和图1E示出的第一级过孔210和RDL走线图案211形成之前测量任何的或者全部的晶片单元206的实际位置。如果实际位置与名义上的参考位置不匹配，那么可为个别晶片单元中的任何一个调整第一级过孔210的x-y位置和/或方向，或者调整积层结构中的任何其它特征，如共同待决的第12/876,915号美国专利申请所述，在此以引用方式将其并入。
接着屏障和/或籽晶层212可通过电镀金属层214例如铜来形成，其然后可被蚀刻以隔离如图2F-2G所示的在介电薄膜202内的第一级过孔218和RDL走线220。第二聚合物层222然后可利用合适的平版印刷技术形成和图案化，以便形成如图2H-2I所示的开口224、226。如图2J-2K所示，焊球228可被应用到开口224内覆盖暴露的RDL走线220部分，而开口226可帮助个别封装件的分割。在图2L所示的实施方式中，屏障或籽晶层232和球栅阵列捕获垫234可以按照与图1N所述类似的方式形成。
在上述说明书中，本发明的各种实施方式已被描述。然而，明显的是在不偏离如附加权利要求中所阐述的本发明的更广泛的精神和范围的情况下，可对本发明做出各种修改和改变。例如，对于CSP积层结构，各种结构性的替代品和工艺已被描述。可考虑，在介电薄膜内的第一级过孔形成之后，将多种的积层结构和工艺可利用无掩膜图案化技术（例如激光烧蚀技术）来应用。因此，说明书和附图被视为是阐述性意义而不是限制性意义。

Claims (20)

1.一种方法，其包括：
将多个晶片单元放置在介电薄膜的表面上；
在将所述多个晶片单元放置到所述介电薄膜的表面上之后固化所述介电薄膜；
用密封材料密封固化的介电薄膜上的所述多个晶片单元；以及
利用无掩膜图案化技术来图案化所述固化的介电薄膜以暴露所述多个晶片单元中的每一个。
2.如权利要求1所述的方法，其中将所述多个晶片单元放置在所述介电薄膜的表面上包括将所述多个晶片单元放置在半固化的介电薄膜的表面上。
3.如权利要求2所述的方法，其中所述半固化的介电薄膜包括B阶固化的环氧树脂。
4.如权利要求1所述的方法，其中所述无掩膜图案化技术包括激光烧蚀。
5.如权利要求2所述的方法，其中密封所述固化的介电薄膜上的所述多个晶片单元包括压缩成型。
6.如权利要求2所述的方法，其中密封所述固化的介电薄膜上的所述多个晶片单元包括层压。
7.如权利要求6所述的方法，其中层压包括真空层压。
8.如权利要求7所述的方法，其中真空层压包括：
在位于所述固化的介电薄膜上的所述多个晶片单元上放置半固化的密封薄膜；以及
在真空条件下将热量和压力应用到所述半固化的密封薄膜。
9.如权利要求1所述的方法，其中所述多个晶片单元被放置在所述介电薄膜的、与被层压到载体基板的第二表面相反的表面上。
10.如权利要求9所述的方法，还包括在密封位于所述固化的介电薄膜上的所述多个晶片单元之后并且在图案化所述固化的介电薄膜之前，从所述固化的介电薄膜释放所述载体基板。
11.如权利要求1所述的方法，还包括：
将感光聚合物层应用到图案化的所述固化的介电薄膜上；以及
使用光刻图案化技术在所述感光聚合物层中形成多个开口。
12.如权利要求11所述的方法，还包括：
切割透过所述固化的介电薄膜和所述密封材料而不切割透过所述感光聚合物层。
13.如权利要求1所述的方法，还包括：
在所述图案化的固化的介电薄膜上形成籽晶层；
在所述籽晶层上形成图案化的光阻层；以及
在所述图案化的光阻层的开口和所述图案化的固化的介电薄膜的开口内进行电镀，以便在所述图案化的固化的介电薄膜内形成第一级过孔以及在所述图案化的固化的介电薄膜上形成重分布层（RDL）走线。
14.如权利要求13所述的方法，还包括：
在电镀后去除所述图案化的光阻层以及所述图案化的光阻层以下的所述籽晶层的一部分；以及
在所述图案化的固化的晶片附加薄膜和RDL走线上形成感光聚合物层。
15.如权利要求14所述的方法，还包括：
图案化所述感光聚合物层以暴露所述RDL走线。
16.如权利要求15所述的方法，还包括：
分割所述多个晶片单元。
17.一种封装件，包括：
非感光介电薄膜；
附加到所述介电薄膜上的晶片单元的有效表面；
重分布层，其在所述介电薄膜上形成而且与所述晶片单元的有效表面电气通信；
密封材料层，其包括环氧树脂，所述密封材料层密封所述介电薄膜上的所述晶片单元；
其中，所述介电薄膜和所述密封材料层均包括按重量计算大于大约50%的陶瓷填料。
18.如权利要求17所述的封装件，还包括：
位于所述介电薄膜上的聚合物层；
在所述聚合物层内形成的开口；以及
其中，所述密封材料层的外侧边缘和所述介电薄膜的外侧边缘实质上是齐平的。
19.如权利要求18所述的封装件，其中在所述聚合物层内形成的开口暴露出重分布层（RDL）。
20.如权利要求19所述的封装件，其中所述介电薄膜和密封材料层均具有大于或等于190℃的玻璃态转化温度。
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