CN102714179A - 多栅iii-v量子阱结构 - Google Patents

多栅iii-v量子阱结构 Download PDF

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CN102714179A
CN102714179A CN2010800600689A CN201080060068A CN102714179A CN 102714179 A CN102714179 A CN 102714179A CN 2010800600689 A CN2010800600689 A CN 2010800600689A CN 201080060068 A CN201080060068 A CN 201080060068A CN 102714179 A CN102714179 A CN 102714179A
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CN102714179B (zh
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R.皮拉里塞蒂
J.卡瓦列罗斯
N.穆克赫吉
M.拉多萨夫耶维奇
R.S.乔
U.沙
G.德维
T.拉克施特
M.V.梅茨
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Intel Corp
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Abstract

形成微电子结构的方法被描述。那些方法的实施例包括在衬底上形成III-V三栅鳍、围绕III-V三栅鳍形成包层材料和围绕包层材料形成hik栅电介质。

Description

多栅III-V量子阱结构
背景技术
多种电子和光电子装置在例如元素硅（Si）衬底的半导电衬底上使用薄膜宽松晶格常数III-V半导体。能够使用III-V材料的属性的表面层可接受（host）多种高性能电子装置，例如互补金属氧化物半导体（CMOS）和量子阱（quantum well）（QW）晶体管。
附图说明
虽然说明书以特别指出并清楚地对某些实施例要求权利的权利要求来结束，但是当连同附图阅读时，各种实施例的优点能更容易地从实施例的以下描述来确定，其中：
图1a-1g代表形成根据一实施例的结构的方法。
图2a-2c代表形成根据一实施例的结构的方法。
图3a-3c代表形成根据一实施例的结构的方法。
图4a-4d代表形成根据一实施例的结构的方法。
图5a-5d代表形成根据一实施例的结构的方法。
图6a-6g代表形成根据一实施例的结构的方法。
图7代表根据一实施例的系统。
具体实施方式
在以下详细描述中，对通过图示示出可实践的具体实施例的附图进行参考。这些实施例被足够详细地描述以使本领域的技术人员能够实践实施例。将理解，各种实施例，虽然不同，但不一定互相排斥。例如，本文连同一个实施例描述的特定的特征、结构或特性，可在不偏离它们精神和范畴的情况下，在其它实施例之内被实行。此外，将理解每个公开的实施例之内的各个元件的位置或排布可在不偏离它们的精神和范围的情况下被修改。以下详细描述因此不是在限制的意义中做出，并且实施例的范畴只由适当解释的随附权利要求以及对权利要求授权的等同的完全范围来定义。在图中，在若干视图各处的相似数字指示相同或类似的功能性。
形成和利用例如量子阱结构的微电子结构的方法和相关联的结构被描述。那些方法和结构可包括在衬底上形成III-V三栅鳍（tri-gate fin）、围绕III-V三栅鳍形成包层（cladding）层和围绕包层层形成hi k栅电介质。本文包括的各种实施例能够实现围绕III-V鳍的包层层的生长，从而能够实现具有高k电介质的III-V三栅装置。
图1a-1g示出形成微电子结构的实施例，例如形成量子阱结构，例如。图1示出衬底100。在一个实施例中，衬底100可包括绝缘体上硅衬底（SOI）100，而且也可包括任何类型的合适的衬底材料。鳍102可被形成在衬底100上。鳍可包括III-V材料，例如但不限于InGaAs、InAs和InSb（图1b）。鳍102可包括三栅晶体管的部分并且可包括三栅鳍102。
包层材料104（其可包括如InP、AlInAs、AlInSb的此类材料）例如可围绕鳍102而形成（图1c）。在一些实施例中，包层材料104可包括任何合适的III-V材料。包层材料104可通过使用外延的技术来形成，例如分子束外延（MBE）或分子轨道气相外延（MOVPE）或其它共形（conformal）技术，例如原子层沉积（ALD）、化学气相沉积（CVP）、溅射等等。在一实施例中，包层材料104可沿着具体晶面（crystalline plane）形成，其可导致包层材料104的三角形状。三角的包层材料104可包括侧面部分107和尖109。在一实施例中，包层材料104可经受电介质形成工艺105（图1d），其中电介质材料106（例如但不限于氧化物）可在包层材料104上被形成/生长，例如通过例如氧化、化学气相沉积工艺105。电介质材料106可在三角形的包层材料104的侧面107上形成，使得电介质材料106的顶表面111可与三角包层材料104的尖109共面。
在一实施例中，抗蚀剂材料108可在包层材料104的尖109上/上方、以及在鳍102上方被形成（图1e）。在一实施例中，去除工艺113（例如电介质蚀刻工艺和/或化学机械处理）例如可被执行，其中没被抗蚀剂材料108覆盖的包层材料的部分和电介质材料106可被去除（图1f）。在去除工艺113之后，包层材料104的矩形部分包围着鳍102。抗蚀剂材料108然后可被去除，其中包层材料104的矩形部分被暴露（图1g）。
因此，三角包层材料104可经受一系列电介质形成和去除工艺以形成对量子阱三栅（非平面）晶体管结构的鳍102更有用的结构，例如。在一实施例中，由于三栅架构，包层材料104物理厚度（和整个Toxe）相比平面装置中的该厚度能是宽松的，而由于三栅装置的三维性质而保持相同的静电完整性。在一些实施例中，hi k电介质可随后被生长在包层材料上。
在另一实施例中，三栅鳍202可被布置在衬底200上（例如，类似于图1b的鳍100和衬底100）（图2a）。在一实施例中，三栅鳍202可包括三栅装置的三栅沟道（其中三栅鳍202包括顶栅203和两个侧面栅205、209）。包层材料204可被形成在鳍/沟道202的顶表面上和侧面上（图2b）。在一实施例中，包层材料204可根据与本文先前公开的图（1a-1g）中描绘的工艺类似的工艺而被形成。在一些实施例中，包层材料204可包括任何合适的III-V包层材料。在一实施例中，包层材料包括围绕三栅鳍202的共形包层材料层。高k电介质207（包括大于约4.0的介电常数）可在包层材料204上被形成，以形成三栅结构215，并且可包括布置在三栅鳍202上的高k栅电介质207（图2c）。在一实施例中，三栅结构215可进一步包括栅材料和源/漏区，例如类似于图3c的三栅结构315。
在一实施例中，三栅结构215可包括III-V三栅量子阱装置的部分，其合适于关态（off-state）泄漏和栅长度的最终可缩放性（scalability），而同时保留该III-V量子阱装置的高迁移率和高速度。在包层材料204上形成的高k电介质207可保留三栅沟道的高迁移率并且可能够实现三栅量子阱装置的高速度。III-V三栅量子阱架构能够实现缩放（Ioff控制和间距（pitch）/密度缩放）并且进一步能够实现高性能（高迁移率）装置。三栅结构215可通过组合对于Rext的再生长（在窄鳍中重要）、调制光环（halo）（进一步控制Ioff的反向标记掺杂物（opposite sign dopant））和多个鳍沟道而进一步被优化。
在另一实施例中，三栅鳍302可被布置在衬底300（例如类似于图2a的衬底200和鳍202）上（图3a）。三栅鳍302可包括三个侧面。在一实施例中，三栅鳍302可包括三栅装置的沟道。高k电介质307可被直接形成在三栅鳍302的三个侧面上，以形成三栅结构315，并且可包括布置在三栅沟道302上的高k栅电介质307（图3b）。在一实施例中，三栅结构315可包括III-V三栅量子阱装置的部分。图3c描绘一实施例，其中栅材料309被形成在围绕三栅鳍302的三个侧面的三个栅电介质层307上，并且源/漏区310邻近栅材料309被布置。在一实施例中，直接形成在沟道302上的高k电介质307可改善有效氧化物厚度（EOT）缩放。EOT可被减小，并且改善的短沟道效应导致进一步减小装置的栅长度并且增加封装在芯片上的晶体管的密度以及微处理器复杂性和功能性的能力。在一些情况中，高k电介质307可通原子级沉积（ALD）工艺来形成。
在另一实施例中，三栅鳍402可被布置在衬底400（例如类似于图2a的衬底200和鳍202）上（图4a）。在一实施例中，三栅鳍402可包括三栅量子阱装置的三栅沟道，并且可包括顶表面403。顶壁垒（barrier）材料408可在三栅鳍402的顶表面403上被形成（图4b）。顶壁垒材料408可包括AlInAs、AlInSb、AlGaAs和InP。顶壁垒材料408的部分410可被增量（delta）掺杂，其中单层掺杂物原子（例如n沟道装置的情况中的Si、S或Te和p沟道装置的情况中的Be或C）被结合到壁垒材料408中。这些掺杂物物理地与量子阱分离（远离），但由于此结构中的能带弯曲（band bending）而提供自由载流子到量子阱沟道402（图4c）。
高k电介质407可被形成在顶壁垒材料408上和在鳍402的侧面上（图4d），以形成三栅结构415，其可包括III-V三栅量子阱装置的部分。三栅结构415的增量掺杂改善了装置的迁移率，并且由于如通过增量掺杂层410所能够实现的穿过层408的能带弯曲而能够实现到量子阱402更好的接触阻抗。在沟道402上面的具有增量掺杂的量子阱三栅结构415可包括量子阱平面生长和ALD高Ｋ形成，不需要III-V三栅量子阱沟道402的侧面上技术上困难的外延的生长。在一实施例中，三栅结构415可进一步包括栅材料和源/漏区，例如类似于图3c的三栅结构315。
在另一实施例中，三栅鳍502可被布置在衬底500（例如类似于图2a的衬底200和鳍202）上（图5a）。在一实施例中，三栅鳍502可包括三栅装置的沟道。包层材料504可被形成在鳍/沟道502的侧面上和顶表面上（图5b）。在一实施例中，包层材料504可根据与本文先前公开的图（1a-1g）中描绘的工艺类似的工艺被形成。包层材料504可包括例如类似于图1c的包层材料104的材料。在一实施例中，包层材料504包括围绕三栅鳍502的共形包层材料层。
包层材料504的部分510可被增量掺杂，其中单层掺杂物原子（例如n沟道装置的情况中的Si、S或Te和p沟道装置的情况中的Be或C）被结合在包层材料504中。这些掺杂物物理地与量子阱分离（远离），但由于此结构中的能带弯曲，它们向量子阱装置提供自由载流子（图5c）。
在一些情况中，部分510可包括具有增量掺杂的顶壁垒/界面（interfacial）层510。高k电介质507可被形成在增量掺杂的包层材料504上以形成三栅结构515，并且可包括布置在三栅鳍/沟道502上的高k栅电介质507（图5d）。三栅结构515可包括具有包围三栅沟道502的增量掺杂510的量子阱三栅装置515的部分。在一些情况中，三栅装置515可包括ALD高K和顶壁垒510的共形再生长。三栅结构515可增加迁移率和性能并减小对三栅装置的性能和最大速度的Rc。在一实施例中，三栅结构515可进一步包括栅材料和源/漏区，例如类似于图3c的三栅结构315。
图6a描绘第一衬底600。第一衬底可包括可支持纳米线（nanowire）结构的任何类型的衬底。在一实施例中，第二衬底600可包括InP材料，但可包括其它材料，例如但不限于AlInAs、AlInSb、AlGaAs。第一纳米线层610可被形成/放置在第一衬底600上（图6b）。第一纳米线层610可包括栅/全部在三栅沟道周围。在一实施例中，例如，第一纳米线层可包括III-V材料，例如但不限于InGaAs、InSb、InAs、GaAs。在一实施例中，第一衬底600可与第一纳米线610晶格匹配，但可在化学上不同于第一纳米线层610。
第二衬底600’可被形成/放置在第一纳米线层610上（图6c）。在一实施例中，第二衬底600可包括InP材料，但可包括其它材料AlInAs、AlInSb、AlGaAs。第二纳米线层610’可被形成/放置在第二衬底层600’上（图6d）。在一实施例中，第二衬底600’可与第二纳米线610’晶格匹配，但可在化学上不同于第二纳米线层610。在一实施例中，例如，第二纳米线层可包括III-V材料，例如但不限于InGaAs、InSb、InAs、GaAs。堆叠的衬底/沟道600、610、600’、610’可包括侧面部分611。在一些实施例中，根据特定设计需求，多于两组堆叠的衬底/沟道可被堆叠在彼此之上以形成堆叠的结构612，其包括任何数量的沟道。
源/漏区640可被形成在堆叠的沟道/衬底600、610、600’、610’的侧面部分611上（图6e）。衬底600、600’可通过选择性蚀刻工艺620从堆叠的衬底沟道600、610、600’、610’被去除（图6f），以形成堆叠的沟道三栅结构615。在一实施例中，堆叠的沟道三栅结构可包括量子阱装置的部分。在一实施例中，间隙616将第一纳米线沟道610和第二纳米线沟道610’分离，并且源/漏区640被布置在第一纳米线沟道610和第二纳米线沟道610’的侧面部分618、617上。可选取可底切并生成堆叠的三栅结构615的化学反应（chemistry）。沟道鳍610、610’可被锚定到源/漏区640，而衬底600、600’可从挂起的（suspended）结构的侧面被选择性地蚀刻掉。
沟道结构610、610’拥有改善的可缩放性，并且在垂直结构中堆叠若干沟道增加了每单元设计脚印（footprint）的电流。因为III-V高迁移率/更低的Rext，堆叠的三栅结构615相比现有技术三栅结构（例如基于硅的结构）中的情况增加对更多沟道的访问。在另一实施例中，第一包层层620和第二包层层620’可分别在第一和第二沟道610、610’上被形成，并且第一高k电介质栅材料621和第二高k电介质材料621’可分别在堆叠的三栅结构615的第一和第二包层层620、620’上被形成（图6g）。包层层和高k电介质层可围绕沟道610、610’被形成（在图6g中被描绘为布置在沟道610、610’的顶和底表面上）。
图7示出根据一实施例的计算机系统。在一些实施例中，系统700包括处理器710、存储器装置720、存储器控制器730、图形控制器740、输入和输出（I/O）控制器750、显示器752、键盘754、指点装置756，和外设装置758，其所有可通过总线760在通信上耦合到彼此。处理器710可以是通用处理器或专用集成电路（ASIC）。I/O控制器750可包括用于有线或无线通信的通信模块。存储器装置720可以是动态随机存取存储器（DRAM）装置、静态随机存取存储器（SRAM）装置、闪速存储器（flash memory）装置，或这些存储器装置的组合。因此，在一些实施例中，系统700中的存储器装置720不必包括DRAM装置。
在系统700中示出的组件中的一个或更多可包括本文包括的各种实施例的一个或更多三栅装置。例如，处理器710、或存储器装置720、或I/O控制器750的至少部分，或这些组件的组合可包括在包括本文结构的至少一个实施例的集成电路封装中。
这些元件执行它们的在本领域中公知的常规功能。特别是，存储器装置720可用在一些情况中来为用于形成依照一些实施例的结构的方法的可运行指令提供长期存储，并且在其它实施例中可用于在由处理器710运行期间在更短期的基础上存储用于形成依照实施例的结构的方法的可运行指令。此外，例如，指令可被存储或以其它方式关联于与系统在通信上耦合的机器可访问媒体，例如紧致盘只读存储器（CD-ROM）、数字多功能盘（DVD）、和软盘、载波、和/或其它传播的信号。在一个实施例中，存储器装置720可向处理器710供应用于运行的可运行指令。
系统700可包括计算机（例如，台式计算机、膝上型计算机、手持计算机、服务器、Web设施、路由器等等）、无线通信装置（例如，蜂窝电话、无绳电话、寻呼机、个人数字助理等等）、计算机有关外设（例如，打印机、扫描仪、监视器等等）、娱乐装置（例如，电视机、收音机、立体声系统、磁带和紧致盘播放器、盒式录像录像机（video cassette recorder）、摄录像机（camcorder）、数字摄像机、MP3（运动图片专家组，音频层3）播放器、视频游戏、手表等等）和诸如此类。
本文包括的实施例的益处包括能够实现量子阱III-V三栅技术。实施例能够实现高迁移率、EOT缩放、Rext减小、对Ioff控制和间距/密度缩放的改善缩放性以及能够实现高性能、高迁移率装置。
虽然前面的描述已经指明可用在实施例中的某些步骤和材料，但本领域的技术人员将领会到可进行许多修改和替换。从而,意在所有此类修改、改变、替换和添加被视为落入如随附权利要求所定义的实施例的范畴和精神之内。此外，领会到各种微电子结构（例如晶体管装置）在本领域是公知的。因此，本文提供的图仅示出关于实施例的实践的示范性微电子结构的部分。因此实施例不限于本文描述的结构。

Claims (34)

1. 一种方法，包括：
   在衬底上形成III-V材料鳍；
   在所述III-V材料鳍上形成三角包层材料；
   在所述三角包层材料上形成氧化物；和
   围绕所述III-V材料鳍形成矩形包层材料。
2. 权利要求1所述的方法，进一步包括其中所述矩形包层材料包括布置在所述III-V材料鳍的顶表面和侧面上的III-V包层材料。
3. 权利要求1所述的方法，其中形成所述矩形包层材料包括：
   在所述III-V材料鳍上方的所述氧化物上形成抗蚀剂材料；
   蚀刻所述包层材料；和
   去除所述抗蚀剂。
4. 权利要求1所述的方法，进一步包括其中所述III-V材料鳍包括量子阱装置的III-V三栅沟道。
5. 权利要求4所述的方法，进一步包括在所述矩形包层材料上形成高k电介质，其中所述高k电介质包括hi k栅电介质。
6. 权利要求4所述的方法，进一步包括在包围所述III-V三栅沟道的包层材料上形成增量掺杂的壁垒。
7. 一种方法，包括：
   在衬底上形成III-V三栅鳍；和
   在所述III-V三栅鳍上直接形成hi k电介质。
8. 权利要求1所述的方法，其中形成所述III-V三栅鳍进一步包括在所述III-V三栅鳍的顶表面上形成具有增量掺杂的顶壁垒。
9. 一种方法，包括：
   在衬底上形成III-V三栅鳍；
   围绕所述III-V三栅鳍形成包层层；和
   围绕所述包层层形成hi k栅电介质。
10. 一种方法，包括：
   在第一衬底上形成第一纳米线沟道；
   在所述第一纳米线沟道上形成第二衬底；
   在所述第二衬底上形成第二纳米线沟道，以形成堆叠的结构；
   在所述堆叠的结构的侧面部分上形成源/漏区；和
   去除所述第一和第二衬底以形成堆叠的沟道三栅结构。
11. 权利要求10所述的方法，进一步包括：
   在所述第一和第二纳米线沟道上形成包层层；和
在所述包层层上形成高k电介质。
12. 权利要求10所述的方法，进一步包括：
在所述第一和第二纳米线沟道上形成包层层；和
在所述包层层上形成高k电介质。
13. 权利要求10所述的方法，其中去除所述第一和第二衬底包括从所述堆叠的结构选择性地蚀刻所述第一和第二衬底。
14. 权利要求10所述的方法，进一步包括其中所述第一衬底和所述第一沟道是晶格匹配的，并且其中所述第二衬底和所述第二纳米线是晶格匹配的。
15. 权利要求10所述的方法，进一步包括其中所述第一和第二纳米线沟道包括III-V三栅沟道，并且其中所述第一和第二衬底包括InP。
16. 权利要求10所述的方法，进一步包括其中所述堆叠的沟道三栅结构包括量子阱装置的部分。
17. 一种结构，包括：
   III-V三栅鳍，被布置在衬底上；和
   包层层，被布置在所述III-V三栅鳍的顶表面上和侧面部分上。
18. 权利要求17所述的结构，其中所述III-V三栅鳍包括InGaAs、InAs、InSb、和GaAs中的至少一个。
19. 权利要求17所述的结构，进一步包括围绕所述包层层而布置的hi k栅电介质层，其中所述结构包括量子阱装置。
20. 一种结构，包括：
   III-V三栅鳍，被布置在SOI衬底上；
   包层层，围绕所述III-V三栅鳍并在所述III-V三栅鳍上被布置；
   壁垒界面层，在围绕所述III-V三栅鳍的所述包层层上被布置；和
   hi k栅电介质，被布置在所述壁垒界面层上。
21. 权利要求20所述的结构，其中所述III-V三栅鳍包括三栅沟道。
22. 权利要求20所述的结构，其中所述壁垒界面层包括增量掺杂。
23. 权利要求20所述的结构，其中所述III-V三栅鳍包括InGaAs，并且其中所述结构包括量子阱结构。
24. 一种结构，包括：
   III-V三栅鳍，被布置在SOI衬底上；和
   hi k电介质，被直接布置在所述III-V三栅鳍上。
25. 权利要求24所述的结构，进一步包括一种系统，其中所述系统包括：
   总线，在通信上耦合到所述结构；和
   DRAM，在通信上耦合到所述总线。
26. 权利要求24所述的结构，其中所述结构包括量子阱装置的部分。
27. 一种结构，包括：
   III-V三栅鳍，被布置在衬底上；
   顶壁垒，被布置在所述III-V三栅鳍的顶表面上；和
   hi k栅电介质，被直接布置在所述顶壁垒上和直接布置在所述III-V三栅鳍的侧面上。
28. 权利要求27所述的结构，其中所述结构包括量子阱装置的部分。
29. 权利要求27所述的结构，其中所述顶壁垒包括增量掺杂。
30. 一种结构，包括：
第一纳米线沟道，被布置在第二纳米线沟道的上方；
间隙，分离所述第一纳米线沟道和所述第二纳米线沟道；和
源/漏区，被布置在所述第一纳米线沟道和所述第二纳米线沟道的侧面部分上。
31. 权利要求30所述的结构，进一步包括布置在所述第一纳米线沟道上的第一包层和布置在所述第二纳米线沟道上的第二包层。
32. 权利要求31所述的结构，进一步包括布置在所述第一包层上的第一高k电介质和布置在所述第二包层上的第二高k电介质。
33. 权利要求30所述的结构，进一步包括其中所述第一和第二纳米线沟道包括III-V三栅沟道。
34. 权利要求30所述的结构，进一步包括其中所述结构包括量子阱装置。
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