CN102469698A - 制造半导体插件板的方法 - Google Patents

制造半导体插件板的方法 Download PDF

Info

Publication number
CN102469698A
CN102469698A CN2011100240783A CN201110024078A CN102469698A CN 102469698 A CN102469698 A CN 102469698A CN 2011100240783 A CN2011100240783 A CN 2011100240783A CN 201110024078 A CN201110024078 A CN 201110024078A CN 102469698 A CN102469698 A CN 102469698A
Authority
CN
China
Prior art keywords
substrate
solder layer
semiconductor chip
coupling part
nature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011100240783A
Other languages
English (en)
Inventor
李宽镐
朱龙辉
金泰贤
崔硕文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Publication of CN102469698A publication Critical patent/CN102469698A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3494—Heating methods for reflowing of solder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/828—Bonding techniques
    • H01L2224/82801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83238—Applying energy for connecting using electric resistance welding, i.e. ohmic heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09681—Mesh conductors, e.g. as a ground plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1115—Resistance heating, e.g. by current through the PCB conductors or through a metallic mask
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1121—Cooling, e.g. specific areas of a PCB being cooled during reflow soldering

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)

Abstract

本文公开了一种制造半导体插件板的方法，该方法包括：提供基板，该基板包括形成在其一侧上的连接部分，该连接部分上提供有焊料层；在所述焊料层上布置配备有电流布线的传导性热生成器；将电流施加到所述电流布线上，从而对所述焊料层进行加热，以将半导体芯片附着到所述连接部分上；以及从所述传导性热生成器移除电流布线。该方法的优点在于通过将电流施加到传导性热生成器的电流布线以仅局部加热焊料层来将半导体芯片附着到基板上，从而降低了热应力并避免了基板的变形。

Description

制造半导体插件板的方法
相关申请的交叉引用
本申请要求2010年11月11日提交的、标题为“Method of Manufacturingthe package board”的韩国专利申请No.10-2010-0112281的权益，该申请的全部内容通过引用并入到本申请中。
技术领域
本发明涉及一种用于制造半导体插件板(package board)的方法。
背景技术
近来，在电子工业中，为了使电子装置小而薄，需求使用半导体插件板来安装电子部件的技术，在该半导体插件板上，电子部件可以是高密度、高限定和高集成的。由于电子部件变得高密度、高限定和高集成，所以对半导体插件板的稳定性存在要求，尤其是半导体芯片和板之间的接点的可靠性是非常重要的。
下文中，将参考图1-图5描述制造半导体插件板的传统方法。
首先，如图1所示，双面覆铜层压板11包括绝缘层12，在绝缘层12的两侧上提供有铜箔13。然后，如图2所示，形成导通孔14和镀铜层15，然后通过图形化在双面覆铜层压板11的两侧上形成电路层16。
然后，如图3所示，形成具有用于暴露连接焊盘(pad)的开口的阻焊膜17，并在所暴露的连接焊盘的两侧上形成表面处理层18(诸如，镍/金镀层)。
然后，如图4所示，在连接焊盘的上侧上形成锡球19。最后，如图5所示，将半导体芯片20放置在锡球19上，并然后将半导体芯片20放入回流焊炉30中并加热，从而将半导体芯片20的连接端子附着到基板10的连接焊盘上。
在回流工艺中，将半导体芯片20和基板10都放入回流焊炉30中，并然后将它们加热到锡球19的熔点或更高20～30分钟。在这种情况下，由于基板10已经被完全加热，所以由于基板10、锡球19以及半导体芯片20之间的热膨胀系数不同而出现了热应力。另外，当基板10被加热并然后被再次冷却时，基板10的上下部分因基板10的膨胀和收缩而变得不对称，从而基板10变形，导致半导体芯片20偏离初始附着位置、或者锡球19的厚度变得不均匀，从而恶化了附着可靠性。
发明内容
因此，设计本发明以解决上述问题，并且本发明意欲通过在焊料层上布置配备有电流布线的传导性热生成器、将电流施加给电流布线以仅局部加热焊料层、并然后将半导体芯片安装在基板的连接部分上，来降低热应力并改善半导体芯片和基板之间的附着可靠性。
本发明的一个方面提供了一种制造半导体插件板的方法，该方法包括：提供基板，该基板包括形成在其一侧上的连接部分，该连接部分上提供有焊料层；在所述焊料层上布置配备有电流布线的传导性热生成器；将电流施加到所述电流布线上，从而对所述焊料层进行加热，以将半导体芯片附着到所述连接部分上；以及从所述传导性热生成器移除所述电流布线。
这里，所述方法还可以包括：在将所述半导体芯片附着到所述连接部分上之前，布置用于覆盖所述传导性热生成器的辅助焊料层。
另外，该方法还可以包括：在将半导体芯片附着到连接部分期间，冷却基板的另一侧。
另外，可在保持室温的同时对基板的另一侧进行冷却。
另外，在该方法中，在提供基板的过程中，基板可以包括位于连接部分周围的多个引线，并且在将半导体芯片附着到连接部分上的过程中，半导体芯片可以包括形成于其上的多个焊接区(bonding pad)。该方法还可以包括：使用金属线将多个焊接区与多个引线相连接，以使得在将半导体芯片附着到连接部分上之后，它们彼此对应。
另外，在该方法中，在提供基板的过程中，基板可以包括多个连接部分；在布置传导性热生成器的过程中，由电流布线连接的多个传导性热生成器可以被布置在焊料层上，以使得它们与多个连接部分相对应；以及在将半导体芯片附着到连接部分上的过程中，多个半导体芯片可以被附着到多个连接部分上。
另外，连接部分可以提供有与焊料层电连接的一个或多个连接焊盘，并且半导体芯片可以提供有与焊料层电连接的一个或多个连接端子。
另外，传导性热生成器可以是碳片(carbon sheet)。
另外，传导性热生成器可以具有与焊料层的尺寸相对应的尺寸。
另外，传导性热生成器可以具有网状结构。
本说明书和权利要求中使用的术语和词语不应该被解释为限制于通常的意思或字典的定义，而应该基于发明者能够合适地定义其概念来描述他或她所知道的用于执行本发明的最好的方法的规则，被解释为具有与本发明的技术范围相关的意思和概念。
附图说明
通过下面结合附图的详细描述，本发明的上述以及其它目的、特征和优点将变得更容易理解，其中：
图1-图5为顺序地示出了制造半导体插件板的传统方法的截面图；
图6-图12是顺序地示出了根据本发明的制造半导体插件板的方法的截面图和平面图；
图13是示出了半导体插件板的截面图，半导体芯片通过电线附着到该半导体插件板上；以及
图14和图15是顺序地示出了将多个半导体芯片附着到基板上的过程的截面图。
具体实施方式
根据以下对优选实施方式的详细描述并参考附图，可以更清楚地理解本发明的目的、特征和优点。在整个附图中，相同的参考标记用于指代相同或类似的部件，且省略了对其的多余描述。进一步地，在下面的描述中，术语“第一”、“第二”、“一侧”、“另一侧”等用于将某一部件与其他部件相区分，但是此类部件的配置不应被解释为受这些术语的限制。而且，在本发明的描述中，当确定相关技术的详细描述可能会使本发明的要点模糊时，将省略对其的描述。
下文中，将参照附图对本发明的优选实施方式进行详细描述。
图6-图12是顺序地示出了根据本发明的制造半导体插件板的过程的截面图和平面图。
首先，如图6所示，提供包括连接部分110的基板100，所述连接部分110上布置有焊料层120。具体地，提供基板100的过程包括：提供基板100，该基板100包括形成在其一侧的连接部分110以及形成在基板100中的电路层130；在基板100上形成阻焊层140；在阻焊层140中形成开口，以暴露连接部分110的连接焊盘115；以及形成焊料层120。
基板100是电路板，并且优选可以是印刷电路板(PCB)，在该电路板中，包括连接部分110的一个或多个电路层形成在绝缘层上。印刷电路板(PCB)用于通过使用形成在绝缘板(诸如，酚醛树脂板或环氧树脂板)中的内部电路层来将所安装的部件进行电互连，以向这些部件提供电能并机械地固定这些部件，PCB包括单面PCB和双面PCB，在单面PCB中，电路层130形成在绝缘层的一侧上，而在双面PCB中，电路层130形成在绝缘层的两侧上。图6示出了包括一个绝缘层和两个电路层130的多层印刷电路板。然而，本发明并不局限于此，也可以采用包括两个或更多个电路层的多层印刷电路板。
通过后续过程，在连接部分110上提供焊料层120，并且通过焊料层120，在基板100上安装半导体芯片200或者外部部件。
在这种情况中，连接部分110可以包括一个或多个连接焊盘115。连接焊盘115用于通过焊料层120将安装在基板100上的半导体芯片与形成在基板100中的电路层130相连接。连接焊盘115由导电金属制成，诸如铜、金、银、镍等。连接焊盘115通常由铜制成。
阻焊层140用于保护最外面的电路，并且提供有用于暴露连接部分110的连接焊盘115的开口。阻焊层140可以由绝缘材料制成，诸如油墨或密封剂等，但是本发明并不局限于此。
表面处理层150可以额外地形成在连接部分110的通过阻焊层140的开口所暴露的连接焊盘115上。表面处理层150可以通过电镀金、浸镀金、浸镀银、化学镀镍浸镀金(electroless nickel immersion gold plating，ENIG)、直接浸镀(DIP)、或热风整平(hot air solder levelling，HASL)等来形成。
焊料层120用于将诸如半导体芯片200之类的外部部件附着到基板100的连接部分110上，并且通过使用诸如涂刷器等之类的丝网印刷工具在所暴露的连接部分110上印刷焊膏而形成。焊料层可以由锡/铅(Sn/Pb)、锡/银/铜(Sn/Ag/Cu)、锡/银(Sn/Ag)、锡/铜(Sn/Cu)、锡/铋(Sn/Bi)、锡/锌/铋(Sn/Zn/Bi)、或锡/银/铋(Sn/Ag/Bi)等制成。
如图7中所示，配备有电流布线310的传导性热生成器300布置在焊料层120上。传导性热生成器300在其两端提供有电流布线310，并通过向电流布线310施加电流来对焊料层120加热。该传导性热生成器300可以由诸如银、铜、或镍铬合金等导体制成。当焊料层120被加热到它的熔点或高于熔点时，半导体芯片200通过焊料层120被附着到基板100的连接部分110上，同时传导性热生成器300被浸入焊料层120中。
这里，如图8中所示，用于覆盖传导性热生成器300的辅助焊料层160可以布置在传导性热生成器300上。当辅助焊料层160布置在传导性热生成器300上时，传导性热生成器300被浸入焊料层120中，从而焊料层120可以被快速地加热到它的熔点或熔点之上。辅助焊料层160通过使用涂刷器等来形成。
在这种情况中，传导性热生成器300可以是碳片。该碳片由碳纳米材料(诸如，碳纳米管(CNT)或石墨烯等)和膨胀石墨的混合物制成。由于碳片具有良好的导电性和导热性，它能够在一短的时间周期有效地对焊料层120进行加热，从而减少处理时间。
另外，由于碳片具有良好的强度和弹性，焊料层120的机械特性能够通过将碳片浸入焊料层120中而得到改善。另外，由于碳片具有低的热膨胀系数，当该碳片被浸入焊料层120中时，焊料层120的热膨胀系数能够被减小，从而降低了基板100、焊料层120和半导体芯片200之间的热膨胀系数的差异。
优选地，传导性热生成器300的尺寸与焊料层120的尺寸相对应。当传导性热生成器的尺寸小于焊料层的尺寸时，存在着问题，因为要消耗大量的功率来将焊料层120加热到它的熔点或者熔点之上，从而加热时间变长了。相反地，当传导性热生成器的尺寸大于焊料层的尺寸时，存在着问题，因为很难仅局部加热焊料层120。
另外，如图9中所示，传导性热生成器300可以具有网状结构。当传导性热生成器300具有网状结构时，热被均匀地传递给焊料层120，从而焊料层120能够被有效地加热。另外，在这种情况中，由于传导性热生成器300被均匀地浸入到焊料层120的每一单位区域中，焊料层120的机械特性能够得到有效地改善。
如图10中所示，焊料层120通过将电流施加到传导性热生成器300的电流布线310而被加热，从而将半导体芯片200附着到基板100的连接部分110上。当电流在传导性热生成器300中流动时，会生成热，从而通过使用该热将焊料层120加热到它的熔点或更高。在这种情况中，优点在于，可以通过控制施加到电流布线310的电流的量来精确控制加热温度。也就是说，通过将电流施加到传导性热生成器300的电流布线310，仅焊料层120被局部加热，从而避免基板100变形，并降低了因热膨胀系数差异导致的热应力。
附着到基板100的半导体芯片200可以包括一个或多个连接端子，并且基板100的连接部分110提供有一个或多个连接焊盘115。由于半导体芯片200通过焊料层120被附着到基板100上，半导体芯片200能够与形成在基板100中的电路层电连接。
在该情况中，如图11中所示，当半导体芯片200通过加热焊料层120而被附着到基板100上时，可以执行对基板100的另一侧进行冷却的过程。当使用冷却器400对基板100的另一侧进行冷却时，从传导性热生成器300发出的热不会被施加给除焊料层120之外的基板100，从而完全避免了因热而导致的基板100的变形。
可在保持室温时，对基板100的另一侧进行冷却，因为在室温下，基板100仅稍微受其他部件的温度的影响。
然后，如图12中所示，将电流布线310从传导性热生成器300移除。
在根据本发明的制造半导体插件板的方法中，半导体芯片200的附着并不局限于上述方式，还可以通过使用电线220来完成。在使用电线220将半导体200附着到基板100上的情况中，如图13中所示，基板还包括位于连接部分110周围的多个引线170。这多个引线电连接到基板100的电路层130。
配备有电流布线的传导性热生成器300布置在焊料层120上，然后通过将电流施加到电流布线310来对焊料层120进行加热，从而将半导体芯片200附着到基板100的连接部分110上。
在使用电线220将半导体200附着到基板100上的情况中，在半导体芯片200上提供多个焊接区210，然后将这多个焊接区210与基板100的多个引线170通过电线220相连接，以便它们彼此对应。电线220通常由金(Au)或铝(Al)制成。在这种情况中，半导体芯片200并非仅通过使用连接引线170的电线220来电连接到形成在基板100中的电路层130，而是可以通过仅使用形成在连接部分110中的连接焊盘115来电连接到形成在基板100中的电路层130。
然后，将电流布线310从传导性热生成器300移除。移除电流布线310的过程可以在引线170被通过电线220附着到基板100之前执行。
另外，如图14和图15中所示，多个半导体芯片200可以同时附着到基板100上。如图14中所示，基板100提供有多个连接部分110，并且通过电流布线310连接的多个传导性热生成器300布置在焊料层120上，以便它们与多个连接部分110相对应。
多个半导体芯片200通过将电流施加到电流布线310的两端而被附着到基板100的连接部分，并且如图15中所示，电流布线310被从多个半导体芯片200移除。如同常规回流工艺，多个半导体芯片200能够同时被附着到基板100的连接部分110上。
根据本发明的制造半导体插件板的方法，配备有电流布线的传导性热生成器布置在形成于基板的连接部分上的焊料层上，然后电流被施加给电流布线以对焊料层进行加热，从而将半导体芯片附着到连接部分上。因此，由于仅基板的焊料层被加热，所以降低了热应力并避免了基板的变形，从而改善了半导体芯片和基板之间的附着可靠性。
另外，基板的另一侧被冷却，以便不将热传递到半导体芯片和除了连接部分之外的基板，从而改善了半导体芯片和基板之间的附着可靠性。
另外，基板的连接部分提供有一个或多个连接焊盘，并且附着到基板的半导体芯片包括一个或多个连接端子。由于半导体芯片通过焊料层被附着到基板上，半导体芯片能够与形成在基板中的电路层电连接。
另外，由于传导性热生成器由碳片制成并且该碳片具有良好的导热性，所以焊料层能够在短的时间周期内被加热到熔点或更高，并且在将半导体芯片附着到基板时，通过将碳片浸入到焊料层中，能够改善焊料层的机械特性。
虽然出于说明的目的公开了本发明的优选实施方式，但是本领域技术人员可以理解，在不背离所附权利要求中公开的本发明的范围和精神的情况下，可以作出各种修改、添加和替换。本发明的简单修改、添加和替换属于本发明的范围，本发明的特定范围将由所附权利要求清楚地限定。

Claims (10)

1.一种用于制造半导体插件板的方法，该方法包括：
提供基板，该基板包括形成在该基板一侧上的连接部分，该连接部分上提供有焊料层；
在所述焊料层上布置配备有电流布线的传导性热生成器；
将电流施加到所述电流布线上，从而对所述焊料层进行加热，以将半导体芯片附着到所述连接部分上；以及
从所述传导性热生成器移除所述电流布线。
2.根据权利要求1所述的方法，该方法还包括：
在将所述半导体芯片附着到所述连接部分上之前，布置用于覆盖所述传导性热生成器的辅助焊料层。
3.根据权利要求1所述的方法，该方法还包括：
在将所述半导体芯片附着到所述连接部分上的过程中，冷却所述基板的另一侧。
4.根据权利要求3所述的方法，其中，所述基板的另一侧在保持室温的同时被冷却。
5.根据权利要求1所述的方法，其中，在所述提供基板的过程中，所述基板包括位于所述连接部分周围的多个引线；
其中，在将所述半导体芯片附着到所述连接部分上的过程中，所述半导体芯片包括形成于该半导体芯片上的多个焊接区；以及
其中，所述方法还包括：使用金属线将所述多个焊接区与所述多个引线相连接，以使得在将所述半导体芯片附着到所述连接部分上之后，所述多个焊接区与所述多个引线彼此对应。
6.根据权利要求1所述的方法，其中，在所述提供基板的过程中，所述基板包括多个连接部分；
其中，在所述布置所述传导性热生成器的过程中，由电流布线连接的多个传导性热生成器被布置在所述焊料层上，以使得所述多个传导性热生成器与所述多个连接部分相对应；以及
其中，在将所述半导体芯片附着到所述连接部分上的过程中，所述多个半导体芯片被附着到所述多个连接部分上。
7.根据权利要求1所述的方法，其中，所述连接部分提供有与所述焊料层电连接的一个或多个连接焊盘，并且所述半导体芯片提供有与所述焊料层电连接的一个或多个连接端子。
8.根据权利要求1所述的方法，其中，所述传导性热生成器是碳片。
9.根据权利要求1所述的方法，其中，所述传导性热生成器具有与所述焊料层的尺寸相对应的尺寸。
10.根据权利要求1所述的方法，其中，所述传导性热生成器具有网状结构。
CN2011100240783A 2010-11-11 2011-01-14 制造半导体插件板的方法 Pending CN102469698A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020100112281A KR20120050834A (ko) 2010-11-11 2010-11-11 반도체 패키지 기판의 제조방법
KR10-2010-0112281 2010-11-11

Publications (1)

Publication Number Publication Date
CN102469698A true CN102469698A (zh) 2012-05-23

Family

ID=46048149

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011100240783A Pending CN102469698A (zh) 2010-11-11 2011-01-14 制造半导体插件板的方法

Country Status (4)

Country Link
US (1) US20120122278A1 (zh)
JP (1) JP2012104792A (zh)
KR (1) KR20120050834A (zh)
CN (1) CN102469698A (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102055361B1 (ko) 2013-06-05 2019-12-12 삼성전자주식회사 반도체 패키지
TWI613775B (zh) 2016-08-24 2018-02-01 國立清華大學 降低電流路徑熱應力之晶片
US11051407B2 (en) * 2018-10-23 2021-06-29 International Business Machines Corporation Facilitating filling a plated through-hole of a circuit board with solder

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040029314A1 (en) * 2001-08-08 2004-02-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
US20060027635A1 (en) * 2004-08-09 2006-02-09 Schaenzer Matthew J Thermally coupling an integrated heat spreader to a heat sink base
US20060292744A1 (en) * 1999-10-01 2006-12-28 Ziptronix Three dimensional device integration method and integrated device
US20070034676A1 (en) * 2005-08-11 2007-02-15 Honeywell International Inc. Electric field assisted solder bonding
US20090275175A1 (en) * 2003-09-30 2009-11-05 Sane Sandeep B Modified chip attach process
US20100237496A1 (en) * 2009-03-18 2010-09-23 Maxat Touzelbaev Thermal Interface Material with Support Structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213740A (ja) * 1996-01-29 1997-08-15 Citizen Watch Co Ltd 液晶表示装置における液晶駆動用半導体装置の実装方法
JP2000260827A (ja) * 1999-03-12 2000-09-22 Towa Corp 半導体チップ実装用加熱装置及び加熱方法
JP2003124624A (ja) * 2001-10-18 2003-04-25 Canon Inc ヒートコネクタ
JP5135185B2 (ja) * 2008-12-01 2013-01-30 アルプス電気株式会社 電子回路モジュール

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060292744A1 (en) * 1999-10-01 2006-12-28 Ziptronix Three dimensional device integration method and integrated device
US20040029314A1 (en) * 2001-08-08 2004-02-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
US20090275175A1 (en) * 2003-09-30 2009-11-05 Sane Sandeep B Modified chip attach process
US20060027635A1 (en) * 2004-08-09 2006-02-09 Schaenzer Matthew J Thermally coupling an integrated heat spreader to a heat sink base
US20070034676A1 (en) * 2005-08-11 2007-02-15 Honeywell International Inc. Electric field assisted solder bonding
US20100237496A1 (en) * 2009-03-18 2010-09-23 Maxat Touzelbaev Thermal Interface Material with Support Structure

Also Published As

Publication number Publication date
KR20120050834A (ko) 2012-05-21
US20120122278A1 (en) 2012-05-17
JP2012104792A (ja) 2012-05-31

Similar Documents

Publication Publication Date Title
JP4159861B2 (ja) プリント回路基板の放熱構造の製造方法
JP5142119B2 (ja) 放熱構造を備えたプリント基板の製造方法および該方法で製造されたプリント基板の放熱構造
US20070010086A1 (en) Circuit board with a through hole wire and manufacturing method thereof
JP5106519B2 (ja) 熱伝導基板及びその電子部品実装方法
JP4992532B2 (ja) 放熱基板及びその製造方法
JP2019530977A (ja) パワーモジュールおよびパワーモジュールを製造するための方法
JP2010199216A (ja) 部品実装構造及び部品実装方法
CN1980523A (zh) 金属芯子、封装板、及其制造方法
CN100378968C (zh) 电子装置
JP4882562B2 (ja) 熱伝導基板とその製造方法及び電源ユニット及び電子機器
JP2009200212A (ja) プリント基板の放熱構造
JP2000100987A (ja) 半導体チップモジュール用多層回路基板およびその製造方法
CN111132476A (zh) 双面线路散热基板的制备方法
JP2008192787A (ja) 熱伝導基板とこれを用いた回路モジュールとその製造方法
KR20070100386A (ko) 부품 실장용 핀을 갖는 프린트 배선판 및 이것을 사용한전자 기기
JP2006515712A (ja) 熱伝導性基板パッケージ
CN102469698A (zh) 制造半导体插件板的方法
WO2010050896A1 (en) Insulated metal substrate and method of forming the same
JP5003202B2 (ja) 熱伝導基板とその製造方法及び回路モジュール
US9614128B2 (en) Surface mountable semiconductor device
JP6251420B1 (ja) 電子モジュールおよび電子モジュールの製造方法
JP2019140321A (ja) 電子部品搭載用基板、及び、電子デバイス
KR101055297B1 (ko) 개선된 열방출 특성을 갖는 메탈 인쇄회로기판의 제조 방법
GB2135525A (en) Heat-dissipating chip carrier substrates
JP2008235321A (ja) 熱伝導基板とその製造方法及びこれを用いた回路モジュール

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120523