CN102468295A - 具有插入物的半导体模块以及用于生产具有插入物的半导体模块的方法 - Google Patents

具有插入物的半导体模块以及用于生产具有插入物的半导体模块的方法 Download PDF

Info

Publication number
CN102468295A
CN102468295A CN2011103337051A CN201110333705A CN102468295A CN 102468295 A CN102468295 A CN 102468295A CN 2011103337051 A CN2011103337051 A CN 2011103337051A CN 201110333705 A CN201110333705 A CN 201110333705A CN 102468295 A CN102468295 A CN 102468295A
Authority
CN
China
Prior art keywords
module housing
sealing ring
face
module
power semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011103337051A
Other languages
English (en)
Other versions
CN102468295B (zh
Inventor
R.施勒克
T.施托尔策
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN102468295A publication Critical patent/CN102468295A/zh
Application granted granted Critical
Publication of CN102468295B publication Critical patent/CN102468295B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H01L2224/48132—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8484—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/858—Bonding techniques
    • H01L2224/8584—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Casings For Electric Apparatus (AREA)
  • Inverter Devices (AREA)

Abstract

本发明涉及具有插入物的半导体模块以及用于生产具有插入物的半导体模块的方法。一种功率半导体模块包括在顶面上具有密封环的模块壳体。所述密封环通过与模块壳体和附着到功率半导体模块的印刷电路板协作，封闭地密封模块壳体的顶面处的用于馈通功率半导体模块的电端子的馈通位置。在模块壳体的底面上，密封环封闭地密封模块壳体的底面。

Description

具有插入物的半导体模块以及用于生产具有插入物的半导体模块的方法
技术领域
本发明涉及半导体模块，并且特别涉及具有插入物（insert）的半导体模块。
背景技术
电力电子模块是用在电力电子电路中的半导体模块。电力电子模块通常被采用在交通工具、轨道和工业应用中，例如用在逆变器或整流器中。它们同样可以应用于能量生成和传输的形式。包含在电力电子模块中的半导体组件可以涉及例如半导体芯片，其中包括绝缘栅（IGBT）、金属氧化物场效应晶体管（MOSFET）、结型场效应晶体管（JFET）、闸流管或者二极管。
许多半导体模块包括馈通（feed through）模块壳体顶面的多个电端子，以便实现与外部印刷电路板等等进行电连接。在模块的底面，衬底可以粘附到模块壳体。但是人们发现，如果模块操作在包含腐蚀性化合物（比如水蒸汽、盐雾、硫化氢（H2S）、硫酸（H2SO4））的腐蚀性环境中，则存在所述（多种）腐蚀性化合物进入模块内部的风险，这是因为所述馈通位置和/或粘附物无法充分抑制（多种）腐蚀性化合物的侵入。在模块内部，（多种）腐蚀性化合物可能会导致枝状晶体特别在操作于不同电势下的铜导线之间生长。最后，这样的枝状晶体可能会导致铜导线之间的电短路。因此需要一种改进的解决方案。
发明内容
根据半导体模块的一个实施例，所述半导体模块包括模块壳体、功率半导体芯片、衬底、多个电端子以及第一密封环。模块壳体具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面。衬底承载功率半导体芯片并且与模块壳体机械联结(join)。多个电端子从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透（penetrate）模块壳体的顶面。第一密封环被布置在模块壳体的顶面，从而使得在垂直于垂直方向的任何横向（lateral）方向上，所述多个电端子被布置在第一密封环的横向内边界内。
根据半导体模块系统的一个实施例，所述系统包括功率半导体模块和相抵保持器（counter holder）。功率半导体模块包括模块壳体、功率半导体芯片、衬底、多个电端子以及第一密封环。模块壳体具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面。衬底承载功率半导体芯片并且与模块壳体机械联结。多个电端子从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面。第一密封环被布置在模块壳体的顶面上，从而使得在垂直于垂直方向的任何横向方向上，所述多个电端子被布置在第一密封环的横向内边界内。相抵保持器包括其上布置第三密封环的底面，其被布置在模块壳体的顶面上并且其底面面向模块壳体的顶面，从而使得在垂直于垂直方向的任何横向方向上，所述多个电端子被布置在第三密封环的横向内边界内。
根据半导体模块装置（arrangement）的一个实施例，所述布置包括功率半导体模块和印刷电路板。功率半导体模块包括模块壳体、功率半导体芯片、衬底、多个电端子以及第一密封环。模块壳体具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面。衬底承载功率半导体芯片并且与模块壳体机械联结。多个电端子从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面。第一密封环被布置在模块壳体的顶面上，从而使得在垂直于垂直方向的任何横向方向上，所述多个电端子被布置在第一密封环的横向内边界内。印刷电路板具有多个相抵端子（counter terminal），其被布置在模块壳体的顶面上，从而使得每一个端子与其中一个相抵端子形成电接触。印刷电路板、第一密封环和模块壳体一起封闭地（hermetically）密封模块壳体顶面上的馈通位置。
根据半导体模块装置的另一个实施例，所述布置包括功率半导体模块、相抵保持器和印刷电路板。功率半导体模块包括模块壳体、功率半导体芯片、衬底、多个电端子以及第一密封环。模块壳体具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面。衬底承载功率半导体芯片并且与模块壳体机械联结。多个电端子从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面。第一密封环被布置在模块壳体的顶面上，从而使得在垂直于垂直方向的任何横向方向上，所述多个电端子被布置在第一密封环的横向内边界内。相抵保持器包括其上布置第三密封环的底面。印刷电路板具有多个相抵端子。相抵保持器和印刷电路板被布置在模块壳体的顶面上，从而使得印刷电路板被布置在相抵保持器与功率半导体模块之间，每一个端子与其中一个相抵端子形成电接触，并且相抵保持器、印刷电路板和第一密封环一起封闭地密封模块壳体顶面上的馈通位置。
根据半导体模块装置的又一个实施例，所述布置包括功率半导体模块、印刷电路板和散热器。功率半导体模块包括模块壳体、功率半导体芯片、衬底、多个电端子、第一密封环以及第二密封环。模块壳体具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面。模块壳体还包括安装框架（mounting frame）和布置在安装框架内的内壳体。承载功率半导体芯片的衬底与模块壳体机械联结。多个电端子从模块内壳体的内部延伸到模块内壳体的外部，并且在馈通位置处穿透模块内壳体的顶面。第一密封环被布置在模块壳体顶面上的安装框架上。第二密封环被布置在模块壳体底面上的安装框架上。印刷电路板包括多个相抵端子。印刷电路板被布置在模块壳体的顶面上，并且散热器被布置在模块壳体的底面上，从而使得每一个端子与其中一个相抵端子形成电接触，并且印刷电路板、第一密封环、安装框架、第二密封环和散热器一起封闭地密封模块内壳体。
根据半导体模块装置的又一个实施例，所述布置包括功率半导体模块、印刷电路板、相抵保持器和散热器。功率半导体模块包括模块壳体、功率半导体芯片、衬底、多个电端子、第一密封环以及第二密封环。模块壳体包括形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面。模块壳体还包括安装框架和布置在安装框架内的内壳体。承载功率半导体芯片的衬底与模块壳体机械联结。多个电端子从模块内壳体的内部延伸到模块内壳体的外部，并且在馈通位置处穿透模块内壳体的顶面。第一密封环被布置在模块壳体顶面上的安装框架上。第二密封环被布置在模块壳体的底面上的安装框架上。印刷电路板包括多个相抵端子。相抵保持器具有其上布置第三密封环的底面。相抵保持器和印刷电路板被布置在模块壳体的顶面上，并且散热器被布置在模块壳体的底面上，从而使得印刷电路板被布置在相抵保持器与功率半导体模块之间，每一个端子与其中一个相抵端子形成电接触，并且相抵保持器、第三密封环、印刷电路板、第一密封环、安装框架、第二密封环和散热器一起封闭地密封模块内壳体。
根据用于组装半导体模块装置的方法的一个实施例，所述方法包括提供功率半导体模块、印刷电路板和散热器。功率半导体模块包括模块壳体、功率半导体芯片、衬底、多个电端子以及第一密封环。模块壳体具有在垂直方向上彼此间隔开并且形成该模块壳体的相对面的顶面和底面。承载功率半导体芯片的衬底与模块壳体机械联结。多个电端子从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面。第一密封环被围绕电端子布置在模块壳体的顶面上。印刷电路板包括多个相抵端子。在组装这些组件时，功率半导体模块被布置在印刷电路板与散热器之间。从而模块壳体的顶面面对印刷电路板，并且模块壳体的底面则面对散热器。印刷电路板、功率半导体模块和散热器被按压在彼此之上，从而使得第一密封环被印刷电路板和模块壳体压紧（compress），并且第二密封环被散热器和模块壳体压紧。在按压步骤期间，每一个端子与其中一个相抵端子形成电接触。其结果是，印刷电路板、第一密封环和模块壳体一起封闭地密封模块壳体顶面上的馈通位置，并且模块壳体、第二密封环和散热器一起封闭地密封联结装置的底面。
根据用于组装半导体模块装置的方法的另一个实施例，所述方法包括提供功率半导体模块、印刷电路板、相抵保持器和散热器。功率半导体模块包括模块壳体、功率半导体芯片、衬底、多个电端子以及第一密封环。模块壳体具有在垂直方向上彼此间隔开并且形成该模块壳体的相对面的顶面和底面。承载功率半导体芯片的衬底与模块壳体机械联结。多个电端子从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面。第一密封环被围绕电端子布置在模块壳体的顶面上。印刷电路板包括多个相抵端子。在相抵保持器的底面上布置第三密封环。在组装这些组件时，印刷电路板被布置在相抵保持器与功率半导体模块之间，并且功率半导体模块被布置在印刷电路板与散热器之间。从而相抵保持器的底面面对印刷电路板和模块壳体，模块壳体的顶面面对印刷电路板，并且模块壳体的底面面对散热器。相抵保持器、印刷电路板、功率半导体模块和散热器被按压在彼此之上，从而使得第一密封环被印刷电路板和模块壳体压紧，第二密封环被散热器和模块壳体压紧，并且第三密封环被相抵保持器和模块壳体压紧。在按压步骤期间，每一个端子与其中一个相抵端子形成电接触。其结果是，相抵保持器、第三密封环、印刷电路板、第一密封环和模块壳体一起封闭地密封模块壳体的顶面上的馈通位置，并且模块壳体、第二密封环和散热器一起封闭地密封联结装置的底面。
在阅读下面的详细描述并查看附图之后，本领域技术人员将认识到附加的特征和优点。
附图说明
附图中的组件不一定是按比例绘制的，而是为了强调说明本发明的原理。此外，在附图中，相同的附图标记指代相应的部件。在附图中：
图1是穿过组装之前的具有功率半导体模块、散热器和外部印刷电路板的功率半导体装置的垂直剖面，其中功率半导体模块配备有第一密封环和第二密封环；
图2是穿过组装之前的具有功率半导体模块、散热器、外部印刷电路板和相抵保持器的功率半导体装置的垂直剖面，其中功率半导体模块配备有第一密封环和第二密封环，并且相抵保持器配备有第三密封环；
图3是穿过组装好的具有功率半导体模块、散热器、外部印刷电路板和相抵保持器的功率半导体装置的垂直剖面，其中功率半导体模块与外部印刷电路之间的电接触是借助于压合引脚（press-fit pin）实现的；
图4是穿过组装好的具有功率半导体模块、散热器、外部印刷电路板和相抵保持器的功率半导体装置的垂直剖面，其中功率半导体模块与外部印刷电路之间的电接触是借助于焊接引脚（solder pin）实现的；
图5是穿过类似于图3的装置的组装好的具有压合引脚的功率半导体装置的垂直剖面，其中用于外部连接功率半导体模块的端子被插入到焊接于衬底的插槽（socket）中；
图6示出了一种功率半导体模块装置，其中所述模块的特征在于被布置在环形安装框架内的内壳体，其中第一密封环和第二密封环被布置在安装框架上；
图7示出了一种功率半导体模块装置，其具有功率半导体模块、印刷电路板、散热器和相抵保持器；
图8是功率半导体模块的顶视图；
图9是功率半导体模块的底视图；
图10是图5的功率半导体模块的顶视图；
图11是图5的功率半导体模块的底视图；以及
图12是相抵保持器130的底视图。
具体实施方式
在下面的详细描述中将参照构成其一部分的附图，在附图中以说明性的方式示出了可以在其中实践本发明的具体实施例。在这方面，参照所描述的附图的取向使用了诸如“顶”、“底”、“前”、“后”、“首”、“尾”之类的方向性术语。由于可以按照许多不同的取向来定位各个实施例的组件，因此所述方向性术语被用于说明而绝非限制。应当理解的是，在不背离本发明的范围的情况下，可以利用其他实施例，并且可以做出结构或逻辑上的改变。因此，不应当按照限制的意义来理解下面的详细描述，并且本发明的范围由所附权利要求书限定。应当理解的是，除非明确另行表明，否则这里所公开的各个示例性实施例的特征可以相互组合。
现在参照图1，其中示出了功率半导体模块100的垂直剖面图，其包括带有侧壁61和可选的壳体覆盖62的模块壳体6。所述壳体可以是电绝缘的，并且例如由塑料制成。模块壳体6的顶面6t和模块壳体6的底面6b在垂直方向v上彼此间隔开。模块100包括布置在衬底2上的一个或多个功率半导体芯片8。衬底2表现出在其顶面上涂覆有顶面金属化层22并且在其底面上涂覆有底面金属化层21的电介质层20，衬底2充当用于功率半导体芯片8的载体和电路板。可选的是，顶面金属化层22可以包括导体路径和/或导体垫（pad）221、222、223、224、225、226。
金属化层21和22被牢固地接合到绝缘载体20，绝缘载体20例如可以是适当的陶瓷材料，比如氮化铝（AlN）、氧化铝（Al2O3）、氮化硅（Si3N4）、碳化硅（SiC）或氧化铍（BeO）。金属化层21和22由铜或铜合金制成。绝缘衬底2例如可以是直接铜接合（DCB）、或者直接铝焊接（DAB）、或者活性金属焊接（AMB）的衬底。可选的是，金属层21和/或22可以是未涂覆的，或者可以独立于彼此还涂覆有银、NiAu、NiPd、NiPdAu当中的一种或更多种，以便产生可焊接表面或者在半导体芯片与顶部金属化层22之间促进LTJT（低温联结技术）联结。
衬底2被布置在模块壳体6的底面6b，并且利用联结装置7（例如胶水或硅酮）与模块壳体6弹性地或非弹性地联结。联结装置7的底面7b（即联结装置7背对模块壳体6顶面6t的一面）未由衬底2完全覆盖。
功率半导体芯片8被安装在顶面金属化层22上并且通过接合层81与之连接，接合层81例如是焊料、导电粘合剂或银压烧结接合物。功率半导体芯片8例如可以是可控功率半导体开关，比如MOSFET、IGBT、闸流管、JFET或功率二极管。功率半导体芯片8可以是例如其特征为超出50A或75A的高标称电流和/或超出400V的高标称闭锁电压的半导体芯片8。此外，功率半导体芯片的覆盖区（footprint）的尺寸可以被确定成等于5.5mm乘5.5mm或7mm乘7mm。
功率半导体芯片8和/或顶面金属化层22可以通过接合线82互相电连接。取代接合线82，还可以提供金属夹，其例如通过焊接、通过导电粘合剂接合或者银压烧结接合而导电连接到芯片8的顶面和/或顶面金属化层22。
功率半导体芯片8的顶部是可选的内部印刷电路板（PCB）95以用于将内部驱动器端子接成电路。PCB 95可以带有电子组件以便控制功率半导体芯片8的可控芯片。带有控制电子装置的功率半导体模块也被称作是“智能的”（IPM）。
为了例如把功率半导体模块100外部连接到外部印刷电路板110，提供了电端子91、92、93、94。举例来说，外部印刷电路板110可以包括用于控制模块100的控制电路。为了清楚起见，在图1中抑制了控制电路。为了与电端子91、92、93、94电接触，印刷电路板110配备有相抵电端子191、192、193、194。
举例来说，电端子91、92、93、94可以被形成为端子弹簧，并且相应的相抵电端子191、192、193、194可以被形成为接触垫。或者，电端子91、92、93、94可以被形成为压合引脚或焊接引脚，并且相应的相抵电端子191、192、193、194被形成为接触孔洞。
为了提升介电强度，用可选的软灌注化合物（soft potting compound）51部分地灌注模块壳体6的内部，例如在垂直方向v上从绝缘衬底2至少延伸超出功率半导体芯片8或者至少超出接合线82的硅胶，并且例如可选地一直延伸到印刷电路板95。软灌注化合物51的顶部是可选的刚性灌注化合物52（例如环氧树脂），以便将电端子91、92、93、94电绝缘以获得附加的机械稳定性。应当注意的是，为了示出电端子91、92、93、94的内部蔓延，在图1到5中部分地去除了软灌注化合物51和硬灌注化合物52。
电端子91、92、93、94从模块壳体6的内部延伸到模块壳体6的外部，从而在馈通位置65处穿透模块壳体6的顶面6b。举例来说，馈通位置65可以是在可选的壳体覆盖62中形成的通孔。如果没有提供壳体覆盖62，则馈通位置65可以被形成为硬灌注化合物52中的通道。当在灌注过程期间将电端子91、92、93、94嵌入到硬灌注化合物52中就会出现这样的通道。
如果功率半导体模块100操作在例如包含至少一种腐蚀性化合物（比如水蒸汽、盐雾、硫化氢（H2S）或硫酸（H2SO4））的腐蚀性环境中，则在模块100的内部没有通过馈通位置65被封闭地密封的情况下，存在所述（多种）腐蚀性化合物进入所述内部的风险。如果馈通位置65和/或联结装置7是间断的，或者如果硬灌注化合物52、软灌注化合物51以及联结装置7的至少其中之一不足以防止腐蚀性化合物的扩散，就可能会发生这种情况。
为了避免或减轻腐蚀问题，功率半导体模块100可以配备有一个或多个密封环。举例来说，在图1所示的功率半导体模块100中，模块壳体6装配有第一密封环41和第二密封环42。第一密封环41被布置在模块壳体6的顶面6t上，从而使得在垂直于垂直方向v的任何横向方向r上，所述多个电端子91、92、93、94被布置在第一密封环41的横向内边界411内。相应地，第二密封环42被布置在模块壳体6的底面6b上，从而使得在垂直于垂直方向v的任何横向方向r上，密封装置7的底面7f被布置在第二密封环42的横向内边界421内。
如果外部印刷电路板110被按压在功率半导体模块100之上，则电端子91、92、93、94分别与相应的相抵电端子191、192、193和194发生接触，并且第一密封环41接触印刷电路板110，并且与印刷电路板110和模块壳体6一起密封馈通位置65以防腐蚀性化合物侵入。当然，要求印刷电路板110至少在其于任何横向方向r上被布置在第一密封环41的横向内边界411内的部分中是紧密的，以防腐蚀性化合物侵入。
相应地，如果散热器120被按压在功率半导体模块100之上，则第二密封环42与散热器120接触，并且与散热器120和模块壳体6一起密封联结装置7以防腐蚀性化合物侵入。当然，要求散热器120至少在其于任何横向方向r上被布置在第二密封环42的横向内边界421内的部分中是紧密的，以防腐蚀性化合物侵入。
如果印刷电路板110在其于任何横向方向r上被布置在第一密封环41的横向内边界411内的部分中对于腐蚀性化合物的侵入不是紧密的，则可以使用如图2中所示的相抵保持器130。在该实施例中，印刷电路板110由于通孔111而不是紧密的。在其面向功率半导体模块100的底面130b上布置第三密封环43。如果正如前面所解释的那样将印刷电路板110按压在功率半导体模块100之上并且如果将相抵保持器130按压在印刷电路板110之上，则第三密封环43与印刷电路板110的顶面110t接触，并且与第一密封环41、印刷电路板110、模块壳体6以及相抵保持器130一起密封馈通位置65以防腐蚀性化合物侵入。当然，要求相抵保持器130至少在其于任何横向方向r上被布置在第三密封环43的横向内边界431内的部分中是紧密的，以防腐蚀性化合物侵入。
在图1和2的装置中，电端子91、92、93、94被示例性地形成为端子弹簧，并且相应的相抵电端子191、192、193、194被形成为接触垫。图3示出了与图2的装置基本上完全相同但是处于组装好的状态下的装置，也就是说其中相抵保持器130和散热器120被按压在功率半导体模块100之上。另一个区别在于，电端子91、92、93、94被形成为压合引脚，其被按压到形成为接触孔洞的相应的相抵电端子191、192、193、194中。
图4示出了与图3的装置基本上完全相同的装置，其区别在于，电端子91、92、93、94被形成为焊接引脚，其被引入到形成为接触孔洞的相应的相抵电端子191、192、193、194中并且通过焊料99被焊接到各自相应的相抵电端子191、192、193、194。另一个区别在于相抵保持器130，其配备有上面布置了第三密封环43的环状突出。
图5示出了与图3的装置类似的装置，其中电端子91、92、93、94被形成为压合引脚，其被按压到形成为接触孔洞的相应的相抵电端子191、192、193、194中。端子91、92、93、94延伸穿过模块壳体6的顶面和可选的壳体覆盖62并且进入到壳体6的内部，其在该处分别被插入到插槽71、72、73和74中，并且通过连接层81（例如焊料或含银烧结层）电连接到衬底2的顶面金属化层22。
在图6中示意性地示出了功率半导体模块装置的另一个实施例。模块壳体6的特征在于内壳体60，其可以被设计成类似于如前面参照图1到5所解释的模块壳体6，并且除了第一密封环41和第二密封环42之外包括相同的组件。此外，模块壳体6还展现出环形安装框架63。内壳体60被布置在安装框架63内部，并且通过弹性耦合条带64弹性地耦合到安装框架63。
如果安装框架63被按压在散热器120之上，则内壳体60也被按压在散热器120之上。由于弹性耦合条带64，可以避免内壳体60以及特别是布置在其中的陶瓷衬底的过度应力。在图6的装置中示例性地示出了可以将第一密封环41和第二密封环42布置在安装框架63上而不是内壳体60上。在组装好的状态下，安装框架63与印刷电路板110、散热器120、第一密封环41以及第二密封环42一起封闭地密封内壳体60。
现在参照图7，其中示出了尚未组装的功率半导体模块装置的另一个实施例。这种装置基本上类似于图6的装置。但是印刷电路板110由于通孔111而不是紧密的，正如前面参照图3到5所描述的那样。因此提供了附加的相抵保持器130，在相抵保持器130面对功率半导体模块100的该面上布置有第三密封环43。相抵保持器130的有效性也和前面参照图3到5所描述的相同。在组装好的状态下，安装框架63和印刷电路板110、相抵保持器130、第三密封环43、散热器120、第一密封环41以及第二密封环42一起封闭地密封内壳体60。
图8是功率半导体模块100的顶视图，其中示出了第一密封环41是闭环。其中还示出了在任何横向方向上，电端子91、92、93、94被布置在第一密封环41的横向内边界411内。
图9是功率半导体模块100的底视图，其中示出了第二密封环42是闭环。其中还示出了在任何横向方向上，联结装置7的底面7b被布置在第二密封环42的横向内边界421内。
图10是图6中所示的功率半导体模块100的顶视图。该视图示出了第一密封环41是闭环，并且在任何横向方向上，模块内壳体60和电端子91、92、93、94被布置在第一密封环41的横向内边界411内。
相应地，图11是图6中所示的功率半导体模块100的底视图，其中示出了第二密封环42是闭环，并且在任何横向方向上，联结装置7的底面7b被布置在第二密封环42的横向内边界421内。
图12是相抵保持器130的底视图，其中示出了第三密封环43是闭环。
所述密封环，例如前面提到的第一、第二和第三密封环41、42、43可以由弹性材料制成，例如硅酮、橡胶、聚氨酯、粘合胶、聚四氟乙烯（PTFE）、纸或者其他适当的密封材料。
在所描述的装置中，功率半导体模块100、外部印刷电路板110、散热器120以及相抵保持器130（如果提供的话）被按压在彼此之上。为了保持该压力，可以通过适当的手段将所提到的组件彼此连接，例如通过螺栓连接或夹钳连接。在前面的例子中存在用于连接所提到的组件的这种连接手段，尽管没有详细地描述这样的连接手段。
根据另一个实施例，所描述的模块可以包括金属底板，其例如由铜、铝或金属基质材料制成，以作为功率半导体模块的基底，并且其充当用于所述模块的所有陶瓷衬底的载体。这样的底板也可以被称作衬底。
诸如“之下”、“以下”、“下方”、“之上”、“上方”等空间相对术语是出于描述起来容易的原因而使用的，以便解释一个元件相对于第二元件的定位。这些术语意图包含除了在附图中所描绘的取向之外的器件的不同取向。此外，诸如“第一”、“第二”之类的术语也是被用来描述各个元件、区段、部分等等，而不是意图进行限制。相同的附图标记在整个描述中指代相同的元件。
这里所使用的术语“具有”、“包含”、“包括”等等是开放性术语，其表明所声明的元件或特征的存在，而不排除附加的元件或特征。除非在上下文中明确另有所指，否则“一个”、“所述”意图包括复数以及单数。
除非另行提到或者除非不同的特征是互斥的，否则在前面的相同或不同实施例中所描述的不同特征可以按照任意置换彼此组合。
鉴于前面的变型和应用范围，应当理解的是，本发明既不限于前面的描述，也不限于附图。相反，本发明仅由所附权利要求书及其法律等效表述限制。

Claims (25)

1.一种半导体模块，其包括：
模块壳体，其具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面；
功率半导体芯片；
承载功率半导体芯片的衬底，所述衬底与模块壳体机械联结；
多个电端子，其从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面；以及
第一密封环，其被布置在模块壳体的顶面上，从而使得在垂直于垂直方向的任何横向方向上，所述多个电端子被布置在第一密封环的横向内边界内。
2.如权利要求1所述的半导体模块，其中，所述多个电端子被形成为端子弹簧或者压合引脚或焊接引脚。
3.如权利要求1所述的半导体模块，其中，第一密封环由以下材料的其中一种制成：硅酮、橡胶、聚氨酯、粘合胶、聚四氟乙烯（PTFE）以及纸。
4.如权利要求1所述的半导体模块，其中，所述多个电端子当中的每一个远离第一密封环间隔开。
5.如权利要求1所述的半导体模块，其还包括第二密封环，其中：
衬底通过接合缝粘附到模块壳体的底面；
所述接合缝包括背对模块壳体的顶面的底面；并且
第二密封环被布置在模块壳体的底面上，从而使得在垂直于垂直方向的任何横向方向上，接合缝的底面的横向外边界被布置在第二密封环的横向内边界内。
6.如权利要求1所述的半导体模块，其中，
模块壳体包括框架和布置在所述框架内部的内壳体。
7.如权利要求6所述的半导体模块，其中，
第一密封环被布置在所述框架上。
8.如权利要求6所述的半导体模块，其还包括布置在模块壳体的底面上的第二密封环，从而使得在垂直于垂直方向的任何横向方向上，接合缝的底面的横向外边界被布置在第二密封环的横向内边界内。
9.如权利要求1所述的半导体模块，其中，所述多个电端子被插入到焊接于衬底的插槽中。
10.一种半导体模块系统，其包括：
功率半导体模块，其包括：
模块壳体，其具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面；
功率半导体芯片；
承载功率半导体芯片的衬底，所述衬底与模块壳体机械联结；
多个电端子，其从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面；以及
围绕所述多个电端子被布置在模块壳体的顶面上的第一密封环；以及
在其底面上布置有第三密封环的相抵保持器；
其中，相抵保持器被布置在模块壳体的顶面上，其中相抵保持器的底面面向模块壳体的顶面，从而使得在垂直于垂直方向的任何横向方向上，所述多个电端子被布置在第三密封环的横向内边界内。
11.如权利要求10所述的半导体模块系统，其中，所述多个电端子被形成为端子弹簧或者压合引脚或焊接引脚。
12.一种半导体模块装置，其包括：
功率半导体模块，其包括：
模块壳体，具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面；
功率半导体芯片；
承载功率半导体芯片的衬底，所述衬底与模块壳体机械联结；
多个电端子，其从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面；以及
围绕所述多个电端子被布置在模块壳体的顶面上的第一密封环；以及
包括多个相抵端子的印刷电路板；
其中，印刷电路板被布置在模块壳体的顶面上，从而使得所述多个端子当中的每一个与其中一个相抵端子形成电接触，并且印刷电路板、第一密封环和模块壳体一起封闭地密封模块壳体顶面上的馈通位置。
13.如权利要求12所述的半导体模块装置，其还包括散热器，其中：
衬底通过接合缝粘附到模块壳体的底面；
所述接合缝包括背对模块壳体的顶面的底面；
第二密封环被布置在模块壳体的底面上，从而使得在垂直于垂直方向的任何横向方向上，接合缝的底面被布置在第二密封环的横向内边界内；
散热器被按压在第二密封环之上；并且
模块壳体、衬底、接合缝、印刷电路板、第一密封环、散热器和第二密封环一起封闭地密封模块壳体的底面上的接合缝。
14.如权利要求12所述的半导体模块，其中，所述多个电端子被形成为端子弹簧或者压合引脚或焊接引脚。
15.一种半导体模块装置，其包括：
功率半导体模块，其包括：
模块壳体，其具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面；
功率半导体芯片；
承载功率半导体芯片的衬底，所述衬底与模块壳体机械联结；
多个电端子，其从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面；以及
围绕所述多个电端子被布置在模块壳体的顶面上的第一密封环；
在其底面上布置有第三密封环的相抵保持器；以及
包括多个相抵端子的印刷电路板；
其中，相抵保持器和印刷电路板被布置在模块壳体的顶面上，从而使得印刷电路板被布置在相抵保持器与功率半导体模块之间，所述多个端子当中的每一个与其中一个相抵端子形成电接触，并且相抵保持器、印刷电路板和第一密封环一起封闭地密封模块壳体的顶面上的馈通位置。
16.如权利要求15所述的半导体模块装置，其还包括散热器，其中：
衬底通过接合缝粘附到模块壳体的底面，所述接合缝具有背对模块壳体的顶面的底面；
第二密封环被布置在模块壳体的底面上，从而使得在垂直于垂直方向的任何横向方向上，接合缝的底面被布置在第二密封环的横向内边界内；
散热器被按压在第二密封环之上；并且
模块壳体、衬底、接合缝、印刷电路板、第一密封环、散热器和第二密封环一起封闭地密封模块壳体的底面上的接合缝。
17.如权利要求16所述的半导体模块装置，其中，所述多个电端子被形成为端子弹簧或者压合引脚或焊接引脚。
18.一种半导体模块装置，其包括：
功率半导体模块，其包括：
模块壳体，其具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面，其中模块壳体包括安装框架和布置在安装框架内的内壳体；
功率半导体芯片；
承载功率半导体芯片的衬底，所述衬底与模块壳体机械联结；
多个电端子，其从模块内壳体的内部延伸到模块内壳体的外部，并且在馈通位置处穿透模块内壳体的顶面；以及
被布置在模块壳体的顶面上的安装框架上的第一密封环；
被布置在模块壳体的底面上的安装框架上的第二密封环；
包括多个相抵端子的印刷电路板；以及
散热器；
其中，印刷电路板被布置在模块壳体的顶面上，散热器被布置在模块壳体的底面上，从而使得所述多个端子当中的每一个与其中一个相抵端子形成电接触；并且印刷电路板、第一密封环、安装框架、第二密封环和散热器一起封闭地密封模块内壳体。
19.如权利要求18所述的半导体模块装置，其中，所述多个电端子被形成为端子弹簧或者压合引脚或焊接引脚。
20.一种半导体模块装置，其包括：
功率半导体模块，其包括：
模块壳体，其包括形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面，其中模块壳体包括安装框架和布置在安装框架内的内壳体；
功率半导体芯片；
承载功率半导体芯片的衬底，所述衬底与模块壳体机械联结；
多个电端子，其从模块内壳体的内部延伸到模块内壳体的外部，并且在馈通位置处穿透模块内壳体的顶面；以及
被布置在模块壳体的顶面上的安装框架上的第一密封环；
被布置在模块壳体的底面上的安装框架上的第二密封环；
在其底面上布置有第三密封环的相抵保持器；以及
包括多个相抵端子的印刷电路板；
散热器；
其中，相抵保持器和印刷电路板被布置在模块壳体的顶面上，并且散热器被布置在模块壳体的底面上，从而使得印刷电路板被布置在相抵保持器与功率半导体模块之间；所述多个端子当中的每一个与其中一个相抵端子形成电接触；并且相抵保持器、第三密封环、印刷电路板、第一密封环、安装框架、第二密封环和散热器一起封闭地密封模块内壳体。
21.如权利要求20所述的半导体模块装置，其中，所述多个电端子被形成为端子弹簧或者压合引脚或焊接引脚。
22.一种用于组装半导体模块装置的方法，其包括：
提供功率半导体模块，所述功率半导体模块包括：
模块壳体，其具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面；
功率半导体芯片；
承载功率半导体芯片的衬底，所述衬底与模块壳体机械联结；
多个电端子，其从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面；以及
围绕所述电端子被布置在模块壳体的顶面上的第一密封环；以及
提供包括多个相抵端子的印刷电路板；
提供散热器：
把功率半导体模块布置在印刷电路板与散热器之间，从而使得模块壳体的顶面面对印刷电路板，并且使得模块壳体的底面面对散热器；
把印刷电路板、功率半导体模块和散热器按压在彼此之上，从而使得第一密封环被印刷电路板和模块壳体压紧，并且第二密封环被散热器和模块壳体压紧，并且模块壳体、衬底、印刷电路板以及第一密封环一起封闭地密封模块壳体的顶面上的馈通位置；并且
其中，在按压期间，所述多个电端子当中的每一个与其中一个相抵端子形成电接触。
23.一种用于组装半导体模块装置的方法，其包括：
提供功率半导体模块，所述功率半导体模块包括：
模块壳体，其具有形成该模块壳体的相对面并且在垂直方向上彼此间隔开的顶面和底面；
功率半导体芯片；
承载功率半导体芯片的衬底，所述衬底与模块壳体机械联结；
多个电端子，其从模块壳体的内部延伸到模块壳体的外部，并且在馈通位置处穿透模块壳体的顶面；以及
围绕所述电端子被布置在模块壳体的顶面上的第一密封环；
提供包括多个相抵端子的印刷电路板；
提供在其底面上布置有第三密封环的相抵保持器；
提供散热器：
把印刷电路板布置在相抵保持器与功率半导体模块之间，并且把功率半导体模块布置在印刷电路板与散热器之间，从而使得相抵保持器的底面面对印刷电路板和模块壳体，模块壳体的顶面面对印刷电路板，并且模块壳体的底面面对散热器；
把相抵保持器、印刷电路板、功率半导体模块和散热器按压在彼此之上，从而使得第一密封环被印刷电路板和模块壳体压紧，第二密封环被散热器和模块壳体压紧，第三密封环被相抵保持器和模块壳体压紧，所述多个端子当中的每一个与其中一个相抵端子形成电接触，相抵保持器、第三密封环、印刷电路板、第一密封环和模块壳体一起封闭地密封模块壳体的顶面上的馈通位置，并且模块壳体、第二密封环和散热器一起封闭地密封联结装置的底面。
24.如权利要求23所述的方法，其中，
所述多个电端子被形成为压合引脚；
所述多个相抵电端子被形成为印刷电路板的接触孔洞；并且
在按压期间，每一个压合引脚被按压到其中一个接触孔洞中。
25.如权利要求23所述的方法，其中，
所述多个电端子被形成为端子弹簧；
所述多个相抵电端子被形成为印刷电路板的接触垫；并且
在按压期间，每一个端子弹簧被按压在其中一个接触垫之上。
CN201110333705.1A 2010-10-28 2011-10-28 具有插入物的半导体模块以及用于生产具有插入物的半导体模块的方法 Active CN102468295B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/914171 2010-10-28
US12/914,171 US8446726B2 (en) 2010-10-28 2010-10-28 Semiconductor module having an insert and method for producing a semiconductor module having an insert

Publications (2)

Publication Number Publication Date
CN102468295A true CN102468295A (zh) 2012-05-23
CN102468295B CN102468295B (zh) 2015-06-24

Family

ID=45935845

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110333705.1A Active CN102468295B (zh) 2010-10-28 2011-10-28 具有插入物的半导体模块以及用于生产具有插入物的半导体模块的方法

Country Status (3)

Country Link
US (1) US8446726B2 (zh)
CN (1) CN102468295B (zh)
DE (1) DE102011085282B4 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681552A (zh) * 2012-09-04 2014-03-26 赛米控电子股份有限公司 功率半导体模块和用于制造功率半导体模块的方法
CN103871978A (zh) * 2012-12-18 2014-06-18 株式会社东芝 半导体装置
CN104064526A (zh) * 2013-03-20 2014-09-24 赛米控电子股份有限公司 功率半导体模块和带有该功率半导体模块的系统
CN106501906A (zh) * 2016-10-26 2017-03-15 博为科技有限公司 一种10g pon bosa贴
CN106561076A (zh) * 2015-10-01 2017-04-12 现代自动车株式会社 具有导热界面材料的逆变器及应用其的混合动力车
CN111863763A (zh) * 2020-06-30 2020-10-30 扬州国扬电子有限公司 一种结构紧凑型ipm功率模块

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103023279B (zh) * 2011-09-27 2015-05-13 株式会社京浜 半导体控制装置
US9048721B2 (en) * 2011-09-27 2015-06-02 Keihin Corporation Semiconductor device
US8586420B2 (en) * 2011-09-29 2013-11-19 Infineon Technologies Ag Power semiconductor arrangement and method for producing a power semiconductor arrangement
KR101228841B1 (ko) * 2011-10-04 2013-02-04 엘에스산전 주식회사 일체형 탄성클립을 이용한 전력용반도체 고정장치
WO2013105351A1 (ja) * 2012-01-10 2013-07-18 株式会社日立製作所 パワーモジュール
TWM460509U (zh) * 2013-03-04 2013-08-21 Giant Technology Co Ltd 電子器物散熱裝置
US9148985B2 (en) * 2013-03-15 2015-09-29 Eaton Corporation Power pole inverter
US9480185B2 (en) * 2014-01-08 2016-10-25 Enphase Energy, Inc. Double insulated heat spreader
EP2903024B1 (en) * 2014-01-31 2022-08-03 Vincotech GmbH Contact element, power semiconductor module and method of fabricating same
SG10201401622RA (en) 2014-04-17 2015-11-27 Delta Electronics Int’L Singapore Pte Ltd Package structure
DE102014106570B4 (de) * 2014-05-09 2016-03-31 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit Schalteinrichtung und Anordnung hiermit
US10959342B2 (en) * 2019-04-08 2021-03-23 Kevin R. Williams Condensation resistant power semiconductor module
US9584038B2 (en) * 2014-06-02 2017-02-28 Enphase Energy, Inc. Ungrounded inverter enclosure and cabling
CN105742252B (zh) * 2014-12-09 2019-05-07 台达电子工业股份有限公司 一种功率模块及其制造方法
JP2017022346A (ja) * 2015-07-15 2017-01-26 富士電機株式会社 半導体装置及び半導体装置の製造方法
JP6809294B2 (ja) * 2017-03-02 2021-01-06 三菱電機株式会社 パワーモジュール
US10283447B1 (en) * 2017-10-26 2019-05-07 Infineon Technologies Ag Power semiconductor module with partially coated power terminals and method of manufacturing thereof
US11183460B2 (en) * 2018-09-17 2021-11-23 Texas Instruments Incorporated Embedded die packaging with integrated ceramic substrate
DE102019129675A1 (de) * 2018-12-11 2020-06-18 Infineon Technologies Ag Leistungshalbleitermodul und Verfahren zum Herstellen eines Leistungshalbleitermoduls
DE102019215523A1 (de) * 2019-10-10 2021-04-15 Vitesco Technologies GmbH Leistungshalbleiterbauteil sowie Verfahren zur Herstellung eines Leistungshalbleiterbauteils
US11049792B1 (en) * 2020-05-06 2021-06-29 Semiconductor Components Industries, Llc Package structure for semiconductor devices
EP4071793A1 (en) * 2021-04-07 2022-10-12 Infineon Technologies AG Power semiconductor module arrangement and housing for a power semiconductor module arrangement

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070165376A1 (en) * 2006-01-17 2007-07-19 Norbert Bones Three phase inverter power stage and assembly
US20090201649A1 (en) * 2005-10-14 2009-08-13 Juergen Jerg Electrical Device, Particularyl for Driving a Motively and/or Rgeneratively Operable Electric Machine

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1275924A (zh) * 1997-06-05 2000-12-06 罗伯特·R·霍尔库姆 产生胶态无机聚合物驻极体
DE102006025453B4 (de) 2006-05-31 2009-12-24 Infineon Technologies Ag Halbleiterschaltungsanordnung
US7511961B2 (en) * 2006-10-26 2009-03-31 Infineon Technologies Ag Base plate for a power semiconductor module
US9373563B2 (en) 2007-07-20 2016-06-21 Infineon Technologies Ag Semiconductor assembly having a housing
JP2010129867A (ja) * 2008-11-28 2010-06-10 Mitsubishi Electric Corp 電力用半導体装置
DE102009026558B3 (de) 2009-05-28 2010-12-02 Infineon Technologies Ag Leistungshalbleitermodul mit beweglich gelagerten Schaltungsträgern und Verfahren zur Herstellung eines solchen Leistungshalbleitermoduls

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090201649A1 (en) * 2005-10-14 2009-08-13 Juergen Jerg Electrical Device, Particularyl for Driving a Motively and/or Rgeneratively Operable Electric Machine
US20070165376A1 (en) * 2006-01-17 2007-07-19 Norbert Bones Three phase inverter power stage and assembly

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681552A (zh) * 2012-09-04 2014-03-26 赛米控电子股份有限公司 功率半导体模块和用于制造功率半导体模块的方法
CN103681552B (zh) * 2012-09-04 2018-01-09 赛米控电子股份有限公司 功率半导体模块和用于制造功率半导体模块的方法
CN103871978A (zh) * 2012-12-18 2014-06-18 株式会社东芝 半导体装置
CN104064526A (zh) * 2013-03-20 2014-09-24 赛米控电子股份有限公司 功率半导体模块和带有该功率半导体模块的系统
CN104064526B (zh) * 2013-03-20 2018-10-16 赛米控电子股份有限公司 功率半导体模块和带有该功率半导体模块的系统
CN106561076A (zh) * 2015-10-01 2017-04-12 现代自动车株式会社 具有导热界面材料的逆变器及应用其的混合动力车
CN106501906A (zh) * 2016-10-26 2017-03-15 博为科技有限公司 一种10g pon bosa贴
CN111863763A (zh) * 2020-06-30 2020-10-30 扬州国扬电子有限公司 一种结构紧凑型ipm功率模块

Also Published As

Publication number Publication date
CN102468295B (zh) 2015-06-24
DE102011085282B4 (de) 2022-02-10
US20120106086A1 (en) 2012-05-03
US8446726B2 (en) 2013-05-21
DE102011085282A1 (de) 2012-05-03

Similar Documents

Publication Publication Date Title
CN102468295B (zh) 具有插入物的半导体模块以及用于生产具有插入物的半导体模块的方法
CN101071809B (zh) 功率半导体模块
US11533824B2 (en) Power semiconductor module and a method for producing a power semiconductor module
CN104517909A (zh) 带有印制电路板的半导体模块及其制造方法
KR20140107292A (ko) 차량용 전자 모듈
EP3511977A1 (en) Semiconductor module and method for producing the same
EP3499649A1 (en) Power semiconductor module arrangement
US11037867B2 (en) Semiconductor module
JP2019531600A (ja) パワーモジュール
CN108735722B (zh) 半导体装置及半导体装置的制造方法
US20220310536A1 (en) Housing, semiconductor module and methods for producing the same
CN116153880A (zh) 半导体器件和制造这种半导体器件的方法
US11978683B2 (en) Semiconductor apparatus
US11004695B2 (en) Power semiconductor module arrangement having a base plate and a contact element
CN111033723B (zh) 功率半导体模块
EP4050650A1 (en) Power semiconductor module arrangement
US11937413B2 (en) Power electronics module and method for fabricating a power electronics module
EP4350764A1 (en) A semiconductor package assembly
US20230369177A1 (en) Molded semiconductor package having an embedded inlay
EP3863045A1 (en) Power semiconductor module arrangement and method for producing the same
US20230326830A1 (en) Semiconductor package module including vertical terminals
EP3703121B1 (en) Semiconductor device and method for manufacturing semiconductor device
EP3806142A1 (en) Semiconductor module and method for producing the same
CN114121826A (zh) 半导体组件
CN114188294A (zh) 半导体封装件及半导体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant