CN114188294A - 半导体封装件及半导体装置 - Google Patents

半导体封装件及半导体装置 Download PDF

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Publication number
CN114188294A
CN114188294A CN202111062226.0A CN202111062226A CN114188294A CN 114188294 A CN114188294 A CN 114188294A CN 202111062226 A CN202111062226 A CN 202111062226A CN 114188294 A CN114188294 A CN 114188294A
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China
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semiconductor package
semiconductor
exposed
substrate
conductor substrate
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CN202111062226.0A
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中田洋辅
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

目的在于针对将多个半导体元件和配线用元件进行树脂封装而一体化的半导体封装件提高布局的自由度以及组装的容易度。半导体封装件(1)所具有的多个半导体元件(3)各自具有：正面电极(32)，其设置于半导体基板(31)的与导体基板(2)相反侧；背面电极，其设置于半导体基板的导体基板侧，与导体基板接合；控制焊盘(34)，其用于对在正面电极与背面电极之间流过的电流进行控制；框体(5)，其与正面电极电连接，该框体的一部分从露出了导体基板的下表面的封装材料(8)的面露出；以及多个端子块(6)，它们与多个第1焊盘(43a)电连接，多个端子块的一部分从封装材料的与露出了导体基板的下表面的面相反侧的面露出。

Description

半导体封装件及半导体装置
技术领域
本发明涉及半导体封装件及半导体装置。
背景技术
在专利文献1中公开了将配线用元件与多个半导体元件进行树脂封装而一体化的结构的半导体装置。
专利文献1：国际公开第2010/110170号
发明内容
就专利文献1所记载的半导体装置而言，例如为了将源极电极与外部的电路进行连接，需要设置诸如导线键合或者引线框这样的外部连接部件。另外，在配线用元件被设置于半导体装置的中央的情况下，控制端子的连接部件与主电流的连接部件发生干涉，所以存在布局受到限制这一问题。本发明就是为了解决上述问题而提出的，其目的在于针对将配线用元件和多个半导体元件进行树脂封装而一体化的半导体封装件，提高布局的自由度以及组装的容易度。
本发明的半导体封装件具有：导体基板；多个半导体元件，它们与导体基板的上表面接合，多个半导体元件具有通断功能；配线用元件，其与导体基板的上表面接合，该配线用元件的数量比多个半导体元件少；以及封装材料，其将导体基板的除了下表面以外的一部分、多个半导体元件和配线用元件封装，多个半导体元件各自具有：第1基板；第1主电极部，其设置于第1基板的与导体基板相反侧；第2主电极部，其设置于第1基板的导体基板侧，与导体基板接合；以及
控制焊盘，其用于对在第1主电极部与第2主电极部之间流过的电流进行控制，配线用元件具有：第2基板；多个第1焊盘，它们设置于第2基板的与导体基板相反侧；以及多个第2焊盘，它们设置于第2基板的与导体基板相反侧，与多个第1焊盘电连接，通过导线而与控制焊盘连接，半导体封装件还具有：框体，其与多个半导体元件各自的第1主电极部电连接，该框体的一部分从露出了导体基板的下表面的封装材料的面露出；以及多个端子块，它们与多个第1焊盘电连接，该多个端子块的一部分从封装材料的与露出了导体基板的下表面的面相反侧的面露出。
发明的效果
根据本发明的半导体封装件，成为半导体元件的主电流路径的导体基板以及框体这两者从封装材料的一个面露出。因此，通过在封装材料的另一个面上进行与成为半导体元件的控制端子的、配线用元件的第2焊盘的连接，从而能够抑制主电流路径与配线之间的干涉。因此，配线用元件的布局的自由度提高。另外，本发明的半导体封装件将成为主电流路径的框体内置，因此，半导体封装件的与外部的电路之间的连接不需要额外的连接部件，能够容易地进行连接。因此，根据本发明的半导体封装件，能够容易地组装半导体装置。
附图说明
图1是表示导体基板之上的半导体元件和配线用元件的配置的图。
图2是图1的A-A′剖视图。
图3是从上方观察实施方式1的半导体封装件时的平面图。
图4是从下方观察实施方式1的半导体封装件时的平面图。
图5是沿图3的B-B′线的实施方式1的半导体封装件的剖视图。
图6是沿图3的C-C′线的实施方式1的半导体封装件的剖视图。
图7是与图3的B-B′线相同的剖面中的实施方式1的变形例的半导体封装件的剖视图。
图8是绝缘基板的俯视图。
图9是实施方式1的半导体装置的俯视图。
具体实施方式
1.实施方式1
1.1序
图1是表示实施方式1的半导体封装件1的示意图。但是，半导体封装件1所包含的框体5、间隔导体7、封装材料8以及多个端子块6在图1中为了方便说明而省略，在图3至图6中进行图示。
如图1所示，半导体封装件1具有导体基板2、配线用元件4以及多个半导体元件3。半导体元件3的个数只要大于或等于2个即可。另外，配线用元件4的个数只要比半导体元件3的个数少即可。在图1中，示出了具有8个半导体元件3和1个配线用元件4的半导体封装件1，以下，对该半导体封装件1进行说明。
各半导体元件3与导体基板2的上表面接合，与导体基板2电连接且热连接。配线用元件4也与各半导体元件3同样地，与导体基板2的上表面接合，与导体基板2电连接且热连接。在图1的例子中，在俯视观察时8个半导体元件3以包围配线用元件4的方式而配置。
1.2半导体元件
各半导体元件3是具有通断功能的元件，例如是包含SiC作为半导体材料的MOSFET(以下，称为“SiC-MOSFET”)。但是，各半导体元件3也可以是包含Si等除了SiC以外的材料作为半导体材料的半导体元件。另外，各半导体元件3也可以是IGBT(Insulated GateBipolar Transistor)等除了MOSFET以外的半导体元件。
如图1所示，各半导体元件3具有第1基板即半导体基板31、正面电极32、背面电极(未图示)、耐压构造35以及1个或者多个控制焊盘34。
第1主电极部即正面电极32设置于半导体基板31的与导体基板2相反侧的面即正面。正面电极32对应于MOSFET的源极电极。
第2主电极部即背面电极(未图示)设置于半导体基板31的导体基板2侧的面即背面，与导体基板2接合。由此，各半导体元件3的背面电极的电位彼此相等。背面电极对应于MOSFET的漏极电极。
控制焊盘34是用于对在正面电极32与背面电极之间流过的电流进行控制的焊盘。控制焊盘34对应于MOSFET的栅极电极。
正面电极32、背面电极以及控制焊盘34例如具有Ni、Cu、Au或者Ag等可烧结连接的膜。正面电极32、背面电极以及控制焊盘34也可以是Al等电极材料与其上的可烧结连接的膜之间的层叠构造。
1.3配线用元件
图2是沿图1的A-A′线的剖视图。但是，在图2中省略了导体基板2的图示。如图2所示，配线用元件4具有第2基板即配线用基板41、绝缘膜42、金属膜44、保护膜45以及多个连接配线43。
配线用基板41例如由Si构成。
多个连接配线43隔着绝缘膜42而设置于配线用基板41的与导体基板2相反侧的面即正面。各连接配线43具有第1焊盘43a、第2焊盘43b以及绕引部43c。第1焊盘43a与第2焊盘43b通过绕引部43c而电连接。
多个连接配线43例如是由Al构成的电极图案。也可以在多个连接配线43中的至少第1焊盘43a形成有例如Ni、Cu、Au或者Ag等可烧结连接的膜46。也可以根据需要，在第2焊盘43b或者绕引部43c形成有可烧结连接的膜46。另外，连接配线43自身也可以由可烧结连接的材料构成。
金属膜44设置于配线用基板41的导体基板2侧的面即背面，与导体基板2接合。即，金属膜44是用于与导体基板2接合的膜。
保护膜45将绝缘膜42的至少一部分和连接配线43的至少一部分覆盖。第1焊盘43a和第2焊盘43b从保护膜45露出。
1.4半导体元件与配线用元件的连接
各半导体元件3的控制焊盘34与配线用元件4的第2焊盘43b电连接。该连接也可以使用由Au或者Ag构成的细导线或者由Al构成的导线。
各半导体元件3的背面电极和配线用元件4的金属膜44都与导体基板2连接。
各半导体元件3的正面电极32与框体5(参照图3至图6)连接。
在配线用元件4的第1焊盘43a连接端子块6。
各半导体元件3的背面电极与导体基板2的接合、金属膜44与导体基板2的接合、正面电极32与框体5的接合以及第1焊盘43a与端子块6的连接能够使用烧结接合。烧结接合所使用的接合材料例如由Ag或者Cu构成。该接合材料通过加压接合工艺或者不加压接合工艺等而形成连接。
在半导体元件3的上表面的正面电极32的周边存在耐压构造35，半导体元件3的端部成为漏极电位。因此，为了使半导体元件3的端部与框体5绝缘，需要一定程度的绝缘距离。因此，为了创造半导体元件3的端部与框体5之间的距离，正面电极32也可以经由间隔导体7(参照图5)而与框体5连接。间隔导体7可以是与框体5一体形成的部件，也可以是通过接合材料与框体5连接的单独的部件。
1.5封装
多个半导体元件3、1个或者多个配线用元件4、导体基板2的至少一部分、框体5的至少一部分、多个端子块6的至少一部分被封装材料8封装。
图3至图6是表示包含框体5和封装材料8的半导体封装件1的图。
图3是从正面侧观察半导体封装件1时的平面图。如图3所示，在俯视观察时，框体5在其中央部具有开口。框体5的开口与配线用元件4重叠，由此框体5不与配线用元件4连接(参照图5)。并且，框体5的开口也可以到达与配线用元件4连接的半导体元件3的控制焊盘34的上部。在这种情况下，能够设置框体5而无需考虑将配线用元件4与控制焊盘34连接的导线键合的导线的高度。另外，配线用元件4的与第1焊盘43a连接的端子块6如图3所示，其一部分从封装材料8的上表面露出。
图4是从背面侧观察半导体封装件1时的平面图。图5是沿图3的B-B′线的半导体封装件1的剖视图。图6是沿图3的C-C′线的半导体封装件1的剖视图。如图4至图6所示，导体基板2的下表面和框体5的至少2个部位从封装材料8的下表面露出。此外，在图5中为了方便说明而省略了导线的图示。
从封装材料8的下表面露出的框体5的2个露出部如图5及图6所示，隔着同样从封装材料8的下表面露出的导体基板2的下表面而相对。
如图5及图6所示，在从封装材料8露出的导体基板2的下表面与从封装材料8露出的框体5的露出部之间设置有用于确保导体基板2与框体5之间的绝缘距离的沿面构造8a。在图5及图6中，沿面构造8a是封装材料8的凹型的部分。
如图7所示，沿面构造8a也可以是封装材料8的凸形的部分。图5或者图7所示的沿面构造8a是使用在由传递模塑法实现的半导体封装件的封装工序中使用的模具而形成的。如图7所示，在沿面构造8a是封装材料8的凸型的部分的情况下，通过在半导体封装件1与后述的绝缘基板12接合时，在与电路图案的间隙重叠的位置配置沿面构造8a，从而能够将沿面构造8a用作针对电路图案的半导体封装件1的定位部件。此外，在图7中，为了方便说明而省略了导线的图示。
1.6半导体装置
图8是绝缘基板12的俯视图。绝缘基板12具有绝缘基材13和在绝缘基材13的上表面彼此隔开间隙而设置的多个电路图案10N、10P、10O1、10O2。
通过在绝缘基板12的电路图案10N、10P、10O1、10O2电连接且热连接多个半导体封装件1，从而形成半导体装置11。电路图案10N、10P、10O1、10O2与各半导体封装件1之间的连接也可以使用焊接或者烧结接合。
图9是包含2个半导体封装件1的半导体装置11的俯视图。半导体装置11构成半桥电路，上桥臂和下桥臂各自各使用1个半导体封装件1。此外，上桥臂或者下桥臂也可以使用多个半导体封装件1。
在图9中，将上桥臂用的半导体封装件记作半导体封装件1H，将下桥臂用的半导体封装件记作半导体封装件1L。
电路图案10P以及电路图案10N分别对应于半导体装置11的P电位以及N电位。另外，电路图案10O1、10O2对应于半导体装置11的输出电位。电路图案10O1、10O2配置于隔着电路图案10P而相对的位置。
如图5至图7所示的那样，框体5的至少2个部位和导体基板2从半导体封装件1的背面露出。就上桥臂的半导体封装件1H而言，导体基板2的下表面与电路图案10P连接，框体5的一个露出部与电路图案10O2连接，另一个露出部与电路图案10O1连接。即，上桥臂的半导体封装件1H的框体5的另一个露出部连接至在下桥臂的半导体封装件1L处与导体基板2连接的电路图案10O1。
在电路图案10O2连接有用于从半导体装置11引出电流的输出端子51。在电路图案10P连接P主电极52，在电路图案10N连接N主电极53。P主电极52以及N主电极53与外部的电容模块等连接。
就下桥臂的半导体封装件1L而言，导体基板2与电路图案10O1连接，框体5的2个露出部与电路图案10N连接。
就下桥臂的半导体封装件1L而言，也与半导体封装件1H同样地，框体5以2个部位从封装材料8露出，因此，电路图案10N在与框体5的各露出部对应的位置处分支地配置。
上桥臂的半导体封装件1H配置于输出端子51侧，下桥臂的半导体封装件1L配置于P主电极52和N主电极53侧。上桥臂的半导体封装件1H和下桥臂的半导体封装件1L以彼此呈大致直角的方向配置。
半导体封装件1的平面形状为矩形。多个端子块6相对于半导体封装件1的俯视观察时的外形的边而沿倾斜方向排列。
各端子块6通过导线55而与外部信号端子54电连接。被输入至外部信号端子54的控制信号经由端子块6和配线用元件4的连接配线43而被传送至半导体元件3。如此，半导体封装件1被驱动，半导体装置11的电路进行动作。此外，外部信号端子54与端子块6之间的接合也可以是不使用导线的直接接合。
1.7作用效果
与半导体元件3的背面电极连接的导体基板2和与半导体元件3的正面电极32连接的框体5从半导体封装件1的下表面露出。从半导体封装件1的上表面仅露出端子块6。因此，不需要设置用于对主电流进行处理的电流容量大的配线连接，能够通过简单的连接方法而构成半导体装置11。
就半导体封装件1而言，作为主电流路径的框体5除了露出部以外都包在封装材料8内，因此，不需要使用外部的配线材料而对主电极进行连接。并且，能够通过同一芯片键合工序将半导体元件3的背面以及正面与电路图案连接，因此，半导体装置11的制造工序减少。在组装电路规模大的半导体装置11的情况下，有时由于使用尺寸大的部件，因此公差变大。但是，半导体封装件1将框体5内置，因此公差小。因此，能够稳定地生产制造性以及可靠性高的半导体装置11。
另外，能够使电路图案彼此尽可能地接近，因此能够使半导体装置11的寄生电感尽可能地减小。因此，能够抑制在半导体元件3使用了SiC-MOSFET的情况下产生的阻尼振荡。
端子块6通过少量导线与外部信号端子54连接。或者，端子块6使用焊料等直接与外部信号端子54连接。无论在哪种情况下，端子块6与外部信号端子54之间的连接都在半导体封装件1的上表面侧进行，因此，不与半导体封装件1的下表面侧的主电流电路图案发生干涉。因此，布局自由度和成品率提高。其结果，能够通过简单的组装而构成半导体装置11，制造成本降低。
就图9所示的半导体装置11而言，通过使用半导体封装件1而提高电路图案的布局的自由度，因此，能够实现低Ls化以及省空间化。
另外，上桥臂的半导体封装件1H与下桥臂的半导体封装件1L以大致直角而配置，由此电路图案为等长配线，能够实现低Ls化以及防止不平衡动作。
另外，通过使多个端子块6相对于半导体封装件1的边而倾斜地排列，从而即使使上桥臂的半导体封装件1H与下桥臂的半导体封装件1L以大致直角而配置，也得到以下2个效果。
第1效果是在对端子块6与外部信号端子54进行导线键合接合时，抑制导线彼此干涉。
第2效果为能够使外部信号端子54相对于上桥臂的半导体封装件1H的排列与外部信号端子54相对于下桥臂的半导体封装件1L的排列平行。由此，确保了控制基板相对于外部信号端子54的安装性。
因此，就上桥臂的半导体封装件1H的配置方向与下桥臂的半导体封装件1L的配置方向所成的角而言，在取得上述2个效果的范围，也可以不是严格的直角。上述的“大致直角”中的“大致”意味着容许上述这样的误差。
通过使用封装材料8的一部分而形成沿面构造8a，从而能够省去由设置沿面构造8a导致的追加的成本，除了创造沿面距离之外，还能够实现半导体封装件1的小型化。在沿面构造8a为封装材料8的一部分的凸部的情况下，通过设为使沿面构造8a进入电路图案彼此的间隙中的设计，从而能够用作自对准的部件，能够提高半导体装置11的制造性。
此外，能够对各实施方式自由地进行组合，或者对各实施方式适当地进行变形、省略。
标号的说明
1、1H、1L半导体封装件，2导体基板，3半导体元件，4配线用元件，5框体，6端子块，7间隔导体，8封装材料，8a沿面构造，10N、10O1、10O2、10P电路图案，11半导体装置，12绝缘基板，13绝缘基材，31半导体基板，32正面电极，34控制焊盘，35耐压构造，41配线用基板，42绝缘膜，43连接配线，43a第1焊盘，43b第2焊盘，43c绕引部，44金属膜，45保护膜，51输出端子，52P主电极，53N主电极，54外部信号端子，55导线。

Claims (8)

1.一种半导体封装件，其具有：
导体基板；
多个半导体元件，它们与所述导体基板的上表面接合，所述多个半导体元件具有通断功能；
配线用元件，其与所述导体基板的上表面接合，该配线用元件的数量比所述多个半导体元件少；以及
封装材料，其将所述导体基板的除了下表面以外的一部分、所述多个半导体元件和所述配线用元件封装，
所述多个半导体元件各自具有：
第1基板；
第1主电极部，其设置于所述第1基板的与所述导体基板相反侧；
第2主电极部，其设置于所述第1基板的所述导体基板侧，与所述导体基板接合；以及
控制焊盘，其用于对在所述第1主电极部与所述第2主电极部之间流过的电流进行控制，
所述配线用元件具有：
第2基板；
多个第1焊盘，它们设置于所述第2基板的与所述导体基板相反侧；以及
多个第2焊盘，它们设置于所述第2基板的与所述导体基板相反侧，与所述多个第1焊盘电连接，通过导线而与所述控制焊盘连接，
所述半导体封装件还具有：
框体，其与所述多个半导体元件各自的所述第1主电极部电连接，该框体的一部分从露出了所述导体基板的下表面的所述封装材料的面露出；以及
多个端子块，它们与所述多个第1焊盘电连接，该多个端子块的一部分从所述封装材料的与露出了所述导体基板的下表面的面相反侧的面露出。
2.根据权利要求1所述的半导体封装件，其中，
在从所述封装材料露出的所述导体基板的下表面与从所述封装材料露出的所述框体的露出部之间还具有凸形或者凹形的沿面构造。
3.一种半导体装置，其具有：
权利要求1或2所述的至少1个半导体封装件；以及
绝缘基板，其接合了所述至少1个半导体封装件，
所述绝缘基板具有：
绝缘基材；以及
多个电路图案，它们在所述绝缘基材的上表面彼此隔开间隙而设置，
所述多个电路图案连接于从所述封装材料露出的所述导体基板的下表面和从所述封装材料露出的所述框体的露出部。
4.根据权利要求3所述的半导体装置，其中，
所述至少1个半导体封装件是权利要求2所述的至少1个半导体封装件，
所述沿面构造是所述封装材料的一部分，呈凸形，在所述至少1个半导体封装件与所述绝缘基板接合时，所述沿面构造与所述多个电路图案的间隙重叠。
5.根据权利要求3或4所述的半导体装置，其中，
所述至少1个半导体封装件构成半桥电路的上桥臂和下桥臂的每一者，
就所述至少1个半导体封装件各自而言，所述框体的至少2个部位从所述封装材料露出。
6.根据权利要求5所述的半导体装置，其中，
就所述至少1个半导体封装件各自而言，所述框体的从所述封装材料露出的2个露出部在俯视观察时隔着从所述封装材料露出的所述导体基板的下表面而相对，
构成所述下桥臂的所述至少1个半导体封装件的所述框体的从所述封装材料露出的所述2个露出部与对应于N主电极的所述电路图案连接，
构成所述上桥臂的所述至少1个半导体封装件的所述框体的从所述封装材料露出的所述2个露出部的一者与所述半导体装置的输出端子连接，另一者连接至与构成所述下桥臂的所述至少1个半导体封装件的所述导体基板连接的所述电路图案。
7.根据权利要求6所述的半导体装置，其中，
构成所述上桥臂的所述至少1个半导体封装件相对于构成所述下桥臂的所述至少1个半导体封装件的配置方向以大致直角而配置。
8.根据权利要求7所述的半导体装置，其中，
所述至少1个半导体封装件的平面形状为矩形，
所述多个端子块相对于所述至少1个半导体封装件的俯视观察时的外形的边而倾斜地排列。
CN202111062226.0A 2020-09-15 2021-09-10 半导体封装件及半导体装置 Pending CN114188294A (zh)

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