CN102458048B - 电子元件 - Google Patents

电子元件 Download PDF

Info

Publication number
CN102458048B
CN102458048B CN201110319259.9A CN201110319259A CN102458048B CN 102458048 B CN102458048 B CN 102458048B CN 201110319259 A CN201110319259 A CN 201110319259A CN 102458048 B CN102458048 B CN 102458048B
Authority
CN
China
Prior art keywords
substrate
pad
electronic component
side pad
strengthening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110319259.9A
Other languages
English (en)
Other versions
CN102458048A (zh
Inventor
中川仁
德山现
水野祐树
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aisin AW Co Ltd
Original Assignee
Aisin AW Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aisin AW Co Ltd filed Critical Aisin AW Co Ltd
Publication of CN102458048A publication Critical patent/CN102458048A/zh
Application granted granted Critical
Publication of CN102458048B publication Critical patent/CN102458048B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02135—Flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06132—Square or rectangular array being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
    • H01L2224/06517—Bonding areas having different functions including bonding areas providing primarily mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16106—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting one bonding area to at least two respective bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32106—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting one bonding area to at least two respective bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3305—Shape
    • H01L2224/33051—Layer connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/33104—Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/33106—Disposition relative to the bonding areas, e.g. bond pads the layer connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

一种待安装到基板上的电子元件及电子设备，其中电子元件包括：电子元件侧焊盘，其当所述电子元件被安装到所述基板上时面向设置在所述基板上的基板侧焊盘，其中，在面向所述基板侧焊盘的所述电子元件侧焊盘的表面上设置有非焊接区域，从而使得所述基板侧焊盘的形状不同于面向所述基板侧焊盘的所述电子元件侧焊盘的形状。本发明提供的电子元件及电子设备能够减少焊接部分的残留空隙，进而可以稳定地保证在电子元件和基板之间有适当的焊接面积。

Description

电子元件
通过引用的并入
于2010年10月27日递交的包括说明书、附图和摘要的日本专利申请号为2010-241338的公开文件通过引用的方式整体并入于此。
技术领域
本发明涉及一种电子元件及电子设备。
背景技术
在现有的技术中，用于将电子元件安装在基板上的焊接铜箔(下文中称作“焊盘(land)”)被设置在基板和电子元件上。特别地，近年来，为了减小电子元件在基板上的占用面积，使用诸如球栅阵列(BGA)和焊盘栅格阵列(LGA)这类的封装将焊盘直接设置在电子元件的下方。
在以这种方式经由焊盘被焊接到基板上的电子元件中，为了改善连接焊盘部分的连接可靠性，提出了一种模块元件，其中在以栅格形式排列在模块基板背面的连接焊盘最外围附近设置有面积为一个连接焊盘面积的3倍或更大的强化焊盘(例如，参见专利号为2859143的日本专利)。
发明内容
由于焊料的表面张力、回流期间电子元件或者基材产生的气体等，在焊接部分可能产生空隙。特别地，如果如同上文描述的现有元件的情况那样设置有大面积焊盘，则可能空隙出现的频率增加，并且所产生的每一空隙的尺寸增大。这样，如果在焊接部分中产生的空隙数量过多然后空隙还保留在焊接部分中，则电子元件和基板之间的焊接面积减小，并且可能导致电气特性和导热性变差。
本发明提供了一种电子元件和电子设备，能够减少焊接部分中的残留空隙，从而可以稳定地保证电子元件和基板之间有合适的焊接面积。
本发明的第一方案提供了一种待安装到基板上的电子元件。该电子元件包括：电子元件侧焊盘，其当所述电子元件被安装到所述基板上时面向设置在所述基板上的基板侧焊盘，其中，在面向所述基板侧焊盘的所述电子元件侧焊盘的表面上设置有非焊接区域，从而使得所述基板侧焊盘的形状不同于面向所述基板侧焊盘的所述电子元件侧焊盘的形状。
使用根据第一方案的电子元件，非焊接区域设置在面向基板侧焊盘的电子元件侧焊盘的表面上，从而使得基板侧焊盘的形状不同于面向基板侧焊盘的电子元件侧焊盘的形状，因而所产生的空隙中的气体可以经由非焊接区域和基板侧焊盘之间的间隙从焊接部分释放出来。通过这样做，减少了焊接部分的残留空隙，进而可以稳定地保证在电子元件和基板之间有适当的焊接面积。
本发明的第二方案提供了一种待安装到基板上的电子元件。该电子元件包括：多个电子元件侧焊盘，其当所述电子元件被安装到所述基板上时分别面向设置在所述基板上的多个基板侧焊盘，其中，所述多个电子元件侧焊盘包括设置在面向所述基板的所述电子元件表面中心处的接地焊盘(这里所说的“中心”不一定是正中央，而只要是面向基板的该电子元件表面的非边缘部分即可)，以及围绕所述接地焊盘设置的多个输入/输出焊盘；所述多个输入/输出焊盘包括强化焊盘，所述强化焊盘设置于面向所述基板的所述电子元件的表面的外围附近，并且形成为面积大于其他的输入/输出焊盘的面积；并且在面向所述基板侧焊盘的所述强化焊盘的表面上设置有非焊接区域，从而使得所述基板侧焊盘的形状不同于面向所述基板侧焊盘的所述强化焊盘的形状。
使用根据第二方案的电子元件，非焊接区域设置在面向基板侧焊盘的强化焊盘的表面上，从而使得基板侧焊盘的形状不同于面向基板侧焊盘的强化焊盘的形状，因而所产生的空隙中的气体可以经由非焊接区域和基板侧焊盘之间的间隙从焊接部分释放出来。通过这样做，减少了强化焊盘和基板侧焊盘之间的焊接部分(在该部分尤其容易产生空隙)的残留空隙，进而可以稳定地保证在电子元件和基板之间有合适的焊接面积。
本发明的第三方案提供了一种电子设备。该电子设备包括：基板，包括基板侧焊盘；以及电子元件，包括当所述电子元件被安装到所述基板上时面向所述基板侧焊盘的电子元件侧焊盘，其中，在面向所述电子元件侧焊盘的所述基板侧焊盘表面以及在面向所述基板侧焊盘的所述电子元件侧焊盘的表面这两个表面至少之一上设置非焊接区域，从而使得所述基板侧焊盘的形状不同于面向所述基板侧焊盘的所述电子元件侧焊盘的形状。
使用根据第三方案的电子设备，在面向电子元件侧焊盘的基板侧焊盘表面以及在面向基板侧焊盘的所述电子元件侧焊盘的表面这两个表面至少之一上设置非焊接区域，从而使得基板侧焊盘的形状不同于面向基板侧焊盘的电子元件侧焊盘的形状，因而所产生的空隙中的气体可以经由非焊接区域和基板侧焊盘之间形成的间隙从焊接部分释放出来。通过这样做，减少了焊接部分的残留空隙，进而可以稳定地保证电子元件和基板之间有合适的焊接面积。
另外，本发明还提供一种待安装到基板上的电子元件，包括：电子元件侧焊盘，其当所述电子元件被安装到所述基板上时面向设置在所述基板上的基板侧焊盘，其中，在面向所述基板侧焊盘的所述电子元件侧焊盘的表面上设置有非焊接区域，从而使得所述基板侧焊盘的形状不同于面向所述基板侧焊盘的所述电子元件侧焊盘的形状；设置有面积不同的多个所述电子元件侧焊盘，并且所述非焊接区域设置在多个所述电子元件侧焊盘中面积最大的电子元件侧焊盘上。
另外，本发明还提供一种电子设备，包括：基板，包括基板侧焊盘；以及电子元件，包括当所述电子元件被安装到所述基板上时面向所述基板侧焊盘的电子元件侧焊盘，其中，在面向所述电子元件侧焊盘的所述基板侧焊盘的表面以及在面向所述基板侧焊盘的所述电子元件侧焊盘的表面这两个表面至少之一上设置非焊接区域，从而使得所述基板侧焊盘的形状不同于面向所述基板侧焊盘的所述电子元件侧焊盘的形状；在所述电子元件设置有面积不同的多个所述电子元件侧焊盘，并且所述非焊接区域设置在多个所述电子元件侧焊盘中面积最大的电子元件侧焊盘上。
附图说明
以下将参照附图描述本发明的特征、优点以及技术和工业重要性，在图中，相似的附图标记表示相似的元件，其中：
图1A和图1B是示出电子元件的视图，其中，图1A是电子元件的侧面图，图1B是电子元件的平面图；
图2A和图2B是示出基板的视图，其中，图2A是基板的平面图，图2B是基板的侧面图；
图3A和图3B是显示电子元件被安装在基板上的状态下的视图，其中，图3A是示出焊料被提供到每一电子元件侧焊盘和对应的基板侧焊盘之间的状态下的侧面剖视图，图3B是示出电子元件被安装在基板上之后的状态下的侧面剖视图；
图4A和图4B是显示根据替换实施例的电子元件被安装在基板上的状态下的视图，其中，图4A是示出焊料被提供到每一电子元件侧焊盘和对应的基板侧焊盘之间的状态下的侧面剖视图，图4B是示出电子元件被安装到基板上之后的状态下的侧面剖视图；
图5是一些电子元件侧焊盘和一些基板侧焊盘被槽分开的情况下电子元件的平面图；
图6是一些电子元件侧焊盘和一些基板侧焊盘被槽分开的情况下基板的平面图；
图7A和图7B是示出一些电子元件侧焊盘和一些基板侧焊盘被槽分开的情况下的视图，其中，图7A是示出焊料被提供到每一电子元件侧焊盘和对应的基板侧焊盘之间的状态下的侧面剖视图，图7B是示出电子元件被安装到基板上之后的状态下的侧面剖视图；
图8是示出电子元件被安装到基板上之后的状态下的侧面剖视图。
具体实施方式
在下文中，将参照附图详细描述根据本发明的方案的电子元件及电子设备的实施例。然而，本发明的方案不限于实施例。此外，在以下的描述中，“焊盘”是指用于将电子元件安装到基板上的焊接金属薄膜(铜箔等)。
首先，将描述根据实施例的电子设备的结构。该电子设备包括基板和安装在基板上的电子元件。图1A和图1B是示出电子元件的视图，其中，图1A是电子元件的侧面图，图1B是电子元件的平面图。此外，图2A和图2B是示出基板的视图，其中，图2A是基板的平面图，图2B是基板的侧面图。
以下将描述电子元件。如图1A和图1B所示，电子元件3包括电子元件侧焊盘30。当电子元件3被安装在基板上时，电子元件侧焊盘30面向基板上的基板侧焊盘。电子元件侧焊盘30在电子元件3的面向基板的表面上形成为以具有通过已知方法(例如蚀刻和加成工艺(additive process))形成的预期形状的金属(例如铜)制成的薄膜。图1A和图1B示出了设置了具有矩形平面形状的多个电子元件侧焊盘30的情况。
以下将描述电子元件侧焊盘。电子元件侧焊盘30包括接地焊盘31和输入/输出焊盘32。接地焊盘31是用于将电子元件3接地的焊盘，基本上设置在面向基板的电子元件3的表面中心，。输入/输出焊盘32是用于将电子元件3和基板之间的信号输入或输出的焊盘，围绕接地焊盘31设置。此外，输入/输出焊盘32包括强化焊盘33。强化焊盘33是用于将电子元件3和基板之间的信号输入或输出并用于强化电子元件3和基板之间的连接的焊盘。强化焊盘33设置在面向基板的电子元件3的表面的外围附近(在本实施例中是指边角部分)。每一强化焊盘33的面积均大于其他输入/输出焊盘32的面积。注意，在多个强化焊盘33中，每一强化焊盘33的面积均相等。这样，通过在电子元件3的边角部分(图1B的四个角)设置每一个的面积均大于其他输入/输出焊盘32的面积的强化焊盘33，能够抑制电子元件3和基板之间焊接部分的焊料中的疲劳开裂/断裂，进而可以改善连接可靠性。稍后将描述这些电子元件侧焊盘30的形状的细节。
以下将描述基板的结构。如图2A和图2B所示，基板2包括基板侧焊盘20。基板侧焊盘20在基板2的面向电子元件3的表面上形成为以具有通过已知方法(例如蚀刻和加成工艺)制成的预期形状的金属(例如铜)制成的薄膜。图2A和图2B示出了设置了具有矩形平面形状的多个基板侧焊盘20的情况。这些基板侧焊盘20和面向基板侧焊盘20的电子元件侧焊盘30成对地布置在各配置(arrangement)位置。稍后将描述每一基板侧焊盘20的形状的细节。
接下来将描述每一电子元件侧焊盘30的形状和每一基板侧焊盘20的形状。除了强化焊盘33之外的每一电子元件侧焊盘(即除了强化焊盘33之外的接地焊盘31和输入/输出焊盘32)的形状均形成为与面向对应的电子元件侧焊盘30的每一基板侧焊盘20的形状基本上相同(即，基板侧焊盘20与对应的电子元件侧焊盘30成对)。
另一方面，在强化焊盘33中，为了使得每一基板侧焊盘20的形状改变为不同于面向基板侧焊盘20的每一强化焊盘33的形状，在每一强化焊盘33的面向基板侧焊盘20的表面上设置有用作非焊接区域的槽34。此处，“非焊接区域”是指没有焊料附着在焊盘上的区域。例如，可以通过在焊盘中设置槽来实体地形成非焊接区域，或者可以通过在焊盘上设置阻焊层来形成非焊接区域。在本实施例中，每一强化焊盘33均被槽34分开，被槽34分开的每一强化焊盘33的平面形状不同于位于面向强化焊盘33的位置处的基板侧焊盘20的平面形状。
例如，当电子元件3被安装在基板2上时，图1B中被虚线P围住的强化焊盘33面向图2A中被虚线R围住的基板侧焊盘20。在这种情况下，在图1B中被虚线P围住的强化焊盘33被槽34分开；而在面向强化焊盘33的位置处的基板侧焊盘20(在图2A中被虚线R围住的基板侧焊盘20)并没有被槽分开，因而强化焊盘33的平面形状不同于面向强化焊盘33的基板侧焊盘20的平面形状。类似地，在图1B中被虚线Q围住的强化焊盘33被槽34分开；而在面向强化焊盘33的位置处的基板侧焊盘20(在图2A中被虚线S围住的基板侧焊盘20)并没有被槽分开，因而强化焊盘33的平面形状不同于面向强化焊盘33的基板侧焊盘20的平面形状。
接下来，将描述如此配置的电子元件3和电子设备的功能。图3A和图3B是显示电子元件3被安装在基板2上的状态下的视图，其中，图3A是示出焊料被提供到每一电子元件侧焊盘30和对应的一个基板侧焊盘20之间的状态下的侧面剖视图，图3B是示出电子元件3被安装在基板2上之后的状态下的侧面剖视图。注意，图3A和图3B显示了图1B中示出的电子元件3和图2A中示出的基板2的III-III剖视图。
例如，当通过已知焊接方法(例如回流焊接)将焊料提供到每一电子元件侧焊盘30和对应的一个基板侧焊盘20之间时，如图3A所示，每一基板侧焊盘20和电子元件侧焊盘30中具有相对大面积的对应的一个电子元件侧焊盘30(例如，在设置于面向基板2的电子元件3的表面外围附近的多个电子元件侧焊盘30中面积最大的强化焊盘33，以及所有电子元件侧焊盘30中面积最大的电子元件侧焊盘30)之间的焊料中可能产生空隙。在现有的电子元件的情况下，这种空隙被强化焊盘、基板侧焊盘和周围焊料封闭，并且在焊料冷却后保留在焊接部分中，因而电子元件和基板之间的焊接面积减小。
相反，在本实施例中，在每一强化焊盘33的面向基板侧焊盘20的表面上设置了槽34，因而所产生的空隙中的气体经由每一槽34和对应的基板侧焊盘20之间的间隙从焊接部分释放出来。因此，如图3B所示，除了强化焊盘33的槽34的位置与基板侧焊盘20之间形成的V形间隙部分之外，每一强化焊盘33和对应的基板侧焊盘20之间的空间被焊料填充。通过这样做，与焊接部分残留空隙的情况相比较，可以保证电子元件3和基板2之间有足够的焊接面积。
此外，当每一电子元件侧焊盘30的面向对应的基板侧焊盘20的每一表面以及每一基板侧焊盘20的面向对应的电子元件侧焊盘30的表面具有槽时，这些电子元件侧焊盘30和基板侧焊盘20中的每一个均完全被槽分开，这样，每一基板侧焊盘20的形状与面向基板侧焊盘20的对应的电子元件侧焊盘30的形状相同，例如，如图3B中的部分C的情况，焊料不会在每一电子元件侧焊盘30的槽和对应的基板侧焊盘20之间流动。这样，在每一电子元件侧焊盘30的槽和对应的基板侧焊盘20的槽之间形成具有矩形截面的间隙。因此，电子元件3和基板2之间的焊接面积减小。
相反，在本实施例中，没有为每一基板侧焊盘20设置槽，而只是每一强化焊盘33被槽34分开。通过这样做，每一强化焊盘33的平面形状不同于在面向电子元件侧焊盘的位置处的基板侧焊盘20的平面形状。因此，没有焊料流到强化焊盘33的槽34的位置；然而，焊料流到基板侧焊盘20的表面。通过这样做，如图3B所示，在强化焊盘33的槽34和对应的基板侧焊盘20之间形成了V形间隙。这样，与每一强化焊盘33的槽和对应的基板侧焊盘20的槽之间形成具有矩形截面的间隙的状态相比，可以保证在电子元件3和基板2之间有足够的焊接面积。
通过这种方式，根据本实施例，在每一强化焊盘33的面向对应的基板侧焊盘20的表面上设置槽34，因而每一基板侧焊盘20的形状不同于面向基板侧焊盘20的对应的强化焊盘33的形状，因而所产生的空隙中的气体可以经由每一槽34和对应的基板侧焊盘20之间形成的间隙从焊接部分释放出来。通过这样做，减少了焊接部分的残留空隙，进而可以稳定地保证电子元件3和基板2之间有合适的焊接面积。
特别地，为多个电子元件侧焊盘30中面积最大的每一电子元件侧焊盘30(在本实施例中指每一强化焊盘33)设置了槽34。通过这样做，每一强化焊盘33和对应的基板侧焊盘20之间的焊接部分(这部分尤其容易产生空隙)的残留空隙减少，进而可以稳定地保证电子元件3和基板2之间有合适的焊接面积。
此外，为设置在电子元件3面向基板2的表面外围附近的多个电子元件侧焊盘30中面积最大的每一电子元件侧焊盘30(在本实施例中指每一强化焊盘33)设置了槽34。通过这样做，每一强化焊盘33和对应的基板侧焊盘20之间的焊接部分(这部分尤其容易产生空隙)的残留空隙减少，进而可以稳定地保证电子元件3和基板2之间有合适的焊接面积。
此外，被槽34分开的每一强化焊盘33的平面形状不同于在面向强化焊盘33的位置处的基板侧焊盘20的平面形状，因而在每一强化焊盘33的槽34和对应的基板侧焊盘20之间形成V形间隙。通过这样做，除了上述描述的基本有益效果之外，与每一强化焊盘33的槽和对应的基板侧焊盘20的槽之间形成具有矩形截面的间隙的状态相比，还可以保证电子元件3和基板2之间有足够的焊接面积。
此外，槽34设置在每一强化焊盘33的面向对应的基板侧焊盘20的表面上，作为非焊接区域，因而所产生的空隙中的气体可以经由每一槽34和对应的基板侧焊盘20之间形成的间隙从焊接部分释放出来。
上述描述了根据本发明的方案的实施例，然而在所附的权利要求列举的技术理念的范围内，还可以对根据本发明的方案的特定结构和方式进行任意改变或改进。在下文中，将描述这些替换实施例。
首先，本发明的方案所解决的问题和本发明的方案的有益效果不限于上文的描述；而是可以依赖于本发明的方案所实施的环境或者结构的细节来改变，并且可以是只解决上述描述的部分问题，或者可以只获得上述描述的部分有益效果。
在上述描述的实施例中，每一强化焊盘33均被槽34分开，因而被槽34分开的每一强化焊盘33的平面形状不同于在面向强化焊盘33的位置处的基板侧焊盘20的平面形状；可替代地，在槽34的位置处的强化焊盘33的厚度可以不同于在面向槽34的位置处的基板侧焊盘20的厚度。图4A和图4B是示出根据替换实施例的电子元件3被安装在基板2上的状态下的视图，其中，图4A是示出焊料被提供到每一电子元件侧焊盘30和对应的基板侧焊盘20之间的状态下的侧面剖视图，图4B是示出电子元件3被安装到基板2上之后的状态下的侧面剖视图。在图4A和图4B的例子中，如上述描述的实施例一样，每一强化焊盘33被槽34分开，此外，每一基板侧焊盘20在面向强化焊盘33的槽34的位置也具有槽21。然而，在强化焊盘33的槽34的位置处每一强化焊盘33的厚度是0，即每一强化焊盘33完全被槽34分开；而每一基板侧焊盘20在槽34的位置处(即基板侧焊盘20的槽21的位置)的厚度设置为大于0的预定厚度。注意，每一基板侧焊盘20的槽21设置为朝向基板侧焊盘20面向强化焊盘33的表面进行开口。当焊料被提供到这样配置的强化焊盘33和基板侧焊盘20之间时，没有焊料流到被完全分开的强化焊盘33的槽34的位置；但是焊料流到没有被完全分开的基板侧焊盘20的表面，包括槽21的位置。通过这样做，如图4B所示，在每一强化焊盘33的槽34和对应的基板侧焊盘20的槽21之间形成了V形间隙。这样，与每一强化焊盘33的槽和对应的基板侧焊盘20的槽之间形成具有矩形截面的间隙的状态相比，可以保证电子元件3和基板2之间有足够的焊接面积。
此外，在上述描述的实施例中，没有为每一基板侧焊盘20设置槽，而只是每一强化焊盘33被槽34分开；可替代地，除了每一强化焊盘33(电子元件侧焊盘30)之外，每一基板侧焊盘20也可以被槽21分开。图5是当每一基板侧焊盘20也被槽21分开时电子元件3的平面图。图6是当每一基板侧焊盘20也被槽21分开时基板2的平面图。图7A和图7B是示出每一基板侧焊盘20也被槽21分开的情况下的视图，其中，图7A是示出焊料被提供到每一电子元件侧焊盘30和对应的基板侧焊盘20之间的状态下的侧面剖视图，图7B是示出电子元件3被安装到基板2上之后的状态下的侧面剖视图。注意，图7A显示了图5中示出的电子元件3和图6中示出的基板2的VIIA-VIIA剖视图，图7B显示了图5示出的电子元件3和图6示出的基板2的VIIB-VIIB剖视图。
在图5到图7B所示的例子中，当电子元件3被安装到基板2上时，强化焊盘33和基板侧焊盘20形成为使得每一强化焊盘33的槽34与面向强化焊盘33的对应的基板侧焊盘20的槽21交叉(intersect)。这种情况下，如图7A和图7B所示，除了强化焊盘33的槽34的位置和基板侧焊盘20之间形成的V形间隙部分以及强化焊盘33和基板侧焊盘20的槽21的位置之间形成的V形间隙部分之外，每一强化焊盘33和对应的基板侧焊盘20之间的空间填充有焊料。通过这样做，所产生的空隙中的气体可以经由强化焊盘33的槽34和基板侧焊盘20之间形成的间隙以及基板侧焊盘20的槽21和电子元件侧焊盘30之间形成的间隙从焊接部分释放出来，从而可以在进一步稳定地减少残留空隙同时保证电子元件3和基板2之间有合适的焊接面积。
此外，在上述描述的实施例中，没有为每一基板侧焊盘20设置槽，而只是每一强化焊盘33被槽34分开；可替代地，可以只是面向强化焊盘33的每一基板侧焊盘20被槽分开，而对于每一强化焊盘33可以不设置槽。在这种情况下，所产生的空隙中的气体也可以经由基板侧焊盘20的槽和对应的电子元件侧焊盘30之间形成的间隙从焊接部分释放出来。通过这样做，减少了焊接部分的残留空隙，进而可以稳定地保证电子元件3和基板2之间有合适的焊接面积。
此外，在上述描述的实施例中，为每一强化焊盘33设置了槽34；可替代地，不仅是强化焊盘33，其他每一电子元件侧焊盘30也都可以具有槽。这种情况下，可以为所有的电子元件侧焊盘30设置槽，或者可以只为部分电子元件侧焊盘30设置槽。
此外，在上述描述的实施例中，只为每一强化焊盘33设置了一个槽34；可替代地，可以为每一强化焊盘33设置多个槽34。例如，可以为每一强化焊盘33设置彼此交叉的两个槽34。通过这样做，可以进一步有效地减少焊接部分的残留空隙。
此外，在上述描述的实施例中，在每一强化焊盘33的槽34和对应的基板侧焊盘20之间形成了V形间隙；但是，形成的间隙的形状不限于V形。形成的间隙的形状可以是另外的形状，例如U形。
此外，在上述描述的实施例中，强化焊盘33设置在电子元件3面向基板的表面的每一边角部分；可替代地，强化焊盘33可以设置在面向基板的电子元件3的表面上外围附近的选定位置(例如以预定间隔围绕外围设置)。
此外，在上述描述的实施例中，槽34设置在电子元件侧焊盘30面向基板侧焊盘20的表面上，作为非焊接区域；可替代地，可以在电子元件侧焊盘30面向基板侧焊盘20的表面上设置阻焊层作为非焊接区域。通过这种方式，通过在电子元件侧焊盘30上设置阻焊层，基板侧焊盘20的焊接部分的形状不同于面向基板侧焊盘20的电子元件侧焊盘30的焊接部分的形状。也就是说，考虑到通过焊料连接的焊盘的功能，基板侧焊盘20的形状不同于面向基板侧焊盘20的电子元件侧焊盘30的形状。
例如，在面向基板侧焊盘20的每一强化焊盘33的表面上形成有带状的阻焊层，从而用阻焊层分开强化焊盘33。通过这样做，被阻焊层分开的强化焊盘33的平面形状不同于在面向强化焊盘33的位置处的基板侧焊盘20的平面形状。图8是示出电子元件3被安装到基板2上之后的状态下的侧面剖视图。在这种情况下，当焊料被提供到每一电子元件侧焊盘30和对应的基板侧焊盘20之间时，没有焊料粘附到阻焊层，因而如图8所示，在每一强化焊盘33的阻焊层的位置和对应的基板侧焊盘20之间形成了V形间隙部分。通过这种方式，通过在面向基板侧焊盘20的电子元件侧焊盘30的表面上设置阻焊层作为非焊接区域，可以容易地在电子元件侧焊盘30上形成非焊接区域，并且所产生的空隙中的气体可以经由阻焊层和基板侧焊盘20之间的形成的间隙从焊接部分释放出来。
此外，可以在面向电子元件侧焊盘30的基板侧焊盘20的表面上设置阻焊层。在这种情况下，所产生的空隙中的气体也可以经由阻焊层和电子元件侧焊盘30之间形成的间隙从焊接部分释放出来。

Claims (1)

1.一种待安装到基板上的电子元件，包括：
多个电子元件侧焊盘，其当所述电子元件被安装到所述基板上时分别面向设置在所述基板上的多个基板侧焊盘，其中，
所述多个电子元件侧焊盘包括设置在面向所述基板的所述电子元件表面中心处的接地焊盘，以及围绕所述接地焊盘设置的多个输入/输出焊盘；
所述多个输入/输出焊盘包括强化焊盘，所述强化焊盘设置于面向所述基板的所述电子元件的表面的外围附近，并且形成为面积大于其他的输入/输出焊盘的面积；并且
在面向所述基板侧焊盘的所述强化焊盘的表面上设置有非焊接区域，从而使得所述基板侧焊盘的形状不同于面向所述基板侧焊盘的所述强化焊盘的形状。
CN201110319259.9A 2010-10-27 2011-10-18 电子元件 Expired - Fee Related CN102458048B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010241338A JP5581972B2 (ja) 2010-10-27 2010-10-27 電子部品、及び電子装置
JP2010-241338 2010-10-27

Publications (2)

Publication Number Publication Date
CN102458048A CN102458048A (zh) 2012-05-16
CN102458048B true CN102458048B (zh) 2015-10-21

Family

ID=44785358

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110319259.9A Expired - Fee Related CN102458048B (zh) 2010-10-27 2011-10-18 电子元件

Country Status (4)

Country Link
US (1) US8787033B2 (zh)
EP (1) EP2447994A3 (zh)
JP (1) JP5581972B2 (zh)
CN (1) CN102458048B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITMI20111776A1 (it) * 2011-09-30 2013-03-31 St Microelectronics Srl Sistema elettronico per saldatura a rifusione
DE102012105297A1 (de) * 2012-06-19 2013-12-19 Endress + Hauser Gmbh + Co. Kg Verfahren zum Verbinden eines Bauteils mit einem Träger über eine Lötung und Bauteil zum Verbinden mit einem Träger
JP6504762B2 (ja) 2014-08-05 2019-04-24 キヤノン株式会社 モジュールの製造方法
US10177107B2 (en) * 2016-08-01 2019-01-08 Xilinx, Inc. Heterogeneous ball pattern package
US11830810B2 (en) * 2020-05-07 2023-11-28 Wolfspeed, Inc. Packaged transistor having die attach materials with channels and process of implementing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005223090A (ja) * 2004-02-04 2005-08-18 Murata Mfg Co Ltd 実装基板と部品との接続構造
CN101267714A (zh) * 2007-03-14 2008-09-17 富士通株式会社 电子装置和电子元件安装方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3599326A (en) * 1969-01-27 1971-08-17 Philco Ford Corp Method of forming electrical connections with solder resistant surfaces
JPS607758A (ja) * 1983-06-27 1985-01-16 Nec Corp 半導体装置
JP2859143B2 (ja) 1994-11-08 1999-02-17 松下電器産業株式会社 モジュール部品
US7654432B2 (en) * 1997-05-27 2010-02-02 Wstp, Llc Forming solder balls on substrates
US6169253B1 (en) * 1998-06-08 2001-01-02 Visteon Global Technologies, Inc. Solder resist window configurations for solder paste overprinting
US6267009B1 (en) * 1998-12-14 2001-07-31 Endress + Hauser Gmbh + Co. Capacitive pressure sensor cells or differential pressure sensor cells and methods for manufacturing the same
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
JP2004095867A (ja) * 2002-08-30 2004-03-25 Casio Comput Co Ltd 電子部品
JP2006060141A (ja) * 2004-08-23 2006-03-02 Sharp Corp 印刷基板及びこれを用いた表面実装型半導体パッケージの実装方法
US7892972B2 (en) * 2006-02-03 2011-02-22 Micron Technology, Inc. Methods for fabricating and filling conductive vias and conductive vias so formed
US20080003803A1 (en) * 2006-06-30 2008-01-03 Pei-Haw Tsao Semiconductor package substrate for flip chip packaging
US20080142964A1 (en) * 2006-12-13 2008-06-19 Haixiao Sun Tubular-shaped bumps for integrated circuit devices and methods of fabrication
US20080150101A1 (en) * 2006-12-20 2008-06-26 Tessera, Inc. Microelectronic packages having improved input/output connections and methods therefor
US7667335B2 (en) * 2007-09-20 2010-02-23 Stats Chippac, Ltd. Semiconductor package with passivation island for reducing stress on solder bumps
JP4999806B2 (ja) * 2008-09-18 2012-08-15 アルプス電気株式会社 電子モジュール及びその製造方法
JP5487691B2 (ja) 2009-04-08 2014-05-07 株式会社デンソー 車両制御装置、車両制御プログラム

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005223090A (ja) * 2004-02-04 2005-08-18 Murata Mfg Co Ltd 実装基板と部品との接続構造
CN101267714A (zh) * 2007-03-14 2008-09-17 富士通株式会社 电子装置和电子元件安装方法

Also Published As

Publication number Publication date
EP2447994A3 (en) 2018-01-24
JP2012094712A (ja) 2012-05-17
EP2447994A2 (en) 2012-05-02
US8787033B2 (en) 2014-07-22
CN102458048A (zh) 2012-05-16
US20120106116A1 (en) 2012-05-03
JP5581972B2 (ja) 2014-09-03

Similar Documents

Publication Publication Date Title
US9548159B2 (en) Electronic component
US9082550B2 (en) Electronic component
CN102458048B (zh) 电子元件
CN101336042B (zh) 焊盘、具有该焊盘的电路板和电子装置
JP4653005B2 (ja) 電子部品パッケージ
CN103000591B (zh) 芯片封装件的环结构
WO2007125849A1 (ja) 基板接合部材ならびにそれを用いた三次元接続構造体
US9018741B2 (en) Semiconductor package and manufacturing method thereof
JP6066324B2 (ja) 電子装置
CN110637361B (zh) 电子设备
CN212677451U (zh) 一种装配印刷电路板及电子设备
JP5983228B2 (ja) 回路基板装置、および、電子機器
TWI525782B (zh) 半導體封裝件及其製法
JP4557757B2 (ja) 半導体装置
CN212084994U (zh) 一种并联封装的器件组
CN104681544A (zh) 多芯片qfn封装结构
JP2007180308A (ja) プリント配線基板
CN104183508A (zh) 半导体器件的制作方法
CN221283415U (zh) 电路板组件及电池
CN203521397U (zh) 一种用于元器件组装的pga/bga三维结构
CN102171822A (zh) 锚固引脚引线框架
US12087675B2 (en) Semiconductor device and mounting structure thereof
JP7131624B2 (ja) モジュール
JP2019508908A (ja) はんだボールを備えたパッケージング構造、及びパッケージング構造を製造する方法
JP2009123869A (ja) モジュールとこれを用いた電子機器

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20151021

Termination date: 20201018