CN102388451B - 形成半导体器件的方法 - Google Patents

形成半导体器件的方法 Download PDF

Info

Publication number
CN102388451B
CN102388451B CN201080014774.XA CN201080014774A CN102388451B CN 102388451 B CN102388451 B CN 102388451B CN 201080014774 A CN201080014774 A CN 201080014774A CN 102388451 B CN102388451 B CN 102388451B
Authority
CN
China
Prior art keywords
mask layer
semiconductor region
crystalline semiconductor
region
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201080014774.XA
Other languages
English (en)
Chinese (zh)
Other versions
CN102388451A (zh
Inventor
S·克朗霍尔兹
A·瑙曼
G·比尔宁克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority claimed from PCT/EP2010/000490 external-priority patent/WO2010086152A1/en
Publication of CN102388451A publication Critical patent/CN102388451A/zh
Application granted granted Critical
Publication of CN102388451B publication Critical patent/CN102388451B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144Manufacturing their gate insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151Manufacturing their isolation regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133Manufacturing common source or drain regions between multiple IGFETs

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
CN201080014774.XA 2009-01-30 2010-01-27 形成半导体器件的方法 Active CN102388451B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102009006886.4 2009-01-30
DE102009006886A DE102009006886B4 (de) 2009-01-30 2009-01-30 Verringerung von Dickenschwankungen einer schwellwerteinstellenden Halbleiterlegierung durch Verringern der Strukturierungsungleichmäßigkeiten vor dem Abscheiden der Halbleiterlegierung
US12/693,227 US8361858B2 (en) 2009-01-30 2010-01-25 Reduction of thickness variations of a threshold semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy
US12/693,227 2010-01-25
PCT/EP2010/000490 WO2010086152A1 (en) 2009-01-30 2010-01-27 Reduction of thickness variations of a threshold adjusting semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy

Publications (2)

Publication Number Publication Date
CN102388451A CN102388451A (zh) 2012-03-21
CN102388451B true CN102388451B (zh) 2015-07-15

Family

ID=42338499

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080014774.XA Active CN102388451B (zh) 2009-01-30 2010-01-27 形成半导体器件的方法

Country Status (5)

Country Link
US (2) US8361858B2 (enExample)
JP (1) JP5781944B2 (enExample)
KR (1) KR101587200B1 (enExample)
CN (1) CN102388451B (enExample)
DE (1) DE102009006886B4 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009021489B4 (de) * 2009-05-15 2012-01-12 Globalfoundries Dresden Module One Llc & Co. Kg Erhöhen der Abscheidegleichmäßigkeit für eine zur Schwellwerteinstellung in einem aktiven Gebiet vorgesehene Halbleiterlegierung
DE102009021484B4 (de) * 2009-05-15 2014-01-30 Globalfoundries Dresden Module One Llc & Co. Kg Höhere Gleichmäßigkeit einer Kanalhalbleiterlegierung durch Herstellen von STI-Strukturen nach dem Aufwachsprozess
DE102009046877B4 (de) 2009-06-30 2012-06-21 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Erhöhung der Selektivität während der Herstellung einer Kanalhalbleiterlegierung durch einen nassen Oxidationsprozess
DE102009055394B4 (de) * 2009-12-30 2012-06-14 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren und Halbleiterbauelement mit Erhöhung der Abscheidegleichmäßigkeit für eine Kanalhalbleiterlegierung durch Bilden einer Vertiefung vor der Wannenimplantation
DE102010028459B4 (de) * 2010-04-30 2018-01-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Reduzierte STI-Topographie in Metallgatetransistoren mit großem ε durch Verwendung einer Maske nach Abscheidung einer Kanalhalbleiterlegierung
DE102010040064B4 (de) * 2010-08-31 2012-04-05 Globalfoundries Inc. Verringerte Schwellwertspannungs-Breitenabhängigkeit in Transistoren, die Metallgateelektrodenstrukturen mit großem ε aufweisen
DE102010063296B4 (de) * 2010-12-16 2012-08-16 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Herstellungsverfahren mit reduzierter STI-Topograpie für Halbleiterbauelemente mit einer Kanalhalbleiterlegierung
DE102011005639B4 (de) 2011-03-16 2016-05-25 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Reduzieren der Defektrate während des Abscheidens einer Kanalhalbleiterlegierung in ein in-situ-abgesenktes aktives Gebiet
DE102011076695B4 (de) * 2011-05-30 2013-05-08 Globalfoundries Inc. Transistoren mit eingebettetem verformungsinduzierenden Material, das in durch einen Oxidationsätzprozess erzeugten Aussparungen ausgebildet ist
US8508001B2 (en) 2011-08-25 2013-08-13 Globalfoundries Inc. Semiconductor device with work function adjusting layer having varied thickness in a gate width direction and methods of making same
US8377773B1 (en) 2011-10-31 2013-02-19 Globalfoundries Inc. Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask
KR102277398B1 (ko) * 2014-09-17 2021-07-16 삼성전자주식회사 반도체 소자 및 이의 제조 방법
KR102707542B1 (ko) * 2016-12-02 2024-09-20 삼성전자주식회사 반도체 메모리 소자 및 그 제조 방법
US10141430B1 (en) * 2017-07-27 2018-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structures with uniform threshold voltage distribution and method of making the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5595526A (en) * 1994-11-30 1997-01-21 Intel Corporation Method and apparatus for endpoint detection in a chemical/mechanical process for polishing a substrate
US6180978B1 (en) 1997-12-30 2001-01-30 Texas Instruments Incorporated Disposable gate/replacement gate MOSFETs for sub-0.1 micron gate length and ultra-shallow junctions
US6617226B1 (en) * 1999-06-30 2003-09-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2001338988A (ja) * 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
KR100398041B1 (ko) * 2000-06-30 2003-09-19 주식회사 하이닉스반도체 반도체 소자의 에피 채널 형성 방법
US6762469B2 (en) * 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
JP2004266064A (ja) * 2003-02-28 2004-09-24 Seiko Epson Corp 半導体装置及びその製造方法
US7381690B1 (en) * 2003-09-25 2008-06-03 Ppt Research Inc Stable aqueous slurry suspensions
US6995456B2 (en) * 2004-03-12 2006-02-07 International Business Machines Corporation High-performance CMOS SOI devices on hybrid crystal-oriented substrates
JP4836416B2 (ja) * 2004-07-05 2011-12-14 富士通セミコンダクター株式会社 半導体装置の製造方法
US7439139B2 (en) * 2004-09-13 2008-10-21 Seliskar John J Fully-depleted castellated gate MOSFET device and method of manufacture thereof
US20060105533A1 (en) * 2004-11-16 2006-05-18 Chong Yung F Method for engineering hybrid orientation/material semiconductor substrate
US7816236B2 (en) 2005-02-04 2010-10-19 Asm America Inc. Selective deposition of silicon-containing films
EP1911086A2 (en) * 2005-07-26 2008-04-16 Amberwave Systems Corporation Solutions integrated circuit integration of alternative active area materials
US7696574B2 (en) * 2005-10-26 2010-04-13 International Business Machines Corporation Semiconductor substrate with multiple crystallographic orientations
AU2006340825A1 (en) * 2005-11-09 2007-10-04 Advanced Technology Materials, Inc. Composition and method for recycling semiconductor wafers having low-k dielectric materials thereon
DE102006035669B4 (de) * 2006-07-31 2014-07-10 Globalfoundries Inc. Transistor mit einem verformten Kanalgebiet, das eine leistungssteigernde Materialzusammensetzung aufweist und Verfahren zur Herstellung
KR100809327B1 (ko) * 2006-08-10 2008-03-05 삼성전자주식회사 반도체 소자 및 그 제조방법
DE102006051492B4 (de) * 2006-10-31 2011-05-19 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit NMOS- und PMOS-Transistoren mit eingebettetem Si/Ge-Material zum Erzeugen einer Zugverformung und einer Druckverformung und Verfahren zur Herstellung eines solchen Halbleiterbauelements
KR101378987B1 (ko) * 2006-10-31 2014-03-28 어드밴스드 마이크로 디바이시즈, 인코포레이티드 인장성 스트레인 및 압축성 스트레인을 생성시키기 위한 임베드된 Si/Ge 물질을 갖는 NMOS 및 PMOS 트랜지스터를 포함하는 반도체 디바이스
US20080237634A1 (en) * 2007-03-30 2008-10-02 International Business Machines Corporation Crystallographic recess etch for embedded semiconductor region
US7687862B2 (en) * 2008-05-13 2010-03-30 Infineon Technologies Ag Semiconductor devices with active regions of different heights
DE102008063402B4 (de) * 2008-12-31 2013-10-17 Advanced Micro Devices, Inc. Verringerung der Schwellwertspannungsfluktuation in Transistoren mit einer Kanalhalbleiterlegierung durch Verringern der Abscheideungleichmäßigkeiten

Also Published As

Publication number Publication date
CN102388451A (zh) 2012-03-21
DE102009006886A1 (de) 2010-08-19
JP5781944B2 (ja) 2015-09-24
JP2012516555A (ja) 2012-07-19
DE102009006886B4 (de) 2012-12-06
KR101587200B1 (ko) 2016-02-02
US8361858B2 (en) 2013-01-29
KR20110113647A (ko) 2011-10-17
US20100193881A1 (en) 2010-08-05
US20130161695A1 (en) 2013-06-27

Similar Documents

Publication Publication Date Title
CN102388451B (zh) 形成半导体器件的方法
US8188551B2 (en) Semiconductor devices and methods of manufacture thereof
US8637357B2 (en) CMOS Transistor with dual high-k gate dielectric and method of manufacture thereof
US8343837B2 (en) Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum
CN102446729B (zh) 用湿式化学方法形成受控底切而有优异完整性的高介电系数栅极堆栈
US7253050B2 (en) Transistor device and method of manufacture thereof
US20110159654A1 (en) Enhanced confinement of high-k metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy
US7160781B2 (en) Transistor device and methods of manufacture thereof
CN102543707B (zh) 通过用基于等离子的掩膜图案化工艺形成沟道半导体合金
JP5669752B2 (ja) チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減
EP1760777A2 (en) Transistors and methods of manufacture thereof
US20080050898A1 (en) Semiconductor devices and methods of manufacture thereof
WO2010086152A1 (en) Reduction of thickness variations of a threshold adjusting semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy
JP2007294811A (ja) 半導体集積回路及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant