CN102362345A - 半导体元件基板及其制造方法、半导体器件 - Google Patents

半导体元件基板及其制造方法、半导体器件 Download PDF

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CN102362345A
CN102362345A CN201080012985XA CN201080012985A CN102362345A CN 102362345 A CN102362345 A CN 102362345A CN 201080012985X A CN201080012985X A CN 201080012985XA CN 201080012985 A CN201080012985 A CN 201080012985A CN 102362345 A CN102362345 A CN 102362345A
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semiconductor element
metallic plate
outer frame
slit
element substrate
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CN102362345B (zh
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户田顺子
马庭进
塚本健人
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Toppan Inc
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Toppan Printing Co Ltd
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Abstract

半导体元件基板的制造方法，包括：形成第一光致抗蚀剂图案的工序，所述第一光致抗蚀剂图案用于在金属板的第一面上形成半导体元件装载部、半导体元件电极连接端子、配线、外框部及狭缝；形成第二光致抗蚀剂图案的工序，所述第二光致抗蚀剂图案用于在所述金属板的所述第二面上形成外部连接端子、所述外框部及所述狭缝；以使作为所述金属板的一部分的所述金属片和所述外框部的四角相连接的方式，通过半蚀刻形成所述狭缝的工序；在所述金属板的所述第二面上形成多个凹部的工序；以不进入所述狭缝的方式向所述多个凹部注入树脂并使该树脂固化的工序；对所述金属板的所述第一面进行蚀刻，来形成所述半导体元件装载部、与所述外部连接端子电连接的所述半导体元件电极连接端子及所述外框部的工序。

Description

半导体元件基板及其制造方法、半导体器件
技术领域
本发明涉及适合安装半导体元件的半导体封装基板的技术，尤其涉及半导体元件基板、半导体元件基板的制造方法及使用了半导体元件基板的半导体器件。
本申请基于在2009年3月25日在日本申请的特愿2009-075139号来主张优先权，在这里引用该内容。
背景技术
在使用了以QFP(Quad Flat Package：方形扁平封装)为代表的引线框的半导体封装中，用于与印刷电路布线基板连接的外部引线配置在半导体封装的侧面。对于引线框，在金属板的两面形成有所希望的光致抗蚀剂图案，并从两面进行蚀刻来形成。由此，能够得到半导体元件装载部、与半导体元件电极连接的连接部即内部引线、外部引线和固定它们的外框部。
此外，除蚀刻方法以外，也可以利用通过冲压(press)的冲裁加工来得到引线框。作为半导体封装的装配工序，将半导体元件与半导体元件装载部芯片键合(die bonding)后，利用金线等将半导体元件的电极与内部引线电连接。之后，对包括内部引线部在内的半导体元件附近进行树脂封固，裁切外框部，并根据需要，对外部引线实施弯曲加工。
这样，就这样设置于侧面的外部引线而言，从微细加工能力来看，针对约30mm见方的封装尺寸所能够设置的管脚数上限为200个至300个。
近年来，随着半导体元件的电极数的增加，在侧面具有外部引线的引线框型的半导体封装已经无法满足对端子数的要求，所以一部分搬到封装被置换为BGA(Ball Grid Aray：球栅阵列)或LGA(Land Grid Aray：栅格阵列)型等与印刷电路布线基板连接的外部连接端子在封装基板底面配置成阵列状的半导体封装。通常，对于在半导体封装使用的基板，在两面覆铜的玻璃环氧基板上用钻头(drill)开孔，并对孔内进行电镀来取得导通，并在一个面形成用于与半导体元件的电极相连接的端子，在另一面形成排列成阵列状的外部连接端子。
然而，这些基板的制造工序复杂，使成本变高，并且在基板内的配线连接上使用电镀法，因此与引线框型的封装相比，存在可靠性差的问题。
因此，公开了使用了引线框的BGA型的半导体封装结构，其利用从两面对引线框进行蚀刻的工序(例如参照专利文献1)。
其是如下半导体封装结构：改变正反面的光致抗蚀剂的图案，并同时进行蚀刻，或者，对一侧进行蚀刻之后，在蚀刻面表层上形成电沉积聚酰亚胺树脂层或涂敷预成型树脂，之后从另一个面实施蚀刻，由此，在一个面形成半导体元件电极的连接端子，在另一个面形成阵列状的外部连接端子。
在图11及图12中示出了现有的半导体元件基板。半导体元件基板包括：配线110、外部连接端子111、外框部112、聚酰亚胺树脂层116、半导体元件装载部118和半导体元件电极连接端子119。如图11及图12所示，在BGA型的引线框中，若增加外部连接端子111的个数，则半导体元件电极的连接端子119的配线110的长度会变长。该配线110是对金属板进行半蚀刻(half etching)来制作的，因此其宽度和厚度都较小，存在在蚀刻以后的工序中发生折断或弯曲，成品率非常差的问题。
在专利文献1中公开了以下内容：首先，仅对外部连接端子111侧进行半蚀刻，在蚀刻面上形成电沉积聚酰亚胺层后，对半导体元件电极连接端子119侧进行蚀刻。由此，微细的配线110虽然为薄膜，但由聚酰亚胺树脂层116来支撑，避免了制作引线框时的配线的折断或弯曲。
然而，在该结构的半导体元件基板上装载半导体元件，并利用引线键合来连接半导体元件电极和连接端子119时，由于连接端子119的下部为中空的，所以用于连接引线的作用力未起到作用，存在发生连接不良，装配成品率显著下降的问题。
在专利文献1中推断：通过填充预成型树脂来取代电沉积聚酰亚胺层，能够一定程度地避免键合不良的问题。但是，会发生下述问题：在凹部中填充的预成型树脂固化时，树脂收缩，由于树脂和外框部的紧贴力小于树脂的收缩力，所以产生了剥离。
现有技术文献
专利文献
专利文献1：日本国特许第3642911号公报。
发明内容
发明要解决的问题
本发明提供一种能够应对半导体元件的电极数的增加、可靠性变高并稳定地进行制作及半导体封装装配的半导体元件基板、半导体元件基板的制造方法及半导体器件。
用于解决问题的手段
本发明第一方式是一种半导体元件基板的制造方法，包括：形成第一光致抗蚀剂图案的工序，所述第一光致抗蚀剂图案用于在金属板的第一面上形成半导体元件装载部、半导体元件电极连接端子、配线、外框部及狭缝，所述狭缝以使所述外框部的四角和作为所述金属板的一部分的金属片相连接的方式贯通所述金属板的所述第一面和与所述第一面不同的第二面；形成第二光致抗蚀剂图案的工序，所述第二光致抗蚀剂图案用于在所述金属板的所述第二面上形成外部连接端子、所述外框部及所述狭缝；以使所述金属片和所述外框部的四角相连接的方式通过半蚀刻形成所述狭缝的工序；在所述金属板的所述第二面上形成多个凹部的工序；以不进入所述狭缝的方式向所述多个凹部注入树脂并使该树脂固化的工序；对所述金属板的所述第一面进行蚀刻，来形成所述半导体元件装载部、与所述外部连接端子电连接的所述半导体元件电极连接端子及所述外框部的工序。
本发明的第二方式是一种半导体元件基板，具有：金属板；半导体元件装载部，形成于所述金属板的第一面上；连接端子，形成于所述金属板的所述第一面上，用于与半导体元件电极相连接；配线，形成于所述金属板的所述第一面上；外框部，形成于所述金属板上；连接片，使所述外框部的四角和作为所述金属板的一部分的金属片相连接；外部连接端子，形成于所述金属板的与所述第一面不同的第二面上；多个凹部，形成于所述金属板的所述第二面上；树脂层，填充于所述多个凹部中。
本发明的第三方式是一种半导体器件，具有：半导体元件基板，该半导体元件基板具有：金属板，半导体元件装载部，形成于所述金属板的第一面上，连接端子，形成于所述金属板的所述第一面上，用于与半导体元件电极相连接，配线，形成于所述金属板的所述第一面上，外框部，形成于所述金属板上，连接片，使所述外框部的四角和作为所述金属板的一部分的金属片相连接，外部连接端子，形成于所述金属板的与所述第一面不同的第二面，多个凹部，形成于所述金属板的所述第二面上，树脂层，填充于所述多个凹部中；半导体元件，装载于所述半导体元件基板的所述半导体元件装载部上，并与所述半导体元件基板电连接。
发明效果
根据本发明，能够将用于与印刷电路布线基板连接的外部连接端子阵列状地配置在半导体元件基板的整个背面上，从而能够对应半导体元件的多端子化。
此外，根据本发明，使用以引线框作为基础的基板并且未使用电镀配线，因此能够确保对热应力的可靠性。进而根据本发明，在制作该基板时，不会发生配线的折断或弯曲等不良，在进行半导体封装装配工序即引线键合时，由于设置了狭缝，从而在凹部填充预成型树脂后，缓和固化时发生的预成型树脂的应力，能够防止预成型树脂从金属板上剥离。
因此，根据本发明，随着半导体元件的电极数的增加，从而可靠性提高并能够稳定地进行制作及半导体封装装配。
附图说明
图1是用于说明本发明的第一实施方式的半导体元件基板的制造方法的工序的概略剖面图。
图2是用于说明本发明的第一实施方式的半导体元件基板的制造方法的工序的概略剖面图。
图3是用于说明本发明的第一实施方式的半导体元件基板的制造方法的工序的概略剖面图。
图4是用于说明本发明的第一实施方式的半导体元件基板的制造方法的工序的概略剖面图。
图5是用于说明本发明的第一实施方式的半导体元件基板的制造方法的工序的概略剖面图。
图6是用于说明本发明的第一实施方式的半导体元件基板的制造方法的工序的概略剖面图。
图7是表示本发明的第一实施方式的半导体元件基板的一部分的局部剖切俯视图。
图8是表示本发明的第一实施方式的半导体元件基板的其他部分的局部剖切俯视图。
图9是用于说明本发明的第二实施方式的半导体器件的制造方法的工序的概略剖面图。
图10是用于说明本发明的第二实施方式的半导体器件的制造方法的其他工序的概略剖面图。
图11是用于说明现有的半导体元件基板的制造方法的工序的概略剖面图。
图12是用于说明现有的半导体元件基板的制造方法的工序的概略剖面图。
具体实施方式
接下来，参照附图对本发明的实施方式进行详细说明。
(第一实施方式)
图1～图6是用于说明本发明的第一实施方式的半导体元件基板的制造方法的工序的概略剖面图。
如图1及图2所示，在用作引线框的金属板1的上表面上形成有光致抗蚀剂的第一光致抗蚀剂图案2a，在金属板1的下表面上形成有第二光致抗蚀剂图案2b。金属板1的上表面的第一光致抗蚀剂图案2a用于在金属板1的上表面上形成半导体元件装载部8、半导体元件电极连接端子9、配线10、外框部5及狭缝4(参照图6)。虽然狭缝4贯通到金属板1的下表面，但是，外框部5的周围和金属片17之间至少在该外框部5的四角相连接。
金属板1的下表面的第二光致抗蚀剂图案2b用于在金属板1的下表面上形成外部连接端子11、外框部5及狭缝4(参照图6)。虽然狭缝4贯通到金属板1的上表面，但是，外框部5的周围和金属片17之间至少在该外框部5的四角相连接。
作为金属板1，只要具有作为引线框的蚀刻加工性、机械的强度、热传导性、膨胀系数等即可，可以使用任意的材料，但是，优选使用以代表42合金为代表的铁-镍类合金，或为了提高机械强度而添加了各种金属元素的铜类合金等。
接着，利用氯化铁溶液等溶解金属板1的蚀刻液，从金属板1的下表面开始进行蚀刻来形成凹部3(参照图3)。关于凹部3的深度，由于金属板1的残存部分最终会成为配线，所以优选残留约10μm到50μm的厚度，以便在接下来从上表面侧进行蚀刻时能够形成微细的配线。
接着，为了不使凹部3贯通而用覆盖膜覆盖之后，从上表面侧进行蚀刻，以在外框部5形成狭缝4(参照图3)。通过在该外框部5形成狭缝4，在外框部5上形成有至少使该外框部5的四角和该外框部5的金属片17相连接的连接片(参照图7及图8)。
接着，将蚀刻加工过的金属板1的上下表面翻转过来，并向金属板1的上表面以不进入狭缝4的方式注入液态的预成型树脂而形成树脂层6(参照图4)。
通过在外框部5的周围设置狭缝4，能够缓和填充于凹部3的由预成型树脂形成的树脂层6固化时发生的应力，从而能够防止树脂层6从金属板1剥离。
进而，再使金属板1的上下表面翻转过来返回原来状态后，对金属板1的上表面进行蚀刻，形成半导体装载部8、半导体元件电极连接端子9、配线10，从而制作出半导体元件基板7(参照图5及图6)。
图7是表示本发明的第一实施方式的半导体元件基板的一部分的局部剖切俯视图。图8是表示本发明的第一实施方式的半导体元件基板的其他部分的局部剖切俯视图。如图7及图8所示，能够将外部连接端子11配置成阵列状，从而能够对应半导体元件的多管脚化。此外，通过形成狭缝4，形成为外框部5的至少四角通过连接片18与金属片17相连接的状态。
(第二实施方式)
接下来，参照附图对本发明的第二实施方式进行说明。图9是用于说明本发明的第二实施方式的半导体器件的制造方法的工序的概略剖面图。图10是用于说明本发明的第二实施方式的半导体器件的制造方法的工序的概略剖面图。在本发明的第二实施方式中，对与本发明的第一实施方式相同的结构要素标注相同的附图标记并省略该说明。
如图9所示，在半导体元件基板7的半导体元件装载部8之上借助芯片粘贴材料(die attach stuff)14装载有半导体元件12，半导体元件12用金线13与半导体元件电极连接端子9连接。根据需要，在半导体元件电极连接端子9上施加镍-金电镀、锡电镀、银电镀或者镍-钯-金电镀。进行引线键合时，在加热块之上装载该引线框型的半导体元件基板7，一边加热一边接合，由于树脂层6以与半导体元件电极连接端子9形成同一个面的方式存在于该半导体元件电极连接端子9的下部且难于形成中空结构，因此能够在不引起接合不良的情况下进行装配。
最后，如图10所示，通过传递成型(transfer molding)或者浇注(potting)对半导体元件基板7的一侧进行封固，并用金刚石刀片(diamond blade)等来分离外框部5，实现小片化。若为BGA型，则在外部连接端子11上装载焊锡球，从而可以得到使用了半导体元件基板7的半导体器件(半导体封装)。
(实施例1)
接下来，参照附图对本发明的实施例1进行详细说明。本发明的实施例1是关于制造LGA型的半导体元件基板的一个例子。
所制造的LGA的封装尺寸为10mm见方，并在封装的下表面具有168管脚的阵列状的外部连接端子11。
首先，如图1所示，准备宽度为150mm厚度为200μm的长带状的铜合金制的金属板1(古河电工制造，EFTEC64T)。接着，如图2所示，在该金属板1的两面，用辊涂机涂敷光致抗蚀剂(东京应化(株式会社)制造，OFPR4000)使该光致抗蚀剂达到5μm的厚度后，在90℃下预烘十。
接着，经由具有所希望的图案的光掩模，从两面进行图案曝光，之后，用1％碳酸钠溶液进行显影处理之后，进行水洗及后烘干，从而得到了图2所示的第一光致抗蚀剂图案2a及第二光致抗蚀剂图案2b。
金属板1的上表面(第一面)的第一光致抗蚀剂图案2a，用于形成半导体元件装载部8、与半导体元件电极连接的连接端子9、配线10、外框部5及狭缝4(参照图6)。虽然狭缝4贯通到金属板1的第二面，但是，外框部5的周围和金属片17之间至少在该外框部5的四角连接。
金属板1的下表面(第二面)的第二光致抗蚀剂图案2b用于在金属板1的第二面形成外部连接端子11、外框部5及狭缝4(参照图6)。虽然狭缝4贯通到金属板1的第一面，但是外框部5的周围和金属片17至少在该外框部5的四角连接。
接着，用背板(back sheet)覆盖金属板1的第一面来进行保护(未图示)之后，使用氯化铁溶液从金属板的第二面进行第一次的蚀刻处理，使第二面侧的从光致抗蚀剂图案2b露出的金属板1的部位薄到厚度为30μm为止，从而形成了凹部3(参照图3)。设氯化铁溶液的比重在液体温度50℃下为1.38。
接着，为了不使凹部3贯通而用覆盖膜进行保护之后(未图示)，使用氯化铁溶液进行第二次的蚀刻处理，而形成了贯通到第一面的狭缝4(参照图3)。氯化铁溶液的比重在液体温度50℃下为1.38。
接着，将对第二面蚀刻后的金属板1浸渍在30℃、50g/L的过硫酸铵溶液中5分钟，使在第一次及第二次的蚀刻中所形成的蚀刻面的表面粗糙化(未图示)。进而，将金属板1浸渍在规定的氢氧化钠溶液类的剥离液中，剥离第二面的光致抗蚀剂(未图示)。
接着，在第一次及第二次的蚀刻中所形成的金属板1的第二面上，以不进入狭缝4的方式，注入液态的热固化性的树脂(信越化学工业制造SMC-376KF1)，在180℃下进行3小时的固化，从而形成树脂层6(参照图4)。
热固化树脂即树脂层6的埋入性良好，因此观察不到空隙等的不良。在外部连接端子11和外框部5的未被蚀刻的表面上，几乎没有残存热固化树脂即树脂层6，但是也兼顾清洗该表面，在60℃的高锰酸钾的碱性溶液(40g/L高锰酸钾+20g/L氢氧化钠)中进行了约3分钟的浸渍处理。
接着，除去金属板1的第一面的背板后，利用氯化铁溶液从金属板1的第一面侧实施第三次的蚀刻处理，来溶解除去从光致抗蚀剂图案2a露出的金属板1的部位，从而形成半导体元件装载部8、半导体元件电极连接端子9和配线10(参照图5)。外部连接端子11从半导体元件电极连接端子9延伸。此外虽然未图示，但是为了不在金属板1的第二面侧进行不需要的蚀刻，优选在进行第三次的蚀刻处理时，在金属板1的第二面贴附背板等。
接着，对金属板1的第一面的光致抗蚀剂图案2a进行剥离，从而得到所希望的引线框型LGA基板即半导体元件基板7(参照图6)。
接着，剥离光致抗蚀剂图案2a、2b之后，对于露出的金属板1的表面，实施电解镍-金电镀。镍的厚度为5μm，金的厚度为0.1μm(未图示)。
接着，在引线框型LGA基板即半导体元件基板7上使用芯片粘贴材料14装载半导体元件12，在150℃下使芯片粘贴材料14固化1小时。进而，使用直径30μm的金线，通过引线键合连接半导体元件12的电极和半导体元件电极的连接端子9(参照图9)。引线键合的加热温度为200℃，测定半导体元件电极的连接端子9侧的电线的拉力强度，结果为9g以上，得到良好的连接。
之后，如图10所示，通过传递成型树脂15来封固包含半导体元件12和半导体元件电极的连接端子9在内的区域，并裁断成小片，得到使用了半导体元件基板7的半导体器件(半导体封装)。
本发明能够减少制造时的不良及半导体封装装配时的不良，从而能够得到提高对热应力的可靠性的引线框型基板，尤其适用于引线框型的半导体封装不能对应的多管脚封装基板。
以上，虽然已说明并例示了本发明的优选的实施例，但这些只不过是本发明的例示，而不应该理解为对本发明的限定。能够在不超出本发明的范围进行追加、削除、置换及其他的变更。即，本发明并不由之前所述的实施例限定，而是由权利要求来限定。
产业上的可利用性
根据本发明，能够将与印刷电路布线基板连接的外部连接端子呈阵列状地配置在半导体元件基板的整个背面上，从而能够对应半导体元件的多端子化。
此外，在本发明中，采用以引线框作为基础的基板并且未使用电镀配线，因此能够确保对热应力的可靠性。进而，根据本发明，在制作该基板时，不会发生配线的折断或弯曲等不良，在半导体封装装配工序即引线键合时，由于设置了狭缝，所以在凹部填充预成型树脂后，缓和固化时发生的预成型树脂的应力，能够防止预成型树脂从金属板剥离。
因此，若采用本发明，则能够应对半导体元件的电极数的增加，可靠性提高，并能够稳定地进行制作及半导体封装装配。
附图标记说明
1金属板
2a第一光致抗蚀剂图案
2b第二光致抗蚀剂图案
3凹部
4狭缝
5外框部
6树脂层
7半导体元件基板
8半导体元件装载部
9半导体元件电极连接端子
10配线
11外部连接端子
12半导体元件
13金线
14芯片粘贴材料
15传递成型树脂
16电沉积聚酰亚胺层
17金属片
18连接片
110配线
111外部连接端子
112外框部
116聚酰亚胺树脂层
118半导体元件装载部
119半导体元件电极连接端子

Claims (3)

1.一种半导体元件基板的制造方法，其特征在于，包括：
形成第一光致抗蚀剂图案的工序，所述第一光致抗蚀剂图案用于在金属板的第一面上形成半导体元件装载部、半导体元件电极连接端子、配线、外框部及狭缝，所述狭缝以使所述外框部的四角和作为所述金属板的一部分的金属片相连接的方式贯通所述金属板的所述第一面和与所述第一面不同的第二面；
形成第二光致抗蚀剂图案的工序，所述第二光致抗蚀剂图案用于在所述金属板的所述第二面上形成外部连接端子、所述外框部及所述狭缝；
以使所述金属片和所述外框部的四角相连接的方式，通过半蚀刻形成所述狭缝的工序；
在所述金属板的所述第二面上形成多个凹部的工序；
以不进入所述狭缝的方式向所述多个凹部注入树脂并使该树脂固化的工序；
对所述金属板的所述第一面进行蚀刻，来形成所述半导体元件装载部、与所述外部连接端子电连接的所述半导体元件电极连接端子及所述外框部的工序。
2.一种半导体元件基板，其特征在于，具有：
金属板，包含第一面和与所述第一面不同的第二面；
半导体元件装载部，形成于所述金属板的所述第一面上；
连接端子，形成于所述金属板的所述第一面上，用于与半导体元件电极相连接；
配线，形成于所述金属板的所述第一面上；
外框部，形成于所述金属板上；
连接片，使所述外框部的四角和作为所述金属板的一部分的金属片相连接；
外部连接端子，形成于所述金属板的所述第二面上；
多个凹部，形成于所述金属板的所述第二面上；
树脂层，填充于所述多个凹部中。
3.一种半导体器件，其特征在于，具有：
半导体元件基板，该半导体元件基板具有：
金属板，包含第一面和与所述第一面不同的第二面，
半导体元件装载部，形成于所述金属板的所述第一面上，
连接端子，形成于所述金属板的所述第一面上，用于与半导体元件电极相连接，
配线，形成于所述金属板的所述第一面上，
外框部，形成于所述金属板上，
连接片，使所述外框部的四角和作为所述金属板的一部分的金属片相连接，
外部连接端子，形成于所述金属板的所述第二面上，
多个凹部，形成于所述金属板的所述第二面上，
树脂层，填充于所述多个凹部中；
半导体元件，装载于所述半导体元件基板的所述半导体元件装载部上，并与所述半导体元件基板电连接。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104766832A (zh) * 2014-01-03 2015-07-08 海成帝爱斯株式会社 制造半导体封装基板的方法及用其制造的半导体封装基板
CN106409696A (zh) * 2016-10-24 2017-02-15 上海凯虹科技电子有限公司 封装方法及封装体
CN113774381A (zh) * 2020-08-28 2021-12-10 株式会社万代 金属部件的制造方法和金属薄片

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404524B2 (en) * 2010-09-16 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with paddle molding and method of manufacture thereof
CN102324413B (zh) * 2011-09-13 2013-03-06 江苏长电科技股份有限公司 有基岛预填塑封料先刻后镀引线框结构及其生产方法
KR101478509B1 (ko) 2013-06-27 2015-01-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조용 원 레이어 기판 제조 방법
CN103413766B (zh) * 2013-08-06 2016-08-10 江阴芯智联电子科技有限公司 先蚀后封芯片正装三维系统级金属线路板结构及工艺方法
CN103400771B (zh) * 2013-08-06 2016-06-29 江阴芯智联电子科技有限公司 先蚀后封芯片倒装三维系统级金属线路板结构及工艺方法
CN103456645B (zh) * 2013-08-06 2016-06-01 江阴芯智联电子科技有限公司 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法
KR102130757B1 (ko) * 2014-01-03 2020-07-08 해성디에스 주식회사 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판
KR102111730B1 (ko) * 2014-01-03 2020-05-15 해성디에스 주식회사 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판
KR101686349B1 (ko) * 2015-10-19 2016-12-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그의 제조 방법
JP6537144B2 (ja) * 2016-03-16 2019-07-03 大口マテリアル株式会社 多列型リードフレーム及びその製造方法
US9595455B1 (en) * 2016-06-09 2017-03-14 Nxp B.V. Integrated circuit module with filled contact gaps
US11244876B2 (en) 2019-10-09 2022-02-08 Microchip Technology Inc. Packaged semiconductor die with micro-cavity

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09307043A (ja) * 1996-05-10 1997-11-28 Dainippon Printing Co Ltd リードフレーム部材とその製造方法、および該リードフレーム部材を用いた半導体装置
US20020079563A1 (en) * 2000-12-25 2002-06-27 Yoshihiko Shimanuki Semiconductor device and method of manufacturing the same
US20030189222A1 (en) * 2002-04-01 2003-10-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273250A (ja) * 1994-03-31 1995-10-20 Hitachi Ltd 半導体装置
JP3612155B2 (ja) * 1996-11-20 2005-01-19 株式会社日立製作所 半導体装置および半導体装置用のリードフレーム
JP3642911B2 (ja) * 1997-02-05 2005-04-27 大日本印刷株式会社 リードフレーム部材とその製造方法
US20040080025A1 (en) * 2002-09-17 2004-04-29 Shinko Electric Industries Co., Ltd. Lead frame, method of manufacturing the same, and semiconductor device manufactured with the same
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabricating method thereof
KR101297645B1 (ko) * 2005-06-30 2013-08-20 페어차일드 세미컨덕터 코포레이션 반도체 다이 패키지 및 그의 제조 방법
US8063470B1 (en) * 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09307043A (ja) * 1996-05-10 1997-11-28 Dainippon Printing Co Ltd リードフレーム部材とその製造方法、および該リードフレーム部材を用いた半導体装置
US20020079563A1 (en) * 2000-12-25 2002-06-27 Yoshihiko Shimanuki Semiconductor device and method of manufacturing the same
US20030189222A1 (en) * 2002-04-01 2003-10-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104766832A (zh) * 2014-01-03 2015-07-08 海成帝爱斯株式会社 制造半导体封装基板的方法及用其制造的半导体封装基板
CN104766832B (zh) * 2014-01-03 2020-07-14 海成帝爱斯株式会社 制造半导体封装基板的方法及用其制造的半导体封装基板
CN106409696A (zh) * 2016-10-24 2017-02-15 上海凯虹科技电子有限公司 封装方法及封装体
CN113774381A (zh) * 2020-08-28 2021-12-10 株式会社万代 金属部件的制造方法和金属薄片

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