CN102347264B - 半导体器件生产用膜、半导体器件生产用膜的生产方法和半导体器件的生产方法 - Google Patents

半导体器件生产用膜、半导体器件生产用膜的生产方法和半导体器件的生产方法 Download PDF

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CN102347264B
CN102347264B CN201110185003.3A CN201110185003A CN102347264B CN 102347264 B CN102347264 B CN 102347264B CN 201110185003 A CN201110185003 A CN 201110185003A CN 102347264 B CN102347264 B CN 102347264B
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film
isolating membrane
cutting belt
semiconductor device
adhesive phase
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CN102347264A (zh
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高本尚英
志贺豪士
浅井文辉
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Nitto Denko Corp
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Nitto Denko Corp
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    • C09J7/20—Adhesives in the form of films or foils characterised by their carriers
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    • B32B37/1284—Application of adhesive
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    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00—Ancillary operations in connection with laminating processes
    • B32B38/0004—Cutting, tearing or severing, e.g. bursting; Cutter details
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B32B38/00—Ancillary operations in connection with laminating processes
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    • B32B2405/00—Adhesive articles, e.g. adhesive tapes
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    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • B32B2457/14—Semiconductor wafers
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    • C09J2301/302—Additional features of adhesives in the form of films or foils characterized by the chemical, physicochemical or physical properties of the adhesive or the carrier the adhesive being pressure-sensitive, i.e. tacky at temperatures inferior to 30°C
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    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/14—Layer or component removable to expose adhesive
    • Y10T428/1471—Protective layer
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    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
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    • Y10T428/1476—Release layer
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
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Abstract

本发明涉及半导体器件生产用膜、半导体器件生产用膜的生产方法和半导体器件的生产方法。本发明涉及半导体器件生产用膜，其包括：隔离膜；和多个粘贴粘合剂层的切割带，所述多个粘贴粘合剂层的切割带各自包括切割带和层压在切割带上的粘合剂层，所述粘贴粘合剂层的切割带以粘合剂层粘贴至隔离膜的方式以预定间隔层压在隔离膜上，其中所述隔离膜具有沿切割带的外周形成的切口，和切口的深度为不超过所述隔离膜厚度的2/3。

Description

半导体器件生产用膜、半导体器件生产用膜的生产方法和半 导体器件的生产方法
技术领域
本发明涉及半导体器件生产用膜、半导体器件生产用膜的生产方法和半导体器件的生产方法。
背景技术
近年来，日益要求半导体器件及其封装的薄型化和小型化。因此，作为半导体器件及其封装，已经广泛地利用其中将半导体元件如半导体芯片通过倒装芯片接合(倒装芯片连接的)安装至基板上的倒装芯片型半导体器件。在此类倒装芯片连接中，半导体芯片以其中半导体芯片的电路面与基板的电极形成面相对的形式固定至基板。在这类半导体器件等中，存在其中半导体芯片的背面受保护膜保护以防止半导体芯片损坏等的情况(参见专利文献1至10)。
专利文献1：JP-A-2008-166451
专利文献2：JP-A-2008-006386
专利文献3：JP-A-2007-261035
专利文献4：JP-A-2007-250970
专利文献5：JP-A-2007-158026
专利文献6：JP-A-2004-221169
专利文献7：JP-A-2004-214288
专利文献8：JP-A-2004-142430
专利文献9：JP-A-2004-072108
专利文献10：JP-A-2004-063551
本发明人研究用于保护半导体芯片背面的膜。结果，本发明人发明了通过使用半导体器件生产用膜将膜粘贴至半导体芯片背面的方法，其中各自包括层压于切割带上的粘合剂层的多个粘贴粘合剂层的切割带以预定间隔层压于隔离膜上。
粘贴粘合剂层的切割带根据其要粘贴的半导体晶片的形状(例如，圆形)预切割。粘贴粘合剂层的切割带当将其粘贴至半导体晶片时从隔离膜剥离。然而，依赖于粘贴粘合剂层的切割带的物理性质和依赖于设备的条件，发生粘贴粘合剂层的切割带不能良好地从隔离膜分离的额外问题。
发明内容
考虑到上述问题进行了本发明，并且其目的在于提供半导体器件生产用膜、所述膜的生产方法和通过使用半导体器件生产用膜生产半导体器件的方法，所述半导体器件生产用膜包括隔离膜和多个粘贴粘合剂层的切割带，所述粘贴粘合剂层的切割带各自包含层压于切割带上的粘合剂层，所述粘贴粘合剂层的切割带以预定间隔层压在隔离膜上，其中粘贴粘合剂层的切割带可有利地从隔离膜剥离。
本发明人出于解决本领域中上述问题的目的研究半导体器件生产用膜。结果，本发明人发现当采用以下构成时，则粘贴粘合剂层的切割带可有利地从隔离膜剥离，并完成了本发明。
即，本发明提供半导体器件生产用膜，其包括：隔离膜；和多个粘贴粘合剂层的切割带，所述多个粘贴粘合剂层的切割带各自包括切割带和层压在切割带上的粘合剂层，所述粘贴粘合剂层的切割带以粘合剂层粘贴至隔离膜的方式以预定间隔层压在隔离膜上，其中所述隔离膜具有沿切割带的外周形成的切口，和其中切口的深度为不超过隔离膜厚度的2/3。
根据上述构造，加工隔离膜以具有沿切割带外周形成的切口。因此，从切口开始，粘贴粘合剂层的切割带可容易地从隔离膜剥离。由于切口深度(切割深度)为不超过隔离膜厚度的2/3，所以当粘贴粘合剂层的切割带从隔离膜剥离时防止隔离膜从切口部分(切口)撕裂。结果，粘贴粘合剂层的切割带可有利地从隔离膜剥离(拾取)。此处，在本说明书中的术语″切口″是指隔离膜切割至不超出隔离膜厚度的一定厚度的部分。术语″切口″可称为″凹口(groove)″。
另外，本发明还提供半导体器件生产用膜的生产方法，所述方法包括：制备隔离膜粘贴的膜，所述隔离膜粘贴的膜包括隔离膜和多个粘贴粘合剂层的切割带，所述粘贴粘合剂层的切割带各自包括切割带和层压在切割带上的粘合剂层，粘贴粘合剂层的切割带以粘合剂层粘贴至隔离膜的方式层压在隔离膜上，和根据对应于隔离膜粘贴的膜要粘贴的半导体晶片的尺寸切割所述隔离膜粘贴的膜，其中将所述隔离膜粘贴的膜从粘贴粘合剂层的切割带侧切割至不超过隔离膜厚度的2/3的深度。
根据上述构造，当隔离膜粘贴的膜根据对应于该膜要粘贴的半导体晶片的尺寸切割时，将所述膜从切割带侧切割至不超过隔离膜厚度的2/3的深度。结果，在要生产的半导体器件生产用膜中，加工隔离膜从而具有沿切割带的外周形成的切口，和切口的深度为不超过隔离膜厚度的2/3。因此，在根据本发明的半导体器件生产用膜的生产方法要生产的半导体器件生产用膜中，粘贴粘合剂层的切割带可从切口开始容易地从隔离膜剥离。另外，由于切口深度为不超过隔离膜厚度的2/3，所以当粘贴粘合剂层的切割带从隔离膜剥离时防止隔离膜从切口部分(切口)撕裂。结果，粘贴粘合剂层的切割带可有利地从隔离膜剥离(拾取)。
本发明还提供通过使用上述半导体器件生产用膜来生产半导体器件的方法，所述方法包括：从半导体器件生产用膜剥离隔离膜，和粘贴半导体晶片至粘合剂层上。
本发明的半导体器件生产方法使用上述半导体器件生产用膜，其中在隔离膜中形成的切口深度为不超过隔离膜厚度的2/3。因此，当粘贴粘合剂层的切割带从隔离膜剥离时防止隔离膜从切口部分(切口)撕裂，和半导体晶片可有利地粘贴至粘合剂层上。
本发明还提供半导体器件生产用膜，其包括：隔离膜；和以预定间隔层压在隔离膜上多个切割带，其中加工隔离膜从而具有沿切割带的外周形成的切口，和切口的深度为不超过隔离膜厚度的2/3。
在上述构造中，加工隔离膜从而具有沿切割带的外周形成的切口。因此，从切口开始，切割带可容易地从隔离膜剥离。另外，由于切口的深度为不超过隔离膜厚度的2/3，所以当切割带从隔离膜剥离时防止隔离膜从切口部分(切口)撕裂。结果，切割带可有利地从隔离膜剥离(拾取)。
本发明还提供半导体器件生产用膜的生产方法，所述方法包括：制备隔离膜粘贴的膜，所述隔离膜粘贴的膜包括隔离膜和层压在隔离膜上的多个切割带，和根据对应于所述隔离膜粘贴的膜要粘贴的半导体晶片的尺寸切割该膜，其中将该膜从切割带侧切割至不超过隔离膜厚度的2/3的深度。
在上述构造中，当根据对应于隔离膜粘贴的膜要粘贴的半导体晶片的尺寸切割该膜时，将该膜从切割带侧切割至不超过隔离膜厚度的2/3的深度。结果，在要生产的半导体器件生产用膜中，加工隔离膜从而具有沿切割带的外周形成的切口，和切口深度为不超过隔离膜厚度的2/3。因此，在根据本发明的半导体器件生产用膜的生产方法要生产的半导体器件生产用膜中，从切口开始，切割带可容易地从隔离膜剥离。另外，由于切口的深度为不超过隔离膜厚度的2/3，所以当切割带从隔离膜剥离时防止隔离膜从切口部分(切口)撕裂。结果，切割带可有利地从隔离膜剥离(拾取)。
本发明还提供通过使用上述半导体器件生产用膜来生产半导体器件的方法，所述方法包括：从半导体器件生产用膜剥离隔离膜，并粘贴半导体晶片至切割带上。
本发明的半导体器件生产方法使用上述半导体器件生产用膜，其中由此在隔离膜中形成的切口深度为不超过隔离膜厚度的2/3。因此，当切割带从隔离膜剥离时防止隔离膜从切口部分(切口)撕裂，和半导体晶片可有利地粘贴至粘合剂层上。
附图说明
图1A为示出本发明的半导体器件生产用膜的一个实例的横截面示意图；和图1B为其部分平面图。
图2A至2D为示出使用本发明的粘贴粘合剂层的切割带生产半导体器件的方法的一个实例的横截面示意图。
附图标记说明
1粘贴粘合剂层的切割带
2粘合剂层
3切割带
31基材
32压敏粘合剂层
40半导体器件生产用膜
42隔离膜
44切口
33对应于半导体晶片粘贴部分的部分
4半导体晶片
5半导体芯片
51形成于半导体芯片5的电路面侧上的凸块(Bump)
6被粘物
61粘贴至被粘物6的连接垫的连结用导电性材料
具体实施方式
参考图1A和1B描述本发明的一个实施方案，然而，本发明并不局限于此。图1A是示出该实施方案的半导体器件生产用膜的一个实例的横截面示意图，以及图1B是其部分平面图。在本说明书的附图中，省略对于说明不必要的部分，并且为了易于其说明，一些部分被放大或缩小。
(半导体器件生产用膜)
如图1A和1B所示，将半导体器件生产用膜40设计为在其平面图中为圆形的粘贴粘合剂层的切割带1以预定间隔层压在长的隔离膜42上。
(粘贴粘合剂层的切割带)
粘贴粘合剂层的切割带1包括包含基材31和设置于基材31上的压敏粘合剂层32的切割带3，和设置于压敏粘合剂层32上的粘合剂层2。粘合剂层2的直径与切割带3的直径相同，或如图1B中所示，优选小于切割带3的直径。粘贴粘合剂层的切割带1经由用作它们之间粘贴面的粘合剂层2层压在隔离膜42上。从切割带3侧沿切割带3的外周加工隔离膜42从而具有深度不超过隔离膜42厚度的2/3的切口44。切口44的深度优选为隔离膜42厚度的1/6至2/3，更优选1/3至2/3。加工隔离膜42以具有沿切割带3的外周的切口44，由此促进粘贴粘合剂层的切割带1从切口44开始从隔离膜42剥离。由于切口44的深度为不超过隔离膜42厚度的2/3，所以当粘贴粘合剂层的切割带1从隔离膜42剥离时防止隔离膜42从切口部分(切口)撕裂。结果，粘贴粘合剂层的切割带1可有利地从隔离膜42剥离(拾取)。
(隔离膜)
作为隔离膜42，可用的是例如以下的薄片：纸或其它纸类基材；纤维、无纺布、毡、网和其它纤维基材；金属箔、金属板和其它金属基材；塑料类基材如塑料膜或片；橡胶类基材如橡胶片；发泡体(foams)如发泡片；及它们的层压体[尤其是塑料类材料与其它基材的层压体，塑料膜(或片材)彼此的层压体]。作为本发明的基材，优选的为塑料类基材如塑料膜或片材。塑料材料包括例如，烯烃类树脂如聚乙烯(PE)、聚丙烯(PP)和乙烯-丙烯共聚物；使用乙烯作为单体组分的共聚物，如乙烯-乙酸乙烯酯共聚物(EVA)、离聚物树脂、乙烯-(甲基)丙烯酸共聚物，和乙烯-(甲基)丙烯酸酯(无规，交替)共聚物；聚酯类如聚对苯二甲酸乙二酯(PET)、聚萘二甲酸乙二酯(PEN)和聚对苯二甲酸丁二醇酯(PBT)；丙烯酸类树脂；聚氯乙烯(PVC)；聚氨酯；聚碳酸酯；聚苯硫醚(PPS)；酰胺类树脂如聚酰胺(尼龙)和全芳族聚酰胺(whole aromatic polyamides)(芳族聚酰胺)；聚醚醚酮(PEEK)；聚酰亚胺；聚醚酰亚胺；聚偏二氯乙烯；ABS(丙烯腈-丁二烯-苯乙烯共聚物)；纤维素类树脂；硅酮树脂；和氟化树脂。隔离膜42可为单层或由两层以上形成的多层。隔离膜42可根据已知方法生产。
优选地，将隔离膜42至少在其粘合剂层2层压的表面上进行剥离处理。
剥离处理用脱模剂的实例包括氟类脱模剂、长链烷基丙烯酸酯类脱模剂、硅酮类脱模剂。总之，优选硅酮类脱模剂。
不特别限制，但隔离膜42的厚度优选为3至300μm，更优选5至200μm，甚至更优选10至100μm。当隔离膜42的厚度为至少10μm时，可容易地加工隔离膜42从而具有深度为不超过隔离膜42厚度的2/3的切口。
(粘合剂层)
粘合剂层2具有膜状。在粘贴粘合剂层的切割带1或半导体器件生产用膜40作为产物的实施方案中，粘合剂层2通常处于未固化状态(包括半固化状态)，并且在粘贴粘合剂层的切割带1粘贴至半导体晶片之后热固化。
优选地，粘合剂层至少由热固性树脂形成，更优选至少由热固性树脂和热塑性树脂形成。当粘合剂层至少由热固性树脂形成时，粘合剂层可以有效地显示其粘着功能。
热塑性树脂的实例包括天然橡胶、丁基橡胶、异戊二烯橡胶、氯丁橡胶、乙烯-乙酸乙烯酯共聚物、乙烯-丙烯酸共聚物、乙烯-丙烯酸酯共聚物、聚丁二烯树脂、聚碳酸酯树脂、热塑性聚酰亚胺树脂、聚酰胺树脂如6-尼龙和6，6-尼龙、苯氧基树脂、丙烯酸类树脂、饱和聚酯树脂如PET(聚对苯二甲酸乙二酯)或PBT(聚对苯二甲酸丁二醇酯)、聚酰胺酰亚胺树脂或氟树脂。热塑性树脂可以单独使用或以两种以上的组合使用。在这些热塑性树脂中，特别优选包含少量离子性杂质、具有高耐热性和能够确保半导体元件可靠性的丙烯酸类树脂。
丙烯酸类树脂没有特别限定，其实例包括含有一种或两种以上具有含有30个以下碳原子、优选4-18个碳原子、更优选6-10个碳原子和特别是8或9个碳原子的直链或支链烷基的丙烯酸或甲基丙烯酸的酯作为组分的聚合物。即，在本发明中，丙烯酸类树脂具有还包括甲基丙烯酸类树脂的宽泛含义。所述烷基的实例包括甲基、乙基、丙基、异丙基、正丁基、叔丁基、异丁基、戊基、异戊基、己基、庚基、2-乙基己基、辛基、异辛基、壬基、异壬基、癸基、异癸基、十一烷基、十二烷基(月桂基)、十三烷基、十四烷基、硬脂酰基和十八烷基。
此外，形成丙烯酸类树脂的其它单体(除烷基为具有30个以下碳原子的烷基的丙烯酸或甲基丙烯酸的烷基酯以外的单体)没有特别限定，其实例包括含羧基的单体如丙烯酸、甲基丙烯酸、丙烯酸羧乙酯、丙烯酸羧戊酯、衣康酸、马来酸、富马酸和巴豆酸；酸酐单体如马来酸酐和衣康酸酐；含羟基的单体如(甲基)丙烯酸2-羟乙酯、(甲基)丙烯酸2-羟丙酯、(甲基)丙烯酸4-羟丁酯、(甲基)丙烯酸6-羟己酯、(甲基)丙烯酸8-羟辛酯、(甲基)丙烯酸10-羟癸酯、(甲基)丙烯酸12-羟月桂酯和(4-羟甲基环己基)-甲基丙烯酸酯；含磺酸基的单体如苯乙烯磺酸、烯丙基磺酸、2-(甲基)丙烯酰胺基-2-甲基丙磺酸、(甲基)丙烯酰胺基丙磺酸、(甲基)丙烯酸磺丙酯和(甲基)丙烯酰氧基萘磺酸；和含磷酸基团的单体如2-羟乙基丙烯酰磷酸酯(2-hydroethylacryloyl phosphate)。在这点上，(甲基)丙烯酸是指丙烯酸和/或甲基丙烯酸，(甲基)丙烯酸酯是指丙烯酸酯和/或甲基丙烯酸酯，(甲基)丙烯酰基是指丙烯酰基和/或甲基丙烯酰基，等等，这应用于整个说明书中。
此外，除了环氧树脂和酚醛树脂之外，热固性树脂的实例还包括，氨基树脂、不饱和聚酯树脂、聚氨酯树脂、硅酮树脂和热固性聚酰亚胺树脂。热固性树脂可以单独使用或以其两种以上的组合使用。作为热固性树脂，包含仅少量腐蚀半导体元件的离子性杂质的环氧树脂是合适的。此外，酚醛树脂适合用作环氧树脂的固化剂。
环氧树脂不特别限制，例如，可使用双官能环氧树脂或多官能环氧树脂如双酚A型环氧树脂、双酚F型环氧树脂、双酚S型环氧树脂、溴化双酚A型环氧树脂、氢化双酚A型环氧树脂、双酚AF型环氧树脂、联苯型环氧树脂、萘型环氧树脂、芴型环氧树脂、苯酚酚醛清漆(phenol novolak)型环氧树脂、邻甲酚酚醛清漆(o-cresol novolak)型环氧树脂、三羟基苯甲烷型环氧树脂和四羟苯基乙烷(tetraphenylolethane)型环氧树脂，或环氧树脂如乙内酰脲型环氧树脂、三缩水甘油基异氰脲酸酯型环氧树脂或缩水甘油基胺型环氧树脂。
作为环氧树脂，在以上示例的那些中，酚醛清漆型环氧树脂、联苯型环氧树脂、三羟基苯甲烷型环氧树脂和四羟苯基乙烷型环氧树脂是优选的。这是因为这些环氧树脂与作为固化剂的酚醛树脂具有高反应性，且耐热性等优异。
另外，上述酚醛树脂起到环氧树脂的固化剂的作用，其实例包括酚醛清漆型酚醛树脂如苯酚酚醛清漆树脂、苯酚芳烷基树脂、甲酚酚醛清漆树脂、叔丁基苯酚酚醛清漆树脂和壬基苯酚酚醛清漆树脂；甲阶型酚醛树脂；和聚氧苯乙烯(polyoxystyrenes)如聚对氧苯乙烯。所述酚醛树脂可单独使用，或以两种或多种组合使用。在这些酚醛树脂中，苯酚酚醛清漆树脂和苯酚芳烷基树脂是特别优选的。这是因为可改进半导体器件的连接可靠性。
环氧树脂与酚醛树脂的混合比优选使得例如酚醛树脂中的羟基为0.5至2.0当量，基于每当量环氧树脂组分中的环氧基团。更优选0.8至1.2当量。即，当混合比变为在该范围之外时，固化反应不能充分进行，环氧树脂固化产物的特性趋于劣化。
热固性树脂的含量优选为粘合剂层中所有树脂组分的5重量％至90重量％，更优选10重量％至85重量％，甚至更优选15重量％至80重量％。当含量为5％以上时，则热固性收缩量可容易地控制为2体积％以上。另外，在热固化封装树脂中，粘合剂层可完全地热固化以确保粘附和固定至半导体元件背面，从而给出没有剥离失败的倒装芯片型半导体器件。另一方面，当含量为90重量％以下时，则可防止包装(PKG，倒装芯片型半导体器件)翘曲。
用于环氧树脂和酚醛树脂的热固化促进催化剂没有特别限定，可适当选自已知的热固化促进催化剂。热固化促进催化剂可单独使用或以两种以上的组合使用。作为热固化促进催化剂，例如，可使用胺类固化促进催化剂、磷类固化促进催化剂、咪唑类固化促进催化剂、硼类固化促进催化剂或磷-硼类固化促进催化剂。
粘合剂层特别适合由含有环氧树脂和酚醛树脂的树脂组合物或含有环氧树脂、酚醛树脂和丙烯酸类树脂的树脂组合物形成。由于这些树脂仅包含少量离子性杂质并且具有高耐热性，所以能够确保半导体元件的可靠性。
重要的是粘合剂层具有对于半导体晶片背面(非电路形成面)的粘合性(紧密粘合性)。粘合剂层可例如由包含环氧树脂作为热固性树脂组分的树脂组合物形成。在粘合剂层预先固化至一定程度的情况下，在其制备时，优选添加能够与在聚合物的分子链末端的官能团等反应的多官能化合物作为交联剂。由此，可以提高在高温下的粘合特性并且可以实现膜的耐热性的改进。
粘合剂层对于半导体晶片的粘合力(23℃、剥离角度为180°、剥离速率为300mm/分钟)优选在0.5N/20mm至15N/20mm、更优选0.7N/20mm至10N/20mm的范围内。当粘合力为至少0.5N/20mm时，则可将粘合剂层以优良粘合性地粘附至半导体晶片和半导体元件，并且不存在膜鼓起等粘合失败。另外，在切割半导体晶片中，可防止芯片飞出。另一方面，当粘合力为不超过15N/20mm时，则其促进从切割带的剥离。
交联剂不特别限制，可使用已知的交联剂。具体地，例如，不仅可提及异氰酸酯类交联剂、环氧类交联剂、三聚氰胺类交联剂和过氧化物类交联剂，还提及脲类交联剂、金属醇盐类交联剂、金属螯合物类交联剂、金属盐类交联剂、碳二亚胺类交联剂、噁唑啉类交联剂、氮丙啶类交联剂和胺类交联剂等。作为交联剂，异氰酸酯类交联剂或环氧类交联剂是合适的。交联剂可单独或以两种以上组合使用。
异氰酸酯类交联剂的实例包括低级脂肪族多异氰酸酯例如1，2-亚乙基二异氰酸酯、1，4-亚丁基二异氰酸酯和1，6-六亚甲基二异氰酸酯；脂环族多异氰酸酯例如亚环戊基二异氰酸酯、亚环己基二异氰酸酯、异佛尔酮二异氰酸酯、氢化甲苯二异氰酸酯和氢化苯二甲撑二异氰酸酯；和芳香族多异氰酸酯例如2，4-甲苯二异氰酸酯、2，6-甲苯二异氰酸酯、4，4′-二苯甲烷二异氰酸酯和苯二甲撑二异氰酸酯。另外，也使用三羟甲基丙烷/甲苯二异氰酸酯三聚体加合物[商品名“COLONATE L”，由Nippon Polyurethane Industry Co.，Ltd.制造]、三羟甲基丙烷/六亚甲基二异氰酸酯三聚体加合物[商品名“COLONATE HL”，由NipponPolyurethane Industry Co.，Ltd.制造]等。此外，环氧类交联剂的实例包括N，N，N′，N′-四缩水甘油基-间苯二甲胺、二缩水甘油基苯胺、1，3-双(N，N-缩水甘油基氨甲基)环己烷、1，6-己二醇二缩水甘油醚、新戊二醇二缩水甘油醚、乙二醇二缩水甘油醚、丙二醇二缩水甘油醚、聚乙二醇二缩水甘油醚、聚丙二醇二缩水甘油醚、山梨糖醇多缩水甘油醚、甘油多缩水甘油醚、季戊四醇多缩水甘油醚、聚甘油多缩水甘油醚、脱水山梨糖醇多缩水甘油醚、三羟甲基丙烷多缩水甘油醚、己二酸二缩水甘油酯、邻苯二甲酸二缩水甘油酯、三缩水甘油基-三(2-羟乙基)异氰脲酸酯、间苯二酚二缩水甘油醚和双酚-S-二缩水甘油醚，以及还有在分子中具有两个以上的环氧基团的环氧类树脂。
交联剂的使用量没有特别限定，可依赖于交联程度适当选择。具体地，优选交联剂的使用量为通常7重量份以下(例如0.05至7重量份)，基于100重量份聚合物组分(特别地，在分子链末端具有官能团的聚合物)。当交联剂的量基于100重量份聚合物组分大于7重量份时，粘合力降低，因此不优选该情况。从改进内聚力的观点，交联剂的量基于100重量份聚合物组分优选为0.05重量份以上。
在本发明中，代替使用交联剂或与交联剂的使用一起，也可以通过用电子束或紫外线等照射进行交联处理。
优选将粘合剂层着色。由此，能够显示优良的激光标识性和优良的外观性，且变得能够使半导体器件具有增值的外观性。如上所述，由于着色的粘合剂层具有优良的标识性，可借助于利用任何各种标识方法如印刷法和激光标识法通过粘合剂层进行标识以将各种信息如文字信息和图形信息赋予到半导体元件或使用半导体元件的半导体器件的非电路侧的面上。特别地，通过控制着色的颜色，可以观察通过优良可视性标识而赋予的信息(例如，文字信息和图形信息)。此外，当将粘合剂层着色时，切割带和粘合剂层可容易地彼此区分，因而可提高加工性等。另外，例如，作为半导体器件，可以通过使用不同的颜色分类其产物。在将粘合剂层着色的情况(该粘合剂层既不是无色的也不是透明的情况)下，通过着色显示的颜色没有特别限定，但例如优选暗色如黑色、蓝色或红色，黑色是特别适合的。
在本实施方案中，暗色主要指具有60以下(0至60)、优选50以下(0至50)、更优选40以下(0至40)的在L*a*b*颜色空间中定义的L*的暗色。
此外，黑色主要是指具有35以下(0至35)，优选30以下(0至30)，更优选25以下(0至25)的在L*a*b*颜色空间中定义的L*的黑色系颜色。在这点上，在黑色中，在L*a*b*颜色空间中定义的各a*和b*可根据L*的值适当选择。例如，a*和b*两者均优选在-10至10，更优选-5至5，进一步优选-3至3(特别地0或约0)的范围内。
在本实施方案中，在L*a*b*颜色空间中定义的L*、a*和b*可通过用色差计(商品名“CR-200”，由Minolta Ltd制造；色差计)的测量来确定。L*a*b*颜色空间为在1976年由Commission Internationale de l’Eclairage(CIE)建议的颜色空间，是指称为CIE1976(L*a*b*)颜色空间的颜色空间。此外，在日本工业标准(Japanese Industrial Standards)JIS Z8729中定义了L*a*b*颜色空间。
在粘合剂层着色时，根据目标颜色，可使用着色剂(着色试剂)。作为此类着色剂，可适当使用各种暗色着色剂如黑色着色剂、蓝色着色剂和红色着色剂，黑色着色剂是更适合的。着色剂可为任意颜料和染料。着色剂可单独使用或以两种以上的组合使用。在这点上，作为染料，可以使用任何形式的染料如酸性染料、反应性染料、直接染料、分散染料和阳离子染料。此外，同样关于颜料，其形式不特别限制，可在已知颜料中适当选择和使用。
特别地，当使用染料作为着色剂时，染料变为处于通过溶解于粘合剂层中而均匀地或几乎均匀地分散的状态，因此可容易地生产具有均匀的或几乎均匀的着色浓度的粘合剂层(结果，粘贴粘合剂层的切割带)。因此，当使用染料作为着色剂时，在粘贴粘合剂层的切割带中的粘合剂层可具有均匀地或几乎均匀的着色浓度，并可提高标识性和外观性。
黑色着色剂不特别限制，例如，可适当选自无机黑色颜料和黑色染料。此外，黑色着色剂可为混合青色着色剂(蓝-绿色着色剂)、品红色着色剂(红-紫色着色剂)和黄色着色剂(黄色着色剂)的着色剂混合物。黑色着色剂可单独或以两种以上的组合使用。当然，黑色着色剂可与除黑色之外颜色的着色剂组合使用。
黑色着色剂的具体实例包括炭黑(如炉黑、槽黑、乙炔黑、热裂炭黑或灯黑)、石墨、氧化铜、二氧化锰、偶氮型颜料(例如，偶氮甲碱偶氮黑)、苯胺黑、苝黑、钛黑、花青黑、活性炭、铁素体(如非磁性铁素体或磁性铁素体)、磁铁矿、氧化铬、氧化铁、二硫化钼、铬配合物、复合氧化物型黑色颜料和蒽醌型有机黑色颜料。
在本发明中，作为黑色着色剂，也可利用黑色染料如C.I.溶剂黑3、7、22、27、29、34、43、70，C.I.直接黑17、19、22、32、38、51、71，C.I.酸性黑1、2、24、26、31、48、52、107、109、110、119、154，和C.I.分散黑1、3、10、24；和黑色颜料如C.I.颜料黑1、7；等等。
作为此类黑色着色剂，例如，商品名″Oil Black BY″、商品名″Oil Black BS″、商品名″Oil Black HBB″、商品名″Oil Black803″、商品名″Oil Black 860″、商品名″OilBlack 5970″、商品名″Oil Black 5906″、商品名″Oil Black 5905″(由OrientChemicalIndustries Co.，Ltd.制造)等是商购可得的。
除了黑色着色剂的其它着色剂的实例包括青色着色剂、品红色着色剂和黄色着色剂。青色着色剂的实例包括青色染料如C.I.溶剂蓝25、36、60、70、93、95；C.I.酸性蓝6和45；青色颜料如C.I.颜料蓝1、2、3、15、15:1、15:2、15:3、15:4、15:5、15:6、16、17、17:1、18、22、25、56、60、63、65、66；C.I.瓮蓝4、60；C.I.颜料绿7。
此外，在品红色着色剂中，品红色染料的实例包括C.I.溶剂红1、3、8、23、24、25、27、30、49、52、58、63、81、82、83、84、100、109、111、121、122；C.I.分散红9；C.I.溶剂紫8、13、14、21、27；C.I.分散紫1；C.I.碱性红1、2、9、12、13、14、15、17、18、22、23、24、27、29、32、34、35、36、37、38、39、40；C.I.碱性紫1、3、7、10、14、15、21、25、26、27和28。
在品红色着色剂中，品红色颜料的实例包括C.I.颜料红1、2、3、4、5、6、7、8、9、10、11、12、13、14、15、16、17、18、19、21、22、23、30、31、32、37、38、39、40、41、42、48:1、48:2、48:3、48:4、49、49:1、50、51、52、52:2、53:1、54、55、56、57:1、58、60、60:1、63、63:1、63:2、64、64:1、67、68、81、83、87、88、89、90、92、101、104、105、106、108、112、114、122、123、139、144、146、147、149、150、151、163、166、168、170、171、172、175、176、177、178、179、184、185、187、190、193、202、206、207、209、219、222、224、238、245；C.I.颜料紫3、9、19、23、31、32、33、36、38、43、50；C.I.瓮红1、2、10、13、15、23、29和35。
此外，黄色着色剂的实例包括黄色染料如C.I.溶剂黄19、44、77、79、81、82、93、98、103、104、112和162；黄色颜料如C.I.颜料橙31、43；C.I.颜料黄1、2、3、4、5、6、7、10、11、12、13、14、15、16、17、23、24、34、35、37、42、53、55、65、73、74、75、81、83、93、94、95、97、98、100、101、104、108、109、110、113、114、116、117、120、128、129、133、138、139、147、150、151、153、154、155、156、167、172、173、180、185、195；C.I.瓮黄1、3和20。
各种着色剂如青色着色剂、品红色着色剂和黄色着色剂可分别单独使用或以两种以上的组合使用。在这点上，在使用各种着色剂如青色着色剂、品红色着色剂和黄色着色剂中的两种以上的情况下，这些着色剂的混合比(或共混比)没有特别限定，可根据各着色剂的种类和目标颜色等适当选择。
在将粘合剂层2着色的情况下，着色形式没有特别限定。粘合剂层可为例如添加有着色剂的单层膜状制品。此外，该膜可为至少层压至少由热固性树脂形成的树脂层与着色剂层的层压膜。在这点上，在粘合剂层2为树脂层和着色剂层的层压膜的情况下，层压形式中的粘合剂层2优选具有树脂层/着色剂层/树脂层的层压形式。在该情况下，在着色剂层两侧的两层树脂层可为具有相同组成的树脂层或可为具有不同组成的树脂层。
向粘合剂层2中，根据需要可适当共混其它添加剂。其它添加剂的实例除了填料、阻燃剂、硅烷偶联剂和离子捕集剂之外，还包括增量剂、防老剂、抗氧化剂和表面活性剂。
填料可为任意的无机填料和有机填料，但无机填料是合适的。通过共混填料如无机填料，能够实现赋予粘合剂层以导电性、改进导热性和控制弹性模量等。在这点上，粘合剂层2可为导电性的或非导电性的。无机填料的实例包括由以下组成的各种无机粉末：二氧化硅、粘土、石膏、碳酸钙、硫酸钡、氧化铝、氧化铍、陶瓷如碳化硅和氮化硅、金属或合金如铝、铜、银、金、镍、铬、铅、锡、锌、钯，和焊料及碳等。填料可以单独使用或以两种以上的组合使用。特别地，填料适合为二氧化硅，更适合为熔凝硅石(fused silica)。无机填料的平均粒径优选在0.1μm-80μm的范围内。无机填料的平均粒径可通过激光衍射型粒径分布测量设备来测量。
填料(特别地，无机填料)的共混量优选为80重量份以下(0重量份-80重量份)，更优选为0重量份-70重量份，基于100重量份有机树脂组分。
阻燃剂的实例包括三氧化锑、五氧化锑和溴化环氧树脂。阻燃剂可以单独使用或以两种以上的组合使用。硅烷偶联剂的实例包括β-(3，4-环氧环己基)乙基三甲氧基硅烷、γ-环氧丙氧丙基三甲氧基硅烷和γ-环氧丙氧丙基甲基二乙氧基硅烷。硅烷偶联剂可以单独使用或以两种以上的组合使用。离子捕集剂的实例包括水滑石和氢氧化铋。离子捕集剂可以单独使用或以两种以上的组合使用。
粘合剂层2例如可通过利用包括以下步骤的常规使用方法形成：将热固性树脂例如环氧树脂和如果必要的热塑性树脂如丙烯酸类树脂以及任选的溶剂和其它添加剂混合从而制备树脂组合物，接着将其成形为膜状层。具体地，作为粘合剂层的膜状层(粘合剂层)例如能够通过以下方法形成：包括将树脂组合物施涂至切割带的压敏粘合剂层32上的方法；包括将树脂组合物施涂至适当的隔离膜(例如，剥离纸)上以形成树脂层(或粘合剂层)，然后将其转移(转换)至压敏粘合剂层32上的方法；等等。在这点上，树脂组合物可为溶液或分散液。
此外，在粘合剂层2由包含热固性树脂如环氧树脂的树脂组合物形成的情况下，在将所述膜施用至半导体晶片之前的阶段，粘合剂层处于热固性树脂未固化或部分固化的状态。在该情况下，在将其施用至半导体晶片之后(具体地，通常，在当包封材料在倒装芯片接合步骤中固化时)，粘合剂层中的热固性树脂完全或几乎完全固化。
如上所述，由于即使当膜包含热固性树脂时，粘合剂层也处于热固性树脂未固化或部分固化的状态，因此粘合剂层的凝胶分数没有特别限定，但例如在50重量％以下(0-50重量％)的范围内合适地选择，并优选30重量％以下(0-30重量％)，特别优选10重量％以下(0-10重量％)。粘合剂层的凝胶分数可通过以下测量方法测量。
<凝胶分数测量方法>
从粘合剂层中取样约0.1g样品，并精确称重(样品重量)，将样品包裹在网型片材(mesh-type sheet)中后，将它在室温下在约50ml甲苯中浸渍1周。此后，从甲苯中取出溶剂不溶性物质(网型片材中的内容物)，并在130℃下干燥约2小时，将干燥后的溶剂不溶性物质称重(浸渍并干燥后的重量)，然后根据以下表达式(a)计算凝胶分数(重量％)。
凝胶分数(重量％)＝{(浸渍并干燥后的重量)/(样品重量)}×100 (a)
粘合剂层的凝胶分数能够通过树脂组分的种类和含量、交联剂的种类和含量以及除此之外的加热温度和加热时间等来控制。
在本发明中，在粘合剂层为由包含热固性树脂如环氧树脂的树脂组合物形成的膜状制品的情况下，可有效地显示对半导体晶片的紧密粘合性。
此外，由于在半导体晶片的切割步骤中使用切割水，粘合剂层吸收水分，从而在一些情况下具有常规状态以上的水分含量。当在仍维持此类高水分含量下进行倒装芯片接合时，水蒸气残留在粘合剂层和半导体晶片或其加工体(半导体)之间的粘合界面处，并且在一些情况下产生浮起。因此，通过构成粘合剂层为将具有高透湿性的芯材料设置于其各表面上的构造，水蒸气扩散，由此可以避免此类问题。从该观点，其中粘合剂层形成于芯材料的一面或两面的多层结构可用作粘合剂层。芯材料的实例包括膜(例如，聚酰亚胺膜、聚酯膜、聚对苯二甲酸乙二酯膜、聚萘二甲酸乙二酯膜、聚碳酸酯膜等)、用玻璃纤维或塑料无纺纤维增强的树脂基板、硅基板和玻璃基板。
粘合剂层2的厚度(在层压膜的情况下为总厚度)不特别限制，但例如可适当选自约2μm-200μm的范围。另外，该厚度优选约4μm-160μm，更优选约6μm-100μm和特别优选约10μm-80μm。
粘合剂层2在23℃下的未固化状态时的拉伸贮能弹性模量优选为1GPa以上(例如，1GPa-50GPa)，更优选2GPa以上，特别地3GPa以上是适合的。当该拉伸贮能弹性模量为1GPa以上时，当在将半导体芯片与粘合剂层2一起从切割带的压敏粘合剂层32剥离之后将粘合剂层2放置在支承体上并进行输送等时，能够有效地抑制或防止粘合剂层粘贴至支承体。在这点上，支承体例如为载带(carrier tape)中的顶带和底带等。如上所述，在粘合剂层2由包含热固性树脂的树脂组合物形成的情况下，热固性树脂通常处于未固化或部分固化的状态，因此粘合剂层在23℃下的拉伸贮能弹性模量为处于热固性树脂未固化或部分固化的状态的23℃下的拉伸贮能弹性模量。
此处，粘合剂层2可为单层或层压多层的层压膜。在层压膜的情况下，作为整个层压膜的拉伸贮能弹性模量为充分的1GPa以上(例如，1GPa-50GPa)。此外，处于未固化状态的粘合剂层的拉伸贮能弹性模量(23℃)可通过适当设定树脂组分(热塑性树脂和/或热固性树脂)的种类和含量或填料如二氧化硅填料的种类和含量来控制。在粘合剂层2为层压多层的层压膜的情况下(粘合剂层具有层压层形式的情况下)，作为层压层形式，例如，可示例由晶片粘合剂层和激光标识层构成的层压形式。此外，在晶片粘合剂层和激光标识层之间，可设置其它层(中间层、遮光层、补强层、着色层、基材层、电磁波屏蔽层、导热层、压敏粘合剂层等)。在这点上，晶片粘合剂层为显示对晶片优良的紧密粘合性(粘合性质)的层和与晶片背面接触的层。另一方面，激光标识层为显示优良的激光标识性的层和在半导体芯片背面上激光标识时利用的层。
拉伸贮能弹性模量通过如下测定：制备没有层压至切割带3上的处于未固化状态的粘合剂层2，并使用由Rheometrics Co.，Ltd.制造的动态粘弹性测量设备“SolidAnalyzer RS A2”，在规定温度(23℃)下，在氮气气氛下，在样品宽度为10mm、样品长度为22.5mm、样品厚度为0.2mm、频率1Hz和升温速率为10℃/分钟的条件下，以拉伸模式测量弹性模量，并将该测量的弹性模量作为所得拉伸贮能弹性模量的值。
此外，在粘合剂层2中对于可见光的透光率(可见光透过率，波长：400至800nm)不特别限制，但是，例如，优选在20％以下(0至20％)，更优选10％以下(0至10％)，特别优选5％以下(0至5％)的范围内。当粘合剂层2具有大于20％的可见光透过率时，存在光的透过率可能不利地影响半导体元件的顾虑。可见光透过率(％)能够通过粘合剂层2的树脂组分的种类和含量、着色剂(例如颜料或染料)的种类和含量，和无机填料的含量等来控制。
粘合剂层2的可见光透过率(％)可如下测定。即，制备本身具有厚度(平均厚度)为20μm的粘合剂层2。然后，将粘合剂层2用具有波长为400至800nm的可见光在规定强度下照射[设备：由Shimadzu Corporation制造的可见光产生设备[商品名″ABSORPTION SPECTROPHOTOMETER″]]，并测量透过的可见光的强度。此外，可基于可见光透过粘合剂层2前后的强度变化来确定可见光透过率(％)。在这点上，也可以从厚度不是20μm的粘合剂层2的可见光透过率(％；波长：400至800nm)的值推导出厚度为20μm的粘合剂层2的可见光透过率(％；波长：400至800nm)。在本发明中，在厚度为20μm的粘合剂层2的情况下测定可见光透过率(％)，但根据本发明的粘合剂层不限于厚度为20μm的粘合剂层。
此外，作为粘合剂层2，更优选具有较低吸湿度的粘合剂层。具体地，吸湿度优选1重量％以下，更优选0.8重量％以下。通过将吸湿度调整至1重量％以下，能够提高激光标识性。此外，例如，在再流步骤(reflow step)中能够抑制或防止半粘合剂层2和半导体元件之间空隙的产生。吸湿度为由将粘合剂层2在温度85℃和湿度85％RH的环境下静置168小时前后的重量变化计算的值。在粘合剂层2由包含热固性树脂的树脂组合物形成的情况下，吸湿度是指当将热固化后的粘合剂层在温度85℃和湿度85％RH的环境下静置168小时时获得的值。此外，吸湿度例如可通过改变无机填料的添加量来调整。
此外，作为粘合剂层2，更优选具有较小比例的挥发性物质的粘合剂层。具体地，热处理后粘合剂层2的重量减少的比例(重量减少率)优选为1重量％以下，更优选0.8重量％以下。热处理的条件为：加热温度为250℃，加热时间为1小时。通过将重量减少率调整至1重量％以下，能够提高激光标识性。此外，例如，在再流步骤中能够抑制或防止倒装芯片型半导体器件中裂纹的产生。重量减少率例如可通过添加能够在无铅焊料再流时减少裂纹产生的无机物质来调整。在粘合剂层2由包含热固性树脂组分的树脂组合物形成的情况下，重量减少率为当将热固化后的粘合剂层在温度250℃和加热时间为1小时的条件下加热时获得的值。
(切割带)
切割带3包括基材31和形成于基材31上的压敏粘合剂层32。因而，切割带3充分具有层压基材31和压敏粘合剂层32的构造。基材(支承基材)可用作压敏粘合剂层等的支承材料。基材31优选具有放射线透过性。作为基材31，例如，可使用合适的薄材料，例如纸类基材如纸；纤维类基材如织物、无纺布、毡和网；金属类基材如金属箔和金属板；塑料基材如塑料膜和片；橡胶类基材如橡胶片；发泡体(foamed body)如发泡片；及其层压体[特别地，塑料基材与其它基材的层压体，塑料膜(或片)彼此的层压体等]。在本发明中，作为基材，可适合使用塑料基材如塑料膜和片。此类塑料材料的原料实例包括烯烃类树脂(olefinicresins)如聚乙烯(PE)、聚丙烯(PP)和乙烯-丙烯共聚物；使用乙烯作为单体组分的共聚物，如乙烯-乙酸乙烯酯共聚物(EVA)、离聚物树脂、乙烯-(甲基)丙烯酸共聚物，和乙烯-(甲基)丙烯酸酯(无规，交替)共聚物；聚酯如聚对苯二甲酸乙二酯(PET)、聚萘二甲酸乙二酯(PEN)和聚对苯二甲酸丁二醇酯(PBT)；丙烯酸类树脂；聚氯乙烯(PVC)；聚氨酯；聚碳酸酯；聚苯硫醚(PPS)；酰胺类树脂如聚酰胺(尼龙)和全芳族聚酰胺(whole aromatic polyamides)(芳族聚酰胺)；聚醚醚酮(PEEK)；聚酰亚胺；聚醚酰亚胺；聚偏二氯乙烯；ABS(丙烯腈-丁二烯-苯乙烯共聚物)；纤维素类树脂；硅酮树脂；和氟化树脂。
此外，用于基材31的材料包括聚合物如前述树脂的交联材料。塑料膜可在不拉伸的情况下使用或者需要时可在进行单轴或双轴拉伸处理后使用。根据通过拉伸处理等赋予热收缩性的树脂片，在切割后通过基材31的热收缩减小压敏粘合剂层32和粘合剂层2之间的粘合面积，因而能够使半导体芯片的回收容易。
为了提高与邻接层的紧密粘合性和保持性等，可在基材31的表面上实施常规使用的表面处理，例如化学或物理处理如铬酸盐处理、臭氧暴露(ozone exposure)、火焰暴露(flame exposure)、暴露于高压电击或电离辐射处理，或用底漆剂(undercoating agent)例如稍后提及的压敏粘合剂物质的涂布处理。
作为基材31，可适当选择和使用相同种类或不同种类的材料，需要时，可将几种材料共混并使用。此外，为了赋予基材31以抗静电能力，可在基材31上形成由金属、合金或其氧化物组成的厚度为约30至500埃的导电性物质的气相沉积层。基材31可为单层或其两层以上的多层。
基材31的厚度(在层压层的情况下为总厚度)没有特别限定，可依赖于强度、挠性及预期的用途等适当选择。例如，厚度通常为1000μm以下(例如1μm至1000μm)，优选10μm至500μm，进一步优选20μm至300μm，特别优选约30μm至200μm，但不限于此。
此外，在不损害本发明的优点等的范围内，基材31可包含各种添加剂(着色剂、填料、增塑剂、防老剂、抗氧化剂、表面活性剂、阻燃剂等)。
压敏粘合剂层32由压敏粘合剂形成并具有压敏粘合性。该压敏粘合剂没有特别限定，可在已知压敏粘合剂中适当选择。具体地，作为压敏粘合剂，例如，具有上述特性的压敏粘合剂可在例如以下的已知压敏粘合剂中适当选择并在本文使用：丙烯酸类压敏粘合剂、橡胶类压敏粘合剂、乙烯基烷基醚类压敏粘合剂、硅酮类压敏粘合剂、聚酯类压敏粘合剂、聚酰胺类压敏粘合剂、聚氨酯类压敏粘合剂、氟类压敏粘合剂、苯乙烯-二烯嵌段共聚物类压敏粘合剂，和其中将具有约200℃以下熔点的热熔融性树脂混入上述压敏粘合剂中制备的蠕变特性改进的压敏粘合剂(参见例如，JP-A-56-61468、JP-A-61-174857、JP-A-63-17981、JP-A-56-13040等，通过参考并入本文)。作为压敏粘合剂，此处也可使用照射固化型压敏粘合剂(或能量射线固化型压敏粘合剂)和热膨胀性压敏粘合剂。此类压敏粘合剂可单独或多种组合使用。
作为压敏粘合剂，此处优选使用的是丙烯酸类压敏粘合剂和橡胶类压敏粘合剂，更优选丙烯酸类压敏粘合剂。丙烯酸类压敏粘合剂包括将一种以上(甲基)丙烯酸烷基酯作为单体组分的丙烯酸类聚合物(均聚物或共聚物)用作基础聚合物的丙烯酸类压敏粘合剂。
在上述丙烯酸类压敏粘合剂中的(甲基)丙烯酸烷基酯的实例包括例如，(甲基)丙烯酸甲酯、(甲基)丙烯酸乙酯、(甲基)丙烯酸丙酯、(甲基)丙烯酸异丙酯、(甲基)丙烯酸丁酯、(甲基)丙烯酸异丁酯、(甲基)丙烯酸仲丁酯、(甲基)丙烯酸叔丁酯、(甲基)丙烯酸戊酯、(甲基)丙烯酸己酯、(甲基)丙烯酸庚酯、(甲基)丙烯酸辛酯、(甲基)丙烯酸2-乙基己酯、(甲基)丙烯酸异辛酯、(甲基)丙烯酸壬酯、(甲基)丙烯酸异壬酯、(甲基)丙烯酸癸酯、(甲基)丙烯酸异癸酯、(甲基)丙烯酸十一烷酯、(甲基)丙烯酸十二烷酯、(甲基)丙烯酸十三烷酯、(甲基)丙烯酸十四烷酯、(甲基)丙烯酸十五烷酯、(甲基)丙烯酸十六烷酯、(甲基)丙烯酸十七烷酯、(甲基)丙烯酸十八烷酯、(甲基)丙烯酸十九烷酯和(甲基)丙烯酸二十烷酯等。作为(甲基)丙烯酸烷基酯，优选其中烷基具有4至18个碳原子的(甲基)丙烯酸烷基酯。在(甲基)丙烯酸烷基酯中，烷基可为直链或支链的。
为了改善其内聚力、耐热性及交联性的目的，如果需要，上述丙烯酸类聚合物可包含与上述(甲基)丙烯酸烷基酯可共聚的任何其它单体组分(共聚性单体组分)对应的单元。该共聚性单体组分包括例如，含羧基单体如(甲基)丙烯酸(丙烯酸或甲基丙烯酸)、丙烯酸羧乙酯、丙烯酸羧戊酯、衣康酸、马来酸、富马酸、巴豆酸；含酸酐基团的单体如马来酸酐、衣康酸酐；含羟基的单体如(甲基)丙烯酸羟乙酯、(甲基)丙烯酸羟丙酯、(甲基)丙烯酸羟丁酯、(甲基)丙烯酸羟己酯、(甲基)丙烯酸羟辛酯、(甲基)丙烯酸羟癸酯、(甲基)丙烯酸羟月桂酯和甲基丙烯酸(4-羟甲基环己基)甲酯；含磺酸基团单体如苯乙烯磺酸、烯丙基磺酸、2-(甲基)丙烯酰胺-2-甲基丙磺酸、(甲基)丙烯酰胺丙磺酸、(甲基)丙烯酸磺丙酯、(甲基)丙烯酰氧基萘磺酸；含磷酸基团的单体如2-羟乙基丙烯酰磷酸酯；(N-取代的)酰胺类单体如(甲基)丙烯酰胺、N，N-二甲基(甲基)丙烯酰胺、N-丁基(甲基)丙烯酰胺、N-羟甲基(甲基)丙烯酰胺、N-羟甲基丙烷(甲基)丙烯酰胺；(甲基)丙烯酸氨基烷基酯类单体如(甲基)丙烯酸氨基乙酯、(甲基)丙烯酸N，N-二甲氨基乙酯、(甲基)丙烯酸叔丁氨基乙酯；(甲基)丙烯酸烷氧基烷基酯类单体如(甲基)丙烯酸甲氧基乙酯、(甲基)丙烯酸乙氧基乙酯；氰基丙烯酸酯类单体如丙烯腈和甲基丙烯腈；含环氧基的丙烯酸类单体如(甲基)丙烯酸缩水甘油酯；苯乙烯类单体如苯乙烯、α-甲基苯乙烯；乙烯基酯类单体例如乙酸乙烯酯、丙酸乙烯酯；烯烃类单体如异戊二烯、丁二烯、异丁烯；乙烯基醚类单体例如乙烯基醚；含氮单体如N-乙烯基吡咯烷酮、甲基乙烯基吡咯烷酮、乙烯基吡啶、乙烯基哌啶酮、乙烯基嘧啶、乙烯基哌嗪、乙烯基吡嗪、乙烯基吡咯、乙烯基咪唑、乙烯基噁唑、乙烯基吗啉、N-乙烯基碳酰胺、N-乙烯基己内酰胺；马来酰亚胺类单体如N-环己基马来酰亚胺、N-异丙基马来酰亚胺、N-月桂基马来酰亚胺、N-苯基马来酰亚胺；衣康酰亚胺类单体如N-甲基衣康酰亚胺、N-乙基衣康酰亚胺、N-丁基衣康酰亚胺、N-辛基衣康酰亚胺、N-2-乙基己基衣康酰亚胺、N-环己基衣康酰亚胺、N-月桂基衣康酰亚胺；琥珀酰亚胺类单体如N-(甲基)丙烯酰氧亚甲基琥珀酰亚胺、N-(甲基)丙烯酰基-6-氧六亚甲基琥珀酰亚胺、N-(甲基)丙烯酰基-8-氧八亚甲基琥珀酰亚胺；二醇类丙烯酸酯单体(acryl glycolate monomer)如聚乙二醇(甲基)丙烯酸酯、聚丙二醇(甲基)丙烯酸酯、甲氧基乙二醇(甲基)丙烯酸酯(methoxyethylene glycol(meth)acrylate)、甲氧基聚丙二醇(甲基)丙烯酸酯(methoxypolypropylene glycol (meth)acrylate)；具有杂环、卤原子或硅原子等的丙烯酸酯类单体，如(甲基)丙烯酸四氢糠酯、含氟(甲基)丙烯酸酯(fluoro(meth)acrylate)、含硅酮(甲基)丙烯酸酯(silicone(meth)acrylate)；多官能单体如己二醇二(甲基)丙烯酸酯、(聚)乙二醇二(甲基)丙烯酸酯、(聚)丙二醇二(甲基)丙烯酸酯、新戊二醇二(甲基)丙烯酸酯、季戊四醇二(甲基)丙烯酸酯、三羟甲基丙烷三(甲基)丙烯酸酯、季戊四醇三(甲基)丙烯酸酯、二季戊四醇六(甲基)丙烯酸酯、环氧丙烯酸酯、聚酯丙烯酸酯、聚氨酯丙烯酸酯、二乙烯基苯、二(甲基)丙烯酸丁酯、二(甲基)丙烯酸己酯等。此处这些共聚性单体组分可单独或多种组合使用。
在本发明中可使用的照射固化型压敏粘合剂(或能量射线固化型压敏粘合剂)(组合物)包括例如，其中包括在聚合物侧链、主链或主链末端处具有自由基反应性碳-碳双键的聚合物作为基础聚合物的内部照射固化型压敏粘合剂，和通过将UV固化型单体组分或低聚物组分共混入压敏粘合剂中制备的照射固化型压敏粘合剂。此处还可使用的热膨胀性压敏粘合剂包括例如，包含压敏粘合剂和发泡剂(特别地，热膨胀性微球)的热膨胀性压敏粘合剂。
在本发明中，在不损害本发明优点的范围内，压敏粘合剂层32可包含各种添加剂(例如，增粘剂、着色剂、增稠剂、增量剂、填料、增塑剂、防老剂、抗氧化剂、表面活性剂、交联剂等)。
交联剂没有特别限定，可使用已知的交联剂。具体地，作为交联剂，不仅可提及异氰酸酯类交联剂、环氧类交联剂、三聚氰胺类交联剂和过氧化物类交联剂，还提及脲类交联剂、金属醇盐类交联剂、金属螯合物类交联剂、金属盐类交联剂、碳二亚胺类交联剂、噁唑啉类交联剂、氮丙啶类交联剂和胺类交联剂等，异氰酸酯类交联剂和环氧类交联剂是合适的。交联剂可以单独使用或两种以上组合使用。此外，交联剂的使用量没有特别限定。
异氰酸酯类交联剂的实例包括低级脂肪族多异氰酸酯例如1，2-亚乙基二异氰酸酯、1，4-亚丁基二异氰酸酯和1，6-六亚甲基二异氰酸酯；脂环族多异氰酸酯例如亚环戊基二异氰酸酯、亚环己基二异氰酸酯、异佛尔酮二异氰酸酯、氢化甲苯二异氰酸酯和氢化苯二甲撑二异氰酸酯；和芳香族多异氰酸酯例如2，4-甲苯二异氰酸酯、2，6-甲苯二异氰酸酯、4，4′-二苯甲烷二异氰酸酯和苯二甲撑二异氰酸酯。此外，也使用三羟甲基丙烷/甲苯二异氰酸酯三聚体加合物[商品名“COLONATE L”，由Nippon Polyurethane Industry Co.，Ltd.制造]和三羟甲基丙烷/六亚甲基二异氰酸酯三聚体加合物[商品名“COLONATE HL”，由NipponPolyurethane Industry Co.，Ltd.制造]等。此外，环氧类交联剂的实例包括N，N，N′，N′-四缩水甘油基-间-苯二甲胺、二缩水甘油基苯胺、1，3-双(N，N-缩水甘油基氨甲基)环己烷、1，6-己二醇二缩水甘油醚、新戊二醇二缩水甘油醚、乙二醇二缩水甘油醚、丙二醇二缩水甘油醚、聚乙二醇二缩水甘油醚、聚丙二醇二缩水甘油醚、山梨糖醇多缩水甘油醚、甘油多缩水甘油醚、季戊四醇多缩水甘油醚、聚甘油多缩水甘油醚、脱水山梨糖醇多缩水甘油醚、三羟甲基丙烷多缩水甘油醚、己二酸二缩水甘油酯、邻苯二甲酸二缩水甘油酯、三缩水甘油基-三(2-羟乙基)异氰脲酸酯、间苯二酚二缩水甘油醚和双酚-S-二缩水甘油醚，以及在分子中具有两个以上的环氧基团的环氧类树脂。
在本发明中，代替使用交联剂或与交联剂一起使用，压敏粘合剂层也可以通过用电子束或紫外线照射交联处理。
压敏粘合剂层32例如可通过利用包括混合压敏粘合剂和任选的溶剂及其它添加剂，然后将该混合物成形为片状层的通常使用的方法形成。具体地，例如，可提及以下方法：包括将包含压敏粘合剂和任选的溶剂及其它添加剂的混合物施涂至基材31上的方法；包括施涂上述混合物至适当隔离体(如剥离纸)上以形成压敏粘合剂层32，然后将其转移(转换)至基材31上的方法；等等。
压敏粘合剂层32的厚度没有特别限定，例如，优选为约5μm至300μm，更优选5μm至200μm，进一步优选5μm至100μm，特别优选7μm至50μm。当压敏粘合剂层32的厚度在上述范围内时，能够显示适当的压敏粘合力。压敏粘合剂层可为单层或多层。
切割带3的压敏粘合剂层32对粘合剂层2的粘合力(23℃、剥离角度为180°和剥离速率为300mm/分钟)优选在0.02N/20mm至10N/20mm的范围内，更优选在0.05N/20mm至5N/20mm的范围内。当该粘合力为至少0.02N/20mm时，则在切割半导体晶片时可防止半导体芯片飞散。另一方面，当该粘合力为不超过10N/20mm时，则在拾取它们时其促进半导体芯片的拾取，并防止压敏粘合剂残留。
此外，在本发明中，可使粘合剂层2或粘贴粘合剂层的切割带1具有抗静电功能。由于该构造，能够防止电路由于以下原因导致的短路：由于在其粘合时和在剥离时静电能的产生或由于半导体晶片等通过静电能而带电。赋予抗静电功能可通过适当的方式如以下方法进行：添加抗静电剂或导电性物质至基材31、压敏粘合剂层32和粘合剂层2的方法，或在基材31上设置由电荷转移配合物(charge-transfer complex)或金属膜等组成的导电层的方法。作为这些方法，优选其中难以产生具有改变半导体晶片品质风险的杂质离子的方法。为了赋予导电性和改进导热性等的目的而共混的导电性物质(导电性填料)的实例包括银、铝、金、铜、镍或导电性合金等的球形、针形或薄片形金属粉末；金属氧化物如氧化铝；无定形炭黑和石墨。然而，从不具有漏电性的观点，粘合剂层2优选非导电性的。
此外，半导体器件生产用膜40可以以卷绕成卷形物(roll)的形式形成或可以以将片材(膜)层压的形式形成。在这点上，处于卷绕成卷形物的状态或形式的半导体器件生产用膜40可由基材31、在基材31的一个表面上形成的压敏粘合剂层32、在压敏粘合剂层32上形成的粘合剂层2，和在基材31的另一表面上形成的可剥离处理层(后表面处理层)构成。
此外，粘贴粘合剂层的切割带1的厚度(粘合剂层的厚度以及包括基材31和压敏粘合剂层32的切割带的厚度的总厚度)可选自例如8μm至1,500μm的范围内，其优选20μm至850μm、更优选31μm至500μm、特别优选47μm至330μm的范围内。
粘合剂层2的厚度相对于切割带3的压敏粘合剂层32的厚度的比没有具体限定。例如，该比例可在(粘合剂层2的厚度/切割带3的压敏粘合剂层32的厚度)＝150/5至3/100、优选100/5至3/50、更优选60/5至3/40的范围内适当选择。当粘合剂层2的厚度相对于切割带3的压敏粘合剂层32的厚度的比例为至少3/100时，则能够防止两者之间的粘合力过高。另一方面，当该比例为不超过150/5时，则可防止粘合力过低。
粘合剂层2的厚度相对于切割带3的厚度(基材31和压敏粘合剂层32的总厚度)的比例没有具体限定。例如，该比例可在(粘合剂层2的厚度)/(切割带3的厚度)＝150/50至3/500、优选100/50至3/300、更优选60/50至3/150的范围内适当选择。当粘合剂层2的厚度相对于切割带3的厚度的比例为至少3/500时，则其有利于该带的拾取。另一方面，当该比例为不超过150/50时，则防止切割时侧面残余物(side residue)的增加。
在这点上，通过控制粘合剂层2的厚度相对于切割带3的压敏粘合剂层32的厚度的比例或粘合剂层2的厚度相对于切割带的厚度(基材31和压敏粘合剂层32的总厚度)的比例，在切割步骤的切割性和在拾取步骤的拾取性等能够得到改进，并且由此从半导体晶片的切割步骤至半导体芯片的倒装芯片接合步骤均能够有效地利用本发明的半导体器件生产用膜。
(半导体器件生产用膜的生产方法)
使用示于图1A和1B的半导体器件生产用膜40为例描述根据本发明的半导体器件生产用膜的生产方法。该实施方案的半导体器件生产用膜40的生产方法包括以下步骤：隔离膜粘贴的膜的制备步骤，所述隔离膜粘贴的膜包括隔离膜42和粘贴粘合剂层的切割带1，所述粘贴粘合剂层的切割带1各自包含切割带3和层压于切割带3上的粘合剂层2，并且切割带3经由用作粘贴面的粘合剂层2层压于隔离膜42上；和根据对应于所述膜要粘贴的半导体晶片的尺寸切割隔离膜粘贴的膜的步骤。在该方法中，从切割带3侧将所述膜切割为不超过隔离膜42厚度的2/3的深度。
首先，基材31可通过常规已知的成膜方法形成。成膜方法的实例包括压延成膜法、在有机溶剂中的流延法、在严格密闭体系中的膨胀挤出法、T-膜挤出法、共挤出法和干法层压法。
接着，将压敏粘合剂组合物施涂至基材31，并在其上干燥(任选地，在加热下交联)以形成压敏粘合剂层32。施涂体系包括辊涂、丝网涂布(screen coating)和凹版涂布(gravure coating)等。压敏粘合剂层组合物可直接施涂至基材31以在基材31上形成压敏粘合剂层32；或可将压敏粘合剂组合物施涂至表面已润滑处理的剥离片材等上以在其上形成压敏粘合剂层32，并可将压敏粘合剂层32转移至基材31上。于是，切割带3使压敏粘合剂层32形成于基材31上来形成。
另一方面，将用于形成粘合剂层2的形成材料施涂至剥离片材上以形成在干燥后具有规定厚度的涂层，然后在规定条件下(在需要热固化的情况下任选加热，和干燥)将其干燥以形成涂层。随后，在规定条件下干燥涂层由此形成粘合剂层2。
接着，粘合剂层2根据要粘贴于其上的半导体晶片的形状冲切(blanked out)出来，然后粘贴至切割带3。随后，将其经由用作粘贴面的粘合剂层2层压于隔离膜42上，由此给出隔离膜粘贴的膜。隔离膜42可根据已知的成膜方法生产。成膜方法包括例如，压延成膜法、在有机溶剂中的流延法、在严格密闭体系中的膨胀挤出法、T-膜挤出法、共挤出法和干法层压法。
接着，根据对应于所述膜要粘贴的半导体晶片的尺寸切割隔离膜粘贴的膜。在该步骤中，从切割带3侧将所述膜切割至不超过隔离膜42厚度的2/3的深度(参见图1B)。在此，获得半导体器件生产用膜40，其中隔离膜42围绕切割带3的外周切割并且切口的深度为不超过隔离膜42厚度的2/3。不冲切，粘合剂层2可原样直接粘贴至切割带3，然后仍然原样直接层压在隔离膜上，其后，隔离膜粘贴的膜可根据对应于所述膜要粘贴的半导体晶片的尺寸切割。在此情况下，切割粘合剂层2和切割带3，同时形成切口44。
形成切口的方法不具体限定。例如，此处可采用的为使用旋转体(rotary)的方法、使用冲切刀(例如，汤姆森刀(Thomson blade))的方法、激光加工法。总之，由于增加要形成的切口深度的精确度水平，旋转体是有利的。在使用冲切刀的情况下，优选地，在刀内部和/或外部设置间隔体(spacer)。在此，可增加要形成的切口深度的精确度水平。此外，迄今，在隔离膜仅用冲切刀切割的场合下，精确度低，并且在一些情况下，可经常形成具有大于隔离膜厚度2/3的深度的切口。与此相反，在其它一些情况下刀不能到达隔离膜，并且也不能切割切割带。然而，当使用旋转体时或当在刀内部和/或外部设置隔离膜时，则可增加要形成的切口深度的精确度水平。
(半导体晶片)
半导体晶片不特别限制，只要其为已知的或通常使用的半导体晶片即可，可在由各种材料制成的半导体晶片中适当地选择和使用。在本发明中，作为半导体晶片，可适当地使用硅晶片。
(半导体器件的生产方法)
该实施方案的半导体器件的生产方法参考图2A至2D描述。图2A至2D为示出使用该实施方案的粘贴粘合剂层的切割带的半导体器件的生产方法的一个实例的横截面示意图。
在半导体器件生产方法中，使用半导体器件生产用膜40以生产半导体器件。具体地，该方法至少包括将隔离膜42从半导体器件生产用膜40剥离的步骤和粘贴半导体晶片至粘合剂层2的步骤。
首先，制备如图1A和图1B所示的半导体器件生产用膜40，并将隔离膜42从半导体器件生产用膜40剥离。如上所述，在半导体器件生产用膜40中，处理隔离膜42以具有形成于其中的切口，并且隔离膜42的切口深度为不超过隔离膜42厚度的2/3。因此，当隔离膜42从半导体器件生产用膜40剥离时，防止隔离膜42从其切口撕裂。剥离速率可为1至100mm/秒。
[安装步骤]
如图2A所示，将半导体晶片4粘贴至粘贴粘合剂层的切割带1的粘合剂层2上，并通过粘合固定于其上(安装步骤)。此时，粘合剂层2处于未固化状态(包括半固化状态)。将粘贴粘合剂层的切割带1粘贴至半导体晶片4的背面。半导体晶片4的背面是指相对于电路面的面(也称作非电路面、非电极形成面等)。粘贴方法不特别限定，但是优选通过压接的方法。通常在用加压装置如加压辊加压的同时进行压接。
(切割步骤)
接着，如图2B所示，切割半导体晶片4。从而，将半导体晶片4切断成规定尺寸并个体化(成形为小片)，以生产半导体芯片5。所述切割根据常规方法例如，从半导体晶片4的电路面侧进行。另外，本步骤可采取例如形成达到粘贴粘合剂层的切割带1的切口的称作完全切断的切断方法。用于本步骤的切割设备没有特别限定，可使用常规已知的设备。此外，由于半导体晶片4通过具有粘合剂层2的粘贴粘合剂层的切割带1粘合并固定，可抑制芯片破裂和切屑飞散，以及还可抑制半导体晶片4破损。在这点上，当粘合剂层2由包含环氧树脂的树脂组合物形成时，即使当将其通过切割切断时，也能够抑制或防止在切断面处发生粘合剂从粘合剂层挤出。结果，可抑制或防止切断面自身的再粘贴(粘连(blocking))，从而可进一步方便地进行以下要描述的拾取。
在扩展粘贴粘合剂层的切割带1的情况下，扩展(expansion)可使用常规已知的扩展设备进行。所述扩展设备具有能够推动粘贴粘合剂层的切割带1向下通过切割环的环形外环，和直径小于外环并支撑粘贴粘合剂层的切割带的内环。由于该扩展步骤，可以防止相邻的半导体芯片在以下要描述的拾取步骤中通过彼此接触而损坏。
(拾取步骤)
为了收集粘合并固定至粘贴粘合剂层的切割带1的半导体芯片5，如图2C所示进行半导体芯片5的拾取以将半导体芯片5与粘合剂层2一起从切割带3剥离。拾取方法没有特别限定，可采用常规已知的各种方法。例如，可提及包括用针状物从粘贴粘合剂层的切割带1的基材31侧向上推动各半导体芯片5，并用拾取设备拾取推起的半导体芯片5的方法。在这点上，拾取的半导体芯片5的背面用粘合剂层2保护。
(倒装芯片连接步骤)
如图2D所示，拾取的半导体芯片5通过倒装芯片接合法(倒装芯片安装法)固定于被粘物6如基板。具体地，以半导体芯片5的电路面(也称为正面、电路图案形成面、电极形成面等)与被粘物6相对的形式，根据常规方式将半导体芯片5固定于被粘物6上。例如，使在半导体芯片5的电路面侧形成的凸块51与粘贴至被粘物6的连接垫的连结用导电性材料61(如焊料)接触，并在加压下熔融导电性材料61，由此能够确保半导体芯片5和被粘物6之间的电连接，并能够将半导体芯片5固定于被粘物6上(倒装芯片接合步骤)。此时，在半导体芯片5和被粘物6之间形成间隙并且间隙之间的距离通常为约30μm至300μm。在这点上，在将半导体芯片5倒装芯片接合(倒装芯片连接)至被粘物6之后，重要的是将半导体芯片5和被粘物6的相对面以及间隙洗涤，然后将封装材料(如封装树脂)填充入该间隙中以进行封装。
作为被粘物6，可使用各种基板如引线框和电路板(如布线电路板)。基板的材料没有特别限定，可提及陶瓷基板和塑料基板。塑料基板的实例包括环氧基板、双马来酰亚胺三嗪基板和聚酰亚胺基板。
在倒装芯片接合步骤中，凸块和导电性材料的材料没有特别限定，其实例包括焊料(合金)如锡-铅类金属材料、锡-银类金属材料、锡-银-铜类金属材料、锡-锌类金属材料和锡-锌-铋类金属材料，以及金类金属材料和铜类金属材料。
此外，在倒装芯片接合步骤中，将导电性材料熔融以连接半导体芯片5的电路面侧的凸块和在被粘物6表面上的导电性材料。导电性材料熔融时的温度通常为约260℃(例如，250℃至300℃)。通过形成具有环氧树脂等的粘合剂层，可使本发明的粘贴粘合剂层的切割带具有能够承受在倒装芯片接合步骤中的高温的耐热性。
在本步骤中，优选洗涤半导体芯片5和被粘物6之间的相对面(电极形成面)以及间隙。在洗涤时使用的洗涤液没有特别限定，其实例包括有机洗涤液和水性洗涤液。在本发明的粘贴粘合剂层的切割带中的粘合剂层具有对洗涤液的耐溶剂性，并且对这些洗涤液基本不具有溶解性。因此，如上所述，可采用各种洗涤液作为该洗涤液，并可通过任何常规方法而无需任何特别的洗涤液实现该洗涤。
接着，进行封装步骤以封装在倒装芯片接合的半导体芯片5和被粘物6之间的间隙。封装步骤使用封装树脂进行。在此时的封装条件不特别限定，但是封装树脂的固化通常在175℃下进行60至90秒。然而，在本发明中，不限于此，例如，固化可在165至185℃的温度下进行几分钟。通过在该步骤中的热处理，不仅封装树脂固化而且粘合剂层2也与此同时热固化。因此，封装树脂和粘合剂层2二者都固化并随着热固化的过程收缩。结果，通过粘合剂层2的固化收缩可消除或松弛由于封装树脂的固化收缩给予半导体芯片5的应力。此外，在该步骤中，粘合剂层2可完全或几乎完全地热固化并可优异地紧密粘合性地粘贴至半导体元件的背面。此外，即使当所述膜处于未固化状态时，根据本发明的粘合剂层2也可与封装步骤中的封装树脂一起热固化，因此不需要新添加用于热固化粘合剂层2的步骤。
封装树脂没有特别限定，只要该材料为具有绝缘性的树脂(绝缘树脂)即可，可在已知的封装材料如封装树脂中适当选择和使用。封装树脂优选具有弹性的绝缘树脂。封装树脂的实例包括含环氧树脂的树脂组合物。作为环氧树脂，可提及以上示例的环氧树脂。另外，由包含环氧树脂的树脂组合物组成的封装树脂，除了环氧树脂之外，还可包含除了环氧树脂之外的热固性树脂(如酚醛树脂)或热塑性树脂。此外，也可利用酚醛树脂作为环氧树脂用固化剂，作为该酚醛树脂，可提及以上示例的酚醛树脂。
上述实施方案包括含层压在切割带上的粘合剂层的粘贴粘合剂层的切割带，并且包括用隔离膜层压的粘贴粘合剂层的切割带的半导体器件生产用膜。然而，在本发明的半导体器件生产用膜中，可不层压粘合剂层。具体地，本发明的半导体器件生产用膜可包括隔离膜和多个以预定间隔层压于隔离膜上的切割带。在此情况下，半导体器件生产用膜的生产方法包括以下步骤：隔离膜粘贴的膜的制备步骤，所述隔离膜粘贴的膜包括层压于隔离膜上的切割带；根据对应于所述膜要粘贴的半导体晶片的尺寸切割隔离膜粘贴的膜的步骤，其中从切割带侧切割所述膜为不超过隔离膜厚度的2/3的深度。通过使用其中将切割带以预定间隔层压于隔离膜上的半导体器件生产用膜的半导体器件的生产方法，可至少包括从半导体器件生产用膜剥离隔离膜的步骤和粘贴半导体晶片至切割带的步骤。粘贴半导体晶片至切割带的步骤可伴随着例如，切割半导体晶片的步骤、拾取通过切割获得的半导体芯片的步骤和倒装芯片接合半导体芯片至被粘物的步骤，由此生产半导体器件。
根据使用粘贴粘合剂层的切割带1制造的半导体器件(倒装芯片安装的半导体器件)，将粘合剂层粘贴至半导体芯片背面上，由此可以以优良的可见度实施激光标识。特别地，即使当标识方法为激光标识法时，激光标识也能够以优良的对比度实施，并且可以观察通过具有良好可见度地激光标识实施的各种信息(例如，文字信息和图形信息)。在激光标识时，可利用已知的激光标识设备。此外，作为激光器，可以利用各种激光器如气体激光器、固态激光器和液体激光器。具体地，作为气体激光器，可利用任何已知的气体激光器而没有特别限制，但二氧化碳激光器(CO2激光器)和准分子激光器(ArF激光器、KrF激光器、XeCl激光器、XeF激光器等)是合适的。作为固态激光器，可利用任何已知的固态激光器而没有特别限定，但YAG激光器(如Nd:YAG激光器)和YVO4激光器是合适的。
由于使用本发明的粘贴粘合剂层的切割带生产的半导体器件为通过倒装芯片安装法安装的半导体器件，所以该器件与通过模片接合安装法安装的半导体器件相比具有薄型化和小型化的形状。因此，可适当采用半导体器件作为各种电子器件和电子部件或其材料和构件。具体地，作为利用本发明的倒装芯片安装的半导体器件的电子器件，可提及所谓的“移动电话”和“PHS”，小型计算机[例如，所谓的“PDA”(手持终端)，所谓的“笔记本尺寸的个人计算机”，所谓的“Net Book(商标)”和所谓的“可穿戴计算机”等]，具有“移动电话”和计算机集成形式的小型电子器件，所谓的“Digital Camera(商标)”，所谓的“数码摄像机”，小型电视机，小尺寸游戏机，小型数字音频播放机，所谓的“电子记事本”，所谓的“电子词典”，用于所谓的“电子书”的电子器件终端，移动电子器件(可携带电子器件)如小型数字型手表等。不必说，也可提及除了移动器件之外的电子器件(固定型电子器件等)，例如所谓的“桌面个人计算机”、薄型电视机、用于记录和复制的电子器件(硬盘录像机(hard diskrecorders)、DVD播放机等)、投影仪和微型机等。此外，电子部件或用于电子器件和电子部件的材料和构件不特别限制，其实例包括用于所谓“CPU”的部件和用于各种记忆器件(所谓的“存储器”、硬盘等)的构件。
上述实施方案是在生产倒装芯片型半导体器件中使用半导体器件生产用膜。然而，本发明的半导体器件生产用膜不限于该实施方案，但可用于生产除倒装芯片型半导体器件外的其它半导体器件中。例如，在从半导体器件生产用膜剥离隔离膜之后，可将粘贴粘合剂层的切割带中的粘合剂层在另外所述膜的使用中粘贴至半导体晶片(半导体芯片)的表面。在此情况下，半导体器件生产用膜具有的粘贴粘合剂层的切割带可用作普通已知的切割/模片接合膜。
实施例
以下将详细地示例性描述本发明的优选实施例。然而，本发明不限于以下实施例，除非其超出本发明的要旨。此外，除非另外说明，在各实施例中的份为重量基准。
实施例1
<粘合剂层的制备>
基于100份包含丙烯酸乙酯和甲基丙烯酸甲酯作为主要组分的丙烯酸酯类聚合物(商品名“PARACRON W-197CM”，由Negami Chemical Industrial Co.，Ltd.制造)，将113份环氧树脂(商品名“EPICOAT 1004”，由JER Co.，Ltd.制造)、121份酚醛树脂(商品名“MILEXXLC-4L”，由Mitsui Chemicals，Inc.制造)、246份球形二氧化硅(商品名“SO-25R”，由Admatechs Co.Ltd.制造)、5份染料1(商品名“OIL GREEN 502”，由Orient ChemicalIndustries Co.，Ltd.制造)和5份染料2(商品名：“OIL BLACK BS”，由Orient ChemicalIndustries Co.，Ltd.制造)溶解于甲乙酮中，以制备具有固体浓度为23.6重量％的糊剂组合物溶液。
将该糊剂组合物溶液施涂至已进行硅酮剥离处理的、具有厚度为50μm的聚对苯二甲酸乙二酯膜的隔离膜上，然后在130℃下干燥2分钟，以制备具有层压于隔离膜上的厚度(平均厚度)为20μm的粘合剂层A的膜A。
<半导体器件生产用膜的制备>
1.隔离膜粘贴的膜的制备：
使用手动辊，将膜A粘贴至切割带(商品名：″V-8-T″，由Nitto Denko Corporation制造；基材的平均厚度：65μm，压敏粘合剂层的平均厚度：10μm)的压敏粘合剂层上，从而制备具有层压于隔离膜上的粘贴粘合剂层的切割带的隔离膜粘贴的膜A。
2.预切割：
使用圆形汤姆逊刀(Thomson blade)，预切割隔离膜粘贴的膜A以给出半导体器件生产用膜。预切割深度通过在汤姆逊刮板内部和外部引入间隔体控制。具体地，引入间隔体以使隔离膜中切割深度可为13μm。
在实施例1的半导体器件生产用膜中，粘合剂层的厚度(平均厚度)为20μm。在切割带(商品名：″V-8-T″，由Nitto Denko Corporation制造)中，基材的厚度(平均厚度)为65μm，压敏粘合剂层的厚度(平均厚度)为10μm，带的总厚度为75μm。因此，在实施例1的半导体器件生产用膜中，切割带的粘合剂层厚度与压敏粘合剂层厚度的比例(平均厚度比)为20/10；和粘合剂层厚度与切割带厚度(基材和压敏粘合剂层的总厚度)的比例(平均厚度比)为20/75。
实施例2
实施例2的半导体器件生产用膜以与实施例1相同的方式制备，然而，其中引入间隔体以使在预切割时隔离膜中的切割深度可为20μm。
比较例1
比较例1的半导体器件生产用膜以与实施例1相同的方式制备，然而，其中引入间隔体以使在预切割时隔离膜中的切割深度可为27μm。
<评价>
如下测试实施例1、实施例2和比较例1的半导体器件生产用膜的其隔离膜剥离性。
将半导体晶片(直径：8英寸，厚度：0.6mm；硅镜面晶片)在其背面上抛光，从而给出用作工件的厚度为0.2mm的镜面晶片。在从半导体器件生产用膜剥离隔离膜的情况下，将镜面晶片(工件)在70℃下通过辊压接合粘贴至粘合剂层上。半导体晶片抛光条件和粘贴条件如下。
(半导体晶片磨削(grinding)条件)
磨削设备：商品名″DFG-8560″，由DISCO Corporation制造
半导体晶片：8英寸直径(将背面从厚度为0.6mm磨削至厚度为0.2mm)
(粘贴条件)
粘贴设备：商品名“MA-3000III”，由Nitto Seiki Co.，Ltd.制造
粘贴速度：10mm/分钟
粘贴压力：0.15MPa
粘贴时的阶段温度(stage temperature)：70℃
在晶片安装中，晶片可安装性的评价如下。将从中已良好地剥离隔离膜的样品评级为″良好″；将不能从中良好地剥离隔离膜的样品评级为″差″。结果示于表1中。
表1
从表1中，在实施例1和2中的半导体器件生产用膜中隔离膜良好地被剥离。另一方面，在比较例1的半导体器件生产用膜中，隔离膜从切口部分(切口)破裂，并不能良好地剥离。
虽然已详细地并参考其具体实施方案描述本发明，但对于本领域技术人员而言，其中可进行各种变化和改进而不背离其范围将显而易见。
本申请基于2010年7月28日提交的日本专利申请2010-169556，在此将其全部内容引入作为参考。

Claims (1)

1.一种半导体器件生产用膜，其包括：
隔离膜；和
多个粘贴粘合剂层的切割带，所述多个粘贴粘合剂层的切割带各自包括切割带和层压在所述切割带上的粘合剂层，所述多个粘贴粘合剂层的切割带以所述粘合剂层粘贴至所述隔离膜的方式以预定间隔层压在所述隔离膜上，
其中所述隔离膜具有沿所述切割带的外周形成的切口，和
其中所述切口的深度为不超过所述隔离膜厚度的2/3，
所述粘合剂层添加有着色剂，并且粘贴到具有倒装芯片安装的半导体器件的半导体芯片的背面上，且
所述粘合剂层的直径小于所述切口的直径。
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