CN102341895B - 半导体芯片及半导体装置 - Google Patents

半导体芯片及半导体装置 Download PDF

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Publication number
CN102341895B
CN102341895B CN201080010283.8A CN201080010283A CN102341895B CN 102341895 B CN102341895 B CN 102341895B CN 201080010283 A CN201080010283 A CN 201080010283A CN 102341895 B CN102341895 B CN 102341895B
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electrically conductive
conductive film
semiconductor chip
coating
deielectric
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CN102341895A (zh
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酒井启之
福田健志
宇治田信二
河井康史
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

提供一种半导体芯片，是将Si类半导体作为基板的MMIC等半导体芯片，具有低损耗的传送线路，容易连接到安装用电路基板上，且能够确保稳定的GND电位。该半导体芯片是倒装的半导体芯片(10)，具备：Si基板(11)；形成在Si基板(11)的主面上的集成电路(12)；形成在集成电路(12)上方的介质膜(16)；以及形成在介质膜(16)上表面的接地用导体膜(17)，集成电路(12)包括由用于传送该集成电路(12)中的信号的信号线(15)构成的布线层(13a)，由信号线(15)、介质膜(16)及导体膜(17)构成微带线。

Description

半导体芯片及半导体装置
技术领域
本发明涉及半导体芯片、及将该半导体芯片倒装(flip chip)到安装用电路基板上的半导体装置，特别涉及具备传送线路的单片微波集成电路(MMIC)等高频半导体集成电路。
背景技术
随着以移动电话为首的通信设备的发展，使用频率从几百MHz到几GHz的微波、进而从几十GHz到超过100GHz的毫米波的电路装置受到关注。为了得到能够进行更大容量的通信的宽频带，或进行更快速的信号处理，所要求的电路的动作频率越来越高。
由于频率增高时，信号波的波长接近电路元件的实际尺寸，所以已经难以将电路元件作为集总参数元件使用，需要在设计中将电路的尺寸本身作为分布参数元件编入。此外，由于电路元件的形状、安装偏差直接导致频率特性的偏差，所以若安装大量部件，则难以使整个电路装置的特性收敛在规格内。
于是，在这种高频电路中，采用了将作为有源元件的晶体管和传送线路等无源元件一并制作到同一半导体基板上的单片微波集成电路(MMIC；monolithic microwave IC)的技术。通过将包括无源元件在内的大量电路部件一并制作到基板上，能够削减部件个数，并且，通过使用能够进行正确的微细加工的半导体工艺，从而即使波长变小，仍能够正确地再现特性。
作为这种MMIC用的半导体，在此之前，主要使用以GaAs为首的化合物半导体。主要理由是，由于电子迁移率高而使晶体管具有优异的高频特性，能够得到低损耗、高绝缘性的基板。但是，这种化合物半导体相比于通常使用的Si类半导体(以Si为主成分的半导体)，不但基板本身的价格高，而且相比于批量生产的现有的硅工艺，制造工艺尚未成熟的部分较多，从成品率来看，也存在高成本的问题。
近年来，随着微细化技术的发展，Si类半导体的工作频率明显提高，有报告指出，最先进的微细MOS晶体管和SiGe异质双极晶体管(heterobipolar transister)的最高截止频率(ft)和最高振荡频率(fmax)超过100GHz而达到200GHz。由此，各地纷纷进行将以往使用昂贵的化合物半导体制作的微波～毫米波带的MMIC替换为低成本的的Si类半导体的研究开发。
但是，在Si类半导体中，存在难以制作具有像GaAs等化合物半导体那样的优异的绝缘性的基板。即，在GaAs等化合物半导体中，例如，如图8所示，将半绝缘性的基板90本身作为电介质，在基板90上形成线路91，对背面进行金属喷镀(metallize)而形成GND层(接地导体)92，从而构成微带线(Microstrip Line)，能够制作低损耗的电路。但是，若在Si基板上采用相同的结构，则由于通常Si基板具有导电性，所以如果从在形成于Si基板上的线路产生的电磁场侵入到基板内，线路损耗增大。
为了解决该问题，以往使用硅集成电路的多层布线技术，例如，如图9所示，将形成在Si基板93上的第一层布线96作为接地导体(GND层)，将最上层布线94作为信号线，构成微带线，以便从线路产生的电磁场不会侵入到Si基板93内。由此，能够消除由Si基板93的导电性引起的电介质损耗，然而在该方法中，作为电介质使用的布线的层间绝缘膜95相比于半导体基板93非常薄，所以为了得到与将半导体基板93作为电介质使用时相同的特性阻抗，需要减小信号线的线宽。然而，若线宽减小，则信号线的导体损耗增大，其结果，作为传送线路的损耗比化合物半导体大。
在此，为了降低导体损耗，有效的是增大信号线的线宽，然而为了在不降低阻抗的状态下实现，需要增大作为电介质的布线的层间绝缘膜的厚度。作为这种技术的现有例，例如，如专利文献1中所示，堆积与通常的层间绝缘膜不同的BCB(苯并环丁烯)等介质膜，厚度达到几μm～几十μm，将其作为电介质来构成微带线。通过增大介质膜的厚度来增大实现相同阻抗的信号线的线宽，降低导体损耗，进而通过在Si基板上设置GND层(GNDplane)来抑制电磁场侵入到Si基板，能够消除电介质损耗。由此，实现将Si类半导体作为基板的MMIC(下面又称为“Si-MMIC”)。
在先技术文献
专利文献
专利文献1：日本特开平9-17959号公报
发明概要
发明要解决的问题
然而，即使实施专利文献1中公开的改良，实际将Si-MMIC安装到电路基板上而构成电路装置的情况下，会出现新的问题。
图10是示意性地示出将专利文献1中公开的现有的Si-MMIC安装到安装用的电路基板98上时的剖面结构的图。MMIC上的信号线与电路基板上的信号线通常用直径为25μm左右的金属线连接。并且，由于MMIC上的GND层96通常与Si基板93绝缘，所以与信号线相同地，需要在电路基板98上的GND图案上进行线接合(wire bonding)。
在此，由该图可知，为了实现MMIC上的GND与电路基板98的GND的连接而存在有限长度的引线97，所以尤其在毫米波那样的高频中，不能忽略该引线97的电感。MMIC上的GND层96处于经由电感悬浮的状态，本应供给稳定电位的GND有时会根据信号而发生较大变动。由此，在安装后的整个电路上形成反馈回路(feedback loop)，引起不必要的振荡。
另外，在使用了现有的GaAs等化合物半导体的MMIC中，由于将基板本身作为电介质使用，所以GND层位于基板的下表面，能够在与电路基板之间得到稳定的连接。而且，电路上的GND布线通常经由通孔与背面GND连接，所以能够将寄生电感抑制得较小。如上述现有技术所示，在Si-MMIC中，由于GND位于基板的上表面，所以无论如何都会在MMIC的GND与电路基板的GND的连接中产生较大的寄生电感。
像这样，在Si-MMIC中，在位于MMIC基板上表面的GND层与电路基板的连接中无论如何都会产生寄生电感，其结果，MMIC上的GND不稳定，特性变动，而且容易引起振荡等。
发明内容
本发明是鉴于这种情况而提出的，其目的在于，提供一种半导体芯片、及将这种半导体芯片倒装到电路基板上的半导体装置，该半导体芯片是将Si类半导体作为基板的MMIC等半导体芯片，具有低损耗的传送线路，容易连接到安装用电路基板上，且能够确保稳定的GND电位。
解决问题的于段
达到上述目的本发明的第一方式，为倒装半导体芯片，具备：硅基板；形成在所述硅基板的主面上的集成电路；形成在所述集成电路上方的介质膜；以及形成在所述介质膜上表面的接地用导体膜，所述集成电路包括由用于传送该集成电路中的信号的信号线构成的布线层，由所述信号线、所述介质膜及所述导体膜构成微带线。
由此，由于在最上表面形成微带线的GND层(导体膜)，所以将该半导体芯片反转，经由凸点将该GND层与安装用电路基板的GND连接(倒装)，从而能够使微带线的GND层确实地与GND连接。
并且，本发明的第二方式，为倒装半导体芯片，具备：硅基板；形成在所述硅基板的主面上的集成电路；形成在所述集成电路上方的接地用第一导体膜；形成在所述第一导体膜上方的介质膜；布线层，形成在所述介质膜中，由用于传送该集成电路中的信号的信号线构成；以及形成在所述介质膜上表面的接地用第二导体膜，由所述信号线、所述电介质、所述第一导体膜、及第二导体膜构成带状线。
由此，由于在最上表面形成带状线的GND层(第二导体膜)，所以将该半导体芯片反转，通过凸点将该GND层与安装用电路基板的GND连接(倒装)，从而能够使带状线的GND层确实地与GND连接。
另外，本发明不仅能够作为半导体芯片实现，还能够作为将这种半导体芯片经由凸点与安装用电路基板连接而得到的作为组件的半导体装置实现。
发明效果
通过本发明，能够实现一种半导体芯片、及将这种半导体芯片倒装到电路基板上的半导体装置，该半导体芯片是将Si类半导体作为基板的MMIC等半导体芯片，具有低损耗的传送线路，容易连接到安装用电路基板上，且能够确保稳定的GND电位。
由此，能够实现价格比由化合物半导体构成的MMIC低的MMIC，在便携电话等各种小型通信设备普及的当今，实用价值非常高。
附图说明
图1(a)是本发明的第一实施方式的半导体芯片的剖视图，图1(b)是本发明的第一实施方式的半导体装置的剖视图。
图2是示出上述半导体芯片的微带线周边的电场强度的图。
图3是示出改变了上述半导体芯片的基板电阻时的微带线的线路损耗的图。
图4是示出上述半导体芯片的制造方法的图。
图5(a)是本发明的第二实施方式的半导体芯片的剖视图，图5(b)是本发明的第二实施方式的半导体装置的剖视图。
图6是第二实施方式的变形例的半导体芯片的剖视图。
图7是示出本发明的半导体芯片的上表面的立体图。
图8是示出将现有的化合物半导体用作基板的微带线的图。
图9是示出将现有的Si用作基板的微带线的图。
图10是示出将现有的Si-MMIC安装到电路基板上的状态的图。
具体实施方式
下面，使用附图，详细说明本发明的实施方式。
(第一实施方式)
首先，说明本发明的第一实施方式的半导体芯片及半导体装置。
图1(a)是本发明的第一实施方式的半导体芯片10的剖视图，图1(b)是将该半导体芯片10倒装到安装用电路基板22上的图，即，本发明的第一实施方式的半导体装置20的剖视图。另外，方便起见，在图1(a)中，除了半导体芯片10之外，还一并示出倒装用凸点(bump)21。
如图1(b)所示，图1(a)所示的半导体芯片10是在上下反转的状态下经由凸点21倒装到安装用电路基板22上的Si-MMIC，具备：Si基板11；形成在Si基板11主面上的集成电路12；形成在集成电路12上方的介质膜16；以及形成在介质膜16上表面的接地用导体膜17。在此，集成电路12包括电路层14和布线层13a～l3c，布线层13a～l3c由用于传送该电路层中的信号的信号线15构成，由该信号线15、介质膜16以及导体膜17构成所谓的微带线。另外，在图1(a)和图1(b)中，省略了后述的制造方法的说明图(图4(a)～(h))中示出的详细的构成要素(将布线层13a中的GND布线及保护膜、介质膜16贯穿的接线柱(post)(接触件)等)的图示。
Si基板11是由Si类半导体构成的基板，优选电阻率为10Ωcm以上的Si基板，更优选电阻率为100Ωcm以上的Si基板。
集成电路12由电路层14和布线层13a～13c构成，电路层14由形成在Si基板11上表面的晶体管等电路元件构成，布线层13a～13c由用于传送该电路层14中的信号的Al或Cu等信号线15构成。布线层13a～13c是信号线隔着SiO2、SiN等绝缘膜形成为多层的多层布线层。
另外，虽然在本图中，在集成电路12内只设有一个电路层14，然而本发明不限于一层电路层，也可以具有多层电路层。并且，在本图中，只示出了布线层13a～13c之中的最上层的布线层13a上的信号线15，其他布线层13b及13c上的信号线省略图示。在各个布线层13a～13c上，不仅设置有独立的信号线，还设置有与上层或下层的布线层的信号线连接的信号线。并且，也可以在最上层的布线层13a中包括与电路层14的元件连接的电极焊盘(pad)用导体膜。这些信号线及电极焊盘用导体膜相当于构成微带线的传送线路。
介质膜16相当于构成微带线的电介质，是介电损耗小且能够形成厚膜的树脂膜，优选含有例如BCB、聚酰亚胺、聚四氟乙烯或聚苯醚的膜，或将由第一材料构成的粒子分散到第二材料中而形成的纳米复合膜。另外，作为纳米复合膜，优选粒子的粒径为1nm以上且200nm以下，该材料优选含有钛酸锶、钛酸锶钡、氧化铪、铝酸铪或锆钛酸铅的陶瓷。
导体膜17是相当于构成微带线的GND层的、由Al、Cu、Au等或含有这些元素的合金等形成的膜，经由凸点21与安装用电路基板22上的GND图案连接。
这种半导体芯片10的制造方法大体由2个工序构成。即，由在Si基板11上形成集成电路12的通常的硅芯片制造工序(所谓的Si工序)和之后形成介质膜16及导体膜17的再布线工序(所谓的后处理)构成。另外，由于布线层13a～13c在Si工序中形成，所以又称为内层布线层。
具有这种结构的本实施方式的半导体芯片10的特征在于，由信号线15、介质膜16及导体膜17构成微带线。在此，“构成微带线”是指具有在信号线与导体膜之间夹持电介质的结构，更严谨地说，是指以使微带线的特性阻抗与该传送线路所要求的值大体一致的方式决定参数(信号线15的厚度及宽度、介质膜16的介电常数及厚度等)，该参数决定微带线的特性阻抗。
在本实施方式的半导体芯片10中，与现有MMIC上的微带线相比，信号线15和导体膜17的上下位置颠倒，通过将其反转后倒装到安装用电路基板22上，从而能够将位于半导体芯片10的最上表面上的导体膜l7经由小的凸点21直接连接到安装用电路基板22的GND上。由此，在将导体膜17连接到GND上的位置(在此为凸点21)处的电感被抑制得很小，构成微带线的GND层(在此为导体膜17)可靠地接地，避免不必要的振荡。
在此，为了降低导体损耗，优选为构成微带线的信号线尽量厚。因此，作为构成微带线的信号线，除了最上层布线(在此为布线层13a处的布线)之外，将其下层的布线层(例如布线层13b)重叠使用。此外，也可以将在焊盘部中使用的Al等焊盘用导体膜重叠使用。
接着说明，作为构成本实施方式的半导体芯片10的Si基板11的基板电阻(电阻率)优选为10Ωcm以上、更优选为100Ωcm以上的意义。
如上所述，微带线的特性阻抗主要由信号线15的宽度W、介质膜16的厚度h、及介质膜16的介电常数ε决定。在保持相同的特性阻抗的状态下，为了增大信号线宽度W而降低导体损耗，需要增大介质膜16的膜厚h，为此优选介质膜16为较厚。但是，在本实施方式中，与现有的Si-MMIC上的微带线不同，Si基板11并未被电屏蔽。因此，虽然来自信号线15的电力线大部分以GND层(导体膜17)为终端，然而一部分会侵入到位于反方向的Si基板11内。
图2是示出用电磁场模拟器计算出的采用本实施方式的结构时的微带线周边的电场强度的结果的图。另外，在该模拟器中假设的结构如下：对于集成电路12的部分，在Si基板11上形成作为绝缘层的内层布线层13a～13c，在其内层布线层的最上层上形成有信号线15。并且，在本图中，区域颜色越白，表示电场越强。即，在信号线15附近电场强，在远离信号线15的Si基板11中电场弱。
如图2的电场所示，在使介质膜16的厚度比内层布线层13a～13c的层间绝缘膜的合计厚度(在此为集成电路12中示出的绝缘层的厚度)大的情况下，由于从信号线15到Si基板11的距离比从信号线15到GND层(导体膜17)的距离更近的缘故，电场的一部分侵入到导电性的Si基板11的内部。因此，即使无意地增大介质膜16的厚度h，侵入到Si基板11的电场增大，反而有可能增大损耗。
为了降低该影响，有效的方法是增大Si基板11的电阻。
在图3中示出，使用电磁场模拟器计算在采用与本实施方式的半导体芯片10相同的结构下，改变了Si基板11的基板电阻时的微带线的606Hz中的每1mm的线路损耗的结果。在此，横轴表示Si基板11的基板电阻(电阻率(Ωcm))，纵轴表示60GHz中的每1mm的微带线的线路损耗(dB/mm)，带圆点标记的曲线表示内层布线层的层间绝缘膜为4.48μm时的基板电阻与线路损耗之间的关系，带方形标记的曲线表示内层布线层的层间绝缘膜为8μm时的基板电阻与线路损耗的关系。
如图3所示，随着Si基板11的基板电阻的增加，微带线的线路损耗明显减少，内层布线层的层间绝缘膜的厚度越薄，倾向越明显。只是将基板电阻从10Ωcm变为50Ωcm，线路损耗就减半，在大于100Ωcm时，基本达到饱和。另外，如非专利文献1所示，只使用了现有的内层布线的MMIC的传送线路的损耗为1dB/mm左右，在本实施方式中的半导体芯片10中，通过将基板电阻设为10Ωcm以上，根据内层布线层的层间绝缘膜的厚度(例如8μm以上)，线路损耗比现有的MMIC低，此外，为100Ωcm以上时，达到基本饱和的最小线路损耗。
非专利文献1：Yanyu Jin，Mihai A.T.Sanduleanu，and Jobn R.Long，“A Wideband Millimeter-Wave Power Amplifier With 20dB Linear PowerGain and+8dBm Maximum Saturated Output Power”IEEE JOURNAL OFSOLID-STATE CIRCUITS，VOL.43，NO.7，JULY 2008，pp.1553-1562
由以上说明可知，作为构成本实施方式中的半导体芯片10的Si基板11的基板电阻(电阻率)，优选为10Ωcm以上，更优选为100Ωcm以上。
接着，进一步详细说明构成本实施方式中的半导体芯片10的介质膜16的材料。
电磁场侵入Si基板11侧的情况，除了介质膜16的膜厚与内层布线层的膜厚的关系之外，还根据各自的介电常数而改变。通常，在介电常数高的一方电场集中，所以为了抑制电场侵入到Si基板11侧，优选增大介质膜16的介电常数。因此，作为介质膜16，使用将由第一材料构成的粒子分散到第二材料中而形成的纳米复合膜，从而能够实现高介电常数的介质膜16。在此，“纳米复合膜”是指，由大介电常数的第一材料构成的纳米级粒子分散到小介电常数的第二材料中而形成的膜。
例如，通过在BCB中混入粒子化为纳米级的高电介质材料而得到的纳米复合膜的介电常数远高于BCB。作为高电介质材料，优选陶瓷，例如、钛酸锶(STO)、钛酸锶钡(BST)、钛酸钡(BTO)氧化铪(HfO2)、铝酸铪(HfAlO2)或锆钛酸铅(PZT)等。在此，纳米级粒子的粒径只要能够混入到第二材料中并分散即可，粒径越小越好。具体地说，优选1μm以下，更优选为200nm以下，尤其分散有粒径为1nm以上且200nm以下的粒子的纳米复合膜能够得到良好的特性。
像这样，作为介质膜16，使用纳米复合膜，从而不仅能提高该介电常数，还能够自由选择介质膜16的介电常数，所以能够自由设计用于得到规定特性阻抗的介质膜16的膜厚。
另外，作为这种纳米复合膜的制法，例如，在将BCB为基料(第二材料)的情况下，与BCB膜相同，能够通过旋涂法容易地制作。
并且，作为介质膜16，不限于单一的纳米复合膜，可以将BCB膜和纳米复合膜层积，也可以将介电常数不同的多个纳米复合膜层积而得。通过这样进行层积，作为整个介质膜16的介电常数的自由度增加，从而在设计规定特性阻抗时的介质膜16的膜厚的自由度增加。
接着，使用图4(a)～图4(h)来说明本实施方式中的半导体芯片10的制造方法。图4(a)示出完成了Si工序(扩散工序)的晶片的一部分的截面结构，在本例中，只示出构成最上布线层13a的信号线15、GND布线15a以及保护膜18，其他内层布线(布线层13b、布线层13c)、晶体管等的电路层14被省略图示。在保护膜18上设置有一部分开口部18a，以便与再布线工序(post process：后处理)的布线连接。在再布线中，形成较厚的层间膜，所以需要注意将上层和下层连接的接触件(contact)的形成。在本制造方法的例子中，预先形成Cu接线柱。
首先，如图4(b)所示，在涂布了膜厚为10-15μm的抗蚀剂19之后，通过光刻工序形成开口部19a。接着，采用无电解电镀，或预先形成镀膜的电解电镀等，在抗蚀剂19的开口部19a上形成Cu接线柱15b(图4(c))。
在除去抗蚀剂19(图4(d))之后，通过旋涂，在晶片整个面上形成作为介质膜16的BCB16(图4(e))。通过合理地选择涂布条件和预烤(pre-bake)条件，从而能够在埋入了接线柱15b的状态下，使表面平坦。接着，为了使接线柱15b的上部露出，通过干法刻蚀等将BCB16的一部分开口(图4(f))，采用电镀等，将Cu制成5μm在右的膜，形成与GND布线15a连接的作为GND层17的上层布线(图4(g))。另外，在GND层17上，可以通过蚀刻等，将一部分分离出来作为与信号线15连接的信号线的引出部17a，或者也可以先用抗蚀剂形成图案之后，再进行电镀。根据需要，在最上层布线上形成基板连接用凸点21(图4(h))。
另外，在本制造方法例中，在预先形成Cu接线柱15b之后，涂布BCB16，然而也可以在先用BCB16形成厚膜之后，将一部分开口，用金属填埋开口部，从而形成接触件15b。在这种情况下，通过使用感光性的BCB16，能够容易地形成开口部。
并且，在本制造方法例中，在接线柱15b之后，形成GND层17后结束，但是通过重复该工序，能够使布线多层化。若形成为多层，则例如由Si工序(内层布线)的最上层布线15构成GND层，由后处理的第一布线形成带状线的信号，由后处理的第二布线形成将第一布线彼此连接的桥式布线，由第三布线形成GND层，从而能够实现以后述的第二实施方式及其变形例示出的结构。
并且，在本制造方法的例子中，作为布线15、接线柱15b的材料，选择了Cu，但不限于该材料，同样地介质膜16也不限于BCB。
如上所述，根据本实施方式的半导体芯片，由于在最上表面形成有微带线的GND层(导体膜)，所以将该半导体芯片反转后，经由凸点将该GND层连接到安装用电路基板的GND上(倒装)，从而能够使微带线的GND层可靠地与GND连接。因此，能够实现一种半导体芯片、及将该半导体芯片倒装到电路基板上的半导体装置，该半导体芯片是将Si类半导体作为基板的MMIC等半导体芯片，具有低损耗的传送线路，容易连接到安装用电路基板上，且能够确保稳定的GND电位。
(第二实施方式)
接着，说明本发明的第二实施方式的半导体芯片及半导体装置。
图5(a)是本发明的第二实施方式的半导体芯片30的剖视图，图5(b)是将该半导体芯片30倒装到安装用电路基板42上的图，即，是本发明的第二实施方式的半导体装置40的剖视图。另外，在图5(a)中，为了方便起见，除了半导体芯片30之外，还一并示出倒装用凸点41。
如图5(b)所示，图5(a)所示的半导体芯片30是在上下反转的状态下，经由凸点41倒装到安装用电路基板42上的Si-MMIC，具备：Si基板31；形成在该硅基板的主面上的集成电路32；形成在该集成电路32上方的接地用第一导体膜、即导体膜37b；形成在该导体膜37b上方的介质膜36；信号线38，形成在该介质膜36中，用于传送集成电路32中的信号；以及形成在介质膜36上表面的作为接地用第二导体膜的导体膜37a，由信号线38、介质膜36、导体膜37a及导体膜37b构成所谓带状线。
Si基板31是由Si类半导体构成的基板。该Si基板31因图5(a)及图5(b)所示的结构上的特征，与第一实施方式中的Si基板11不同，不受电阻率的限制。
集成电路32由如下部分构成：电路层34，由形成在Si基板31上表面的晶体管等电路元件构成；布线层33，由用于传送电路层34中的信号的Al或Cu等信号线构成；以及保护膜(钝化膜)35，形成在布线层33的上表面。布线层33是隔着例如SiO2、SiN等绝缘膜形成多层信号线的多层布线层。
另外，在本图中，在集成电路32内只形成有一个电路层34，然而本发明不限于一层电路层，也可以形成多层电路层。
导体膜37b是与构成带状线的2个GND层之中的一个(下面)相当的、由Al、Cu、Au等、或含有这些元素的合金等形成的膜。
介质膜36相当于构成带状线的电介质，是介质损耗小、且能够形成厚膜的树脂膜，优选为含有例如BCB、聚酰亚胺、聚四氟乙烯或聚苯醚的膜，或者是将由第一材料构成的粒子分散到第二材料中而形成的纳米复合膜。另外，作为纳米复合膜的具体例，与第一实施方式中的介质膜16相同。
导体膜37a是与构成带状线的2个GND层之中的另一方(上面)相当的、由Al、Cu、Au等、或含有这些元素的合金等形成的膜，经由凸点41与安装用电路基板42上的GND图案连接。另外，如图5(b)所示，2个导体膜37a及37b通过例如贯穿介质膜36的导体(via)37c电连接。但是，2个导体膜37a、37b的连接方法不限于此，可以由将介质膜36的侧面包覆的导体膜连接，也可以采用引线连接。
这种半导体芯片30的制造方法大体由2个工序构成。即，在Si基板31上形成集成电路32的通常的硅芯片的制造工序(所谓Si工序)，之后形成导体膜37b、介质膜36、信号线38及导体膜37a的再布线工序(所谓后处理)。另外，布线层33在Si工序中形成，所以又称之为内层布线层。根据本实施方式的半导体芯片30，在再布线工序中形成带状线，所以与Si的工序节点无关，能够适用于多种MMIC的制造。
具有这种结构的本实施方式中的半导体芯片30的特征在于，由信号线38、介质膜36、导体膜37a及37b构成带状线。在此，“构成带状线”是指具有在信号线与导体膜之间夹持电介质的结构，更严谨地说，是指以使带状线的特性阻抗与该传送线路所要求的值大致一致的方式决定参数(信号线38的厚度及宽度、介质膜36的介电常数及厚度等)，该参数决定带状线的特性阻抗。
在本实施方式的半导体芯片30中，最上表面为GND层(导体膜37a)，将半导体芯片30上下反转而倒装到安装用电路基板42上，从而能够将位于半导体芯片30的最上表面的导体膜37a经由较小的凸点41直接连接到安装用电路基板42的GND上。由此，在将导体膜37a连接到GND上的位置(在此为凸点41)处的电感被抑制得非常小，构成带状线的GND层(在此为导体膜37a及37b)可靠地接地，避免不必要的振荡。
另外，在本实施方式的半导体芯片30中，信号线38与Si基板31之间的导体膜37b发挥电场屏蔽作用，与第一实施方式中的半导体芯片10不同，能够忽略电场向Si基板31的侵入，对Si基板31的基板电阻没有限制。由此，能够与Si基板31的基板电阻或内层布线层的厚度无关地实现低损耗的传送线路。例如，采用上述模拟器测定的结果，满足特性阻抗为50Ω这一条件的带状线(例如，导体膜37a及37b的厚度分别为5μm，介质膜36的厚度为25μm，介电常数ε为2.7，tanδ为0.0001，信号线38的厚度为5μm，线宽度为9μm)中的线路损耗为非常小的值(具体为0.24dB/mm)。
另外，作为带状线的结构，不限于图5(a)及图5(b)所示的结构，也可以是图6(a)～图6(c)所示的结构。
在图6(a)示出的半导体芯片50中，只有构成带状线的信号线的结构(层结构)与半导体芯片30不同。在该半导体芯片50中，在介质膜36中形成能够进行桥式布线的多个布线层51a及51b。另外，在该半导体芯片50的后处理中，形成共计4层(导体膜37a、布线层51a、布线层51b、导体膜37b)多层布线。这种半导体芯片50是在硅工艺中形成了集成电路32之后，在后处理中形成导体膜37b、介质膜36、布线层51a、布线层51b及导体膜37a。
并且，在图6(b)中示出的半导体芯片60中，最上表面的导体膜37a通过图案化而使得导体膜的一部分具有缺口区域62，信号线61包括与形成在该缺口区域62中的信号图案63连接的信号线。由此，即使是在介质膜36中仅设置了一层布线层的结构，也可以实现该布线层上的桥式布线。
并且，图6(c)中示出的半导体芯片70相当于，用形成在内层布线层(布线层33)内的GND层(导体膜33a)替换图6(a)中示出的半导体芯片50上的导体膜37b。这种半导体芯片70是在硅工艺中形成了集成电路32(包括作为GND层的导体膜33a)之后，在后处理中形成介质膜36、布线层51a、布线层51b及导体膜37a。另外，为了减低导体损耗，优选形成在内层布线层上的GND层尽量厚。因此，作为GND层，例如，除了最上层布线之外，还可以将该下层的布线层重叠使用。并且，可以将在焊盘部中使用的Al等焊盘用导体膜重叠使用。
另外，作为再布线工序中的布线层，不限于1层或2层，还可以是3层以上。
如上所述，根据本实施方式的半导体芯片，由于在最上表面形成有微带线的GND层(导体膜)，所以将该半导体芯片反转，经由凸点将该GND层连接到安装用电路基板的GND上(倒装)，从而能够使微带线的GND层可靠地与GND连接。由此能够实现一种半导体芯片、及将这种半导体芯片倒装到电路基板上的半导体装置，该半导体芯片是将Si类半导体作为基板的MMIC等半导体芯片，具有低损耗的传送线路，容易连接到安装用电路基板上，且能够确保稳定的GND电位。
以上，根据第一实施方式、第二实施方式及其变形例，说明了本发明的半导体芯片及半导体装置，然而本发明不限于这些实施方式及变形例。本发明还包括本领域技术人员对这些实施方式及变形例实施各种变形得到的方式、将这些实施方式及变形例的构成要素任意组合而实现的方式。
例如，在上述实施方式中，作为导体膜，示出了均质导体，然而实际上为了满足Si工序中的图案的占有面积率的限制，也可以采用网状图案，也可以是适当设置有开口部的导体膜。
并且，在图1(a)及图1(b)、及图5(a)及图5(b)的剖视图中，示出了用于将本发明的半导体芯片的作为最上层的GND层(导体膜17及37a)接地的凸点21及41，然而设置于本发明的半导体装置的凸点不限于这种接地用凸点，如图7所示，也可以设置用于连接电源、信号的凸点23。即，还可以在导体膜17的缺口区域设置与电路层14连接的凸点。
工业实用性
本发明能够应用于被倒装的半导体芯片、及将这种这种半导体芯片倒装到安装用电路基板上的半导体装置，尤其能够应用于Si-MMIC，例如便携电话等小型通信设备用的Si-MMIC。
附图标记说明
10、30、50、60、70 半导体芯片；11、31 Si基板；12、32 集成电路；13a～13c、33、51a、51b 布线层；14、34 电路层；15、38、61 信号线(布线)；15a GND布线；15b 接线柱(contact)；16、36 介质膜(BCB等)；17、33a、37a、37b 导体膜(GND层)；18、35 保护膜；18a保护膜的开口部；19 抗蚀剂；19a 抗蚀剂的开口部；20、40 半导体装置；21、41 凸点；22、42 安装用电路基板；37c 导体(via)；62 缺口区域；63 信号图案。

Claims (17)

1.一种半导体芯片，为倒装的半导体芯片，具备：
硅基板；
形成在所述硅基板的主面上的集成电路；
形成在所述集成电路上方的介质膜；以及
形成在所述介质膜上表面的接地用的导体膜，
所述集成电路包括由用于传送该集成电路中的信号的信号线构成的布线层，
由所述信号线、所述介质膜及所述导体膜构成微带线。
2.根据权利要求1所述的半导体芯片，
所述集成电路包括层积而成的多个布线层，
构成所述微带线的信号线包括构成所述多个布线层之中的最上面的布线层的信号线。
3.根据权利要求1所述的半导体芯片，
所述布线层包括与所述集成电路连接的电极焊盘用的导体膜，
构成所述微带线的信号线包括所述电极焊盘用的导体膜。
4.根据权利要求1所述的半导体芯片，
所述介质膜包含苯并环丁烯、聚酰亚胺、聚四氟乙烯或聚苯醚。
5.根据权利要求1～4的任意一项所述的半导体芯片，
所述介质膜包括将由第一材料构成的粒子分散到第二材料中而形成的纳米复合膜。
6.根据权利要求5所述的半导体芯片，
所述粒子的粒径为1nm以上且200nm以下。
7.根据权利要求6所述的半导体芯片，
所述第一材料是陶瓷。
8.根据权利要求7所述的半导体芯片，
所述陶瓷包含钛酸锶、钛酸锶钡、氧化铪、铝酸铪或锆钛酸铅。
9.根据权利要求1所述的半导体芯片，
所述硅基板的电阻率为10Ωcm以上。
10.一种半导体芯片，为倒装的半导体芯片，具备：
硅基板；
形成在所述硅基板的主面上的集成电路；
形成在所述集成电路上方的接地用的第一导体膜；
形成在所述第一导体膜上方的介质膜；
布线层，形成在所述介质膜中，由用于传送该集成电路中的信号的信号线构成；以及
形成在所述介质膜上表面的接地用的第二导体膜，
由所述信号线、所述介质膜、所述第一导体膜及第二导体膜构成带状线。
11.根据权利要求10所述的半导体芯片，
在所述介质膜中形成有多个布线层。
12.根据权利要求10所述的半导体芯片，
所述第一导体膜、所述介质膜、所述布线层及所述第二导体膜通过与形成所述集成电路的硅工艺不同的后处理形成。
13.根据权利要求10所述的半导体芯片，
所述第一导体膜通过与所述集成电路相同的硅工艺形成，
所述介质膜、所述布线层及所述第二导体膜通过与所述硅工艺不同的后处理形成。
14.根据权利要求10所述的半导体芯片，
所述第二导体膜具有导体膜一部分欠缺的区域，
所述信号线包括与形成在所述区域中的信号图案连接的信号线。
15.一种半导体装置，具备：
权利要求1所述的半导体芯片；以及
经由凸点与权利要求1所述的半导体芯片的导体膜连接的安装用电路基板。
16.一种半导体装置，具备：
权利要求10所述的半导体芯片；以及
经由凸点与权利要求10所述的半导体芯片的第二导体膜连接的安装用电路基板。
17.一种倒装的半导体芯片的制造方法，包括：
在硅基板的主面上形成集成电路的步骤；
在所述集成电路上方形成接地用的第一导体膜的步骤；
在所述第一导体膜上方形成介质膜的步骤；
在所述介质膜中形成布线层的步骤，该布线层由用于传送所述集成电路中的信号的信号线构成；以及
在所述介质膜上表面形成接地用的第二导体膜的步骤，
所述信号线、所述介质膜、所述第一导体膜及第二导体膜构成带状线，
所述第一导体膜通过与所述集成电路相同的硅工艺形成，
所述介质膜、所述布线层及所述第二导体膜通过与所述硅工艺不同的后处理形成。
CN201080010283.8A 2009-03-03 2010-02-18 半导体芯片及半导体装置 Expired - Fee Related CN102341895B (zh)

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