CN102326227A - Soi晶片的制造方法 - Google Patents

Soi晶片的制造方法 Download PDF

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Publication number
CN102326227A
CN102326227A CN2010800086820A CN201080008682A CN102326227A CN 102326227 A CN102326227 A CN 102326227A CN 2010800086820 A CN2010800086820 A CN 2010800086820A CN 201080008682 A CN201080008682 A CN 201080008682A CN 102326227 A CN102326227 A CN 102326227A
Authority
CN
China
Prior art keywords
wafer
insulating film
bonded
soi
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010800086820A
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English (en)
Chinese (zh)
Inventor
阿贺浩司
横川功
能登宣彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of CN102326227A publication Critical patent/CN102326227A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H10P50/644—Anisotropic liquid etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Weting (AREA)
CN2010800086820A 2009-02-26 2010-01-08 Soi晶片的制造方法 Pending CN102326227A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009-043403 2009-02-26
JP2009043403A JP5244650B2 (ja) 2009-02-26 2009-02-26 Ｓｏｉウェーハの製造方法
PCT/JP2010/000076 WO2010098007A1 (ja) 2009-02-26 2010-01-08 Ｓｏｉウェーハの製造方法

Publications (1)

Publication Number Publication Date
CN102326227A true CN102326227A (zh) 2012-01-18

Family

ID=42665227

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010800086820A Pending CN102326227A (zh) 2009-02-26 2010-01-08 Soi晶片的制造方法

Country Status (6)

Country Link
US (1) US20110281420A1 (enExample)
EP (1) EP2402983B1 (enExample)
JP (1) JP5244650B2 (enExample)
KR (1) KR20110116036A (enExample)
CN (1) CN102326227A (enExample)
WO (1) WO2010098007A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104364880A (zh) * 2012-05-24 2015-02-18 信越半导体股份有限公司 Soi晶片的制造方法
CN105280541A (zh) * 2015-09-16 2016-01-27 中国电子科技集团公司第五十五研究所 一种用于超薄半导体圆片的临时键合方法及去键合方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5478604B2 (ja) 2008-03-31 2014-04-23 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド シリコンウェハの端部をエッチングするための方法
WO2010059556A1 (en) 2008-11-19 2010-05-27 Memc Electronic Materials, Inc. Method and system for stripping the edge of a semiconductor wafer
JP5477277B2 (ja) * 2010-12-20 2014-04-23 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US8853054B2 (en) 2012-03-06 2014-10-07 Sunedison Semiconductor Limited Method of manufacturing silicon-on-insulator wafers
JP5862521B2 (ja) * 2012-09-03 2016-02-16 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP6056516B2 (ja) * 2013-02-01 2017-01-11 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
US9177967B2 (en) 2013-12-24 2015-11-03 Intel Corporation Heterogeneous semiconductor material integration techniques
FR3076393A1 (fr) * 2017-12-28 2019-07-05 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1225499A (zh) * 1998-02-04 1999-08-11 佳能株式会社 半导体衬底及其制造方法
CN1272684A (zh) * 1999-02-02 2000-11-08 佳能株式会社 衬底及其制造方法
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JP2007141946A (ja) * 2005-11-15 2007-06-07 Sumco Corp Ｓｏｉ基板の製造方法及びこの方法により製造されたｓｏｉ基板
CN101084577A (zh) * 2004-12-28 2007-12-05 特拉希特技术公司 修整通过组装两晶片构成的结构的方法
CN101124657A (zh) * 2005-02-28 2008-02-13 信越半导体股份有限公司 贴合晶圆的制造方法及贴合晶圆

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11121310A (ja) * 1997-10-09 1999-04-30 Denso Corp 半導体基板の製造方法
JP3030545B2 (ja) 1997-07-19 2000-04-10 信越半導体株式会社 接合ウエーハの製造方法
JP4304879B2 (ja) 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
CN1225499A (zh) * 1998-02-04 1999-08-11 佳能株式会社 半导体衬底及其制造方法
CN1272684A (zh) * 1999-02-02 2000-11-08 佳能株式会社 衬底及其制造方法
CN101084577A (zh) * 2004-12-28 2007-12-05 特拉希特技术公司 修整通过组装两晶片构成的结构的方法
CN101124657A (zh) * 2005-02-28 2008-02-13 信越半导体股份有限公司 贴合晶圆的制造方法及贴合晶圆
JP2007141946A (ja) * 2005-11-15 2007-06-07 Sumco Corp Ｓｏｉ基板の製造方法及びこの方法により製造されたｓｏｉ基板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104364880A (zh) * 2012-05-24 2015-02-18 信越半导体股份有限公司 Soi晶片的制造方法
CN105280541A (zh) * 2015-09-16 2016-01-27 中国电子科技集团公司第五十五研究所 一种用于超薄半导体圆片的临时键合方法及去键合方法

Also Published As

Publication number Publication date
US20110281420A1 (en) 2011-11-17
KR20110116036A (ko) 2011-10-24
EP2402983A4 (en) 2012-07-25
EP2402983B1 (en) 2015-11-25
WO2010098007A1 (ja) 2010-09-02
JP2010199353A (ja) 2010-09-09
EP2402983A1 (en) 2012-01-04
JP5244650B2 (ja) 2013-07-24

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Application publication date: 20120118