CN102280423A - 集成电路装置及其制造方法 - Google Patents

集成电路装置及其制造方法 Download PDF

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Publication number
CN102280423A
CN102280423A CN2011100251010A CN201110025101A CN102280423A CN 102280423 A CN102280423 A CN 102280423A CN 2011100251010 A CN2011100251010 A CN 2011100251010A CN 201110025101 A CN201110025101 A CN 201110025101A CN 102280423 A CN102280423 A CN 102280423A
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layer
copper
work package
integrated circuit
protective layer
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CN102280423B (zh
Inventor
林俊成
黄雅希
陈新瑜
蔡柏豪
林彦甫
黄震麟
蔡方文
邱文智
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract

本发明公开了一种集成电路装置及其制造方法。本发明的集成电路装置的工作件(work piece)包括具有上表面和侧壁的铜凸块。在铜凸块的侧壁上形成保护层，但其上表面没有保护层。保护层包括铜的化合物和聚合物，且为介电层。本发明提供的集成电路装置及其制造方法，在裸片对晶片接合工艺中，即使工作件的温度高时，保护层也可避免铜凸块的氧化。

Description

集成电路装置及其制造方法
技术领域
本发明涉及集成电路，尤其涉及一种侧壁上具有保护层的铜凸块结构。
背景技术
裸片对晶片(die-to-wafer)接合为常用的接合方式，其中由晶片分割的半导体裸片接合至晶片上尚未分割的半导体芯片。借由裸片对晶片接合，可选择已知的良好裸片接合至晶片。因此相较于晶片到晶片接合，其良率更为提升。
传统上裸片对晶片接合方法有缺点。晶片可包括许多芯片(之后称为底部芯片)，有时超过千个芯片。因此，超过千个以上的裸片需一个一个的接合至底部芯片。在整个接合工艺的过程中，必须加热晶片。然而，晶片的温度很难控制。若温度太高，在底部芯片的铜凸块会被严重氧化，且在底部芯片上的助焊剂(flux)可能被烘烤/蒸发。另一方面，若温度太低，可能形成冷焊(cold joint)。故对裸片对晶片接合的良率产生不利的影响。
发明内容
为了克服现有技术存在的缺陷，在一实施例中，本发明的工作件包括具有上表面和侧壁的铜凸块。在铜凸块的侧壁上形成保护层，但其上表面没有保护层。保护层包括铜的化合物和聚合物，且为介电层。
本发明也公开其他实施例。
根据一实施例，本发明提供了一种集成电路装置，包括：
一第一工作件，包括：
一铜凸块，具有一上表面及侧壁；以及
一保护层，在该铜凸块的该侧壁上，而不在该上表面，其中该保护层包括一铜的化合物及一聚合物，且其中该保护层为一介电层。
根据本发明的一实施例，本发明提供了一种集成电路的制造方法，包括：
提供一第一工作件，该第一工作件包括具有一上表面及侧壁的一铜凸块；
在该铜凸块的侧壁形成一聚合物层，且其不与该铜凸块的该上表面接触；
固化该聚合物层，其中该聚合物层部分与该铜凸块反应以在该铜凸块的该侧壁形成一保护层；以及
移除该聚合物层未反应的部分，且保留在该铜凸块的该侧壁上的该保护层。
本发明提供的集成电路装置及其制造方法，在裸片对晶片接合工艺中，即使工作件的温度高时，保护层也可避免铜凸块的氧化。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附的图，作详细说明如下：
附图说明
图1至图4为根据多个实施例的剖面图，用以说明包括焊料帽的凸块结构的形成的中间阶段。
图5至图9为根据其他实施例的剖面图，用以说明不具焊料帽的凸块结构的形成的中间阶段。
图10A及图10B为接合的工作件的剖面图。
【主要附图标记说明】
2、200～工作件
10～基板
14～半导体装置
12～内连线结构
28～金属焊盘
30～钝化层
32～凸块底层金属
34～铜凸块
36～非铜金属层
40～焊料帽
42～聚合物层
42a、34a、36a、40a～上表面
44～保护层
T～厚度
44a～上边缘
36b～底表面
50～抛光金属
202～铜柱凸块
204～阻挡层
206～焊料区
54～底部填充胶
具体实施方式
以下叙述实施例的制造与使用。然而，应注意实施例提供许多可被广泛的应用的发明概念。所述特定实施例仅为说明实施例的特定使用方式，但本发明并不以此为限。
本发明提供新颖的凸块结构及其形成方法。说明制造一实施例的中间阶段，并讨论不同的实施例。在各个不同的说明与附图中，以类似的附图标记指示类似的元件。
参照图1，提供包括基板10的工作件2。工作件2可为元件裸片(device die)，其中包括有源元件，例如为晶体管；然而，工作件2也可为其中不具有有源元件的封装基板或转接板(interposer)。在一实施例中，工作件2为元件裸片，基板10可为半导体基板如硅基板，但也可包括其他半导体材料。可在基板10的表面形成半导体装置14，例如为晶体管。在基板10上形成内连线结构12，包括在其中形成金属线及通孔(未显示)且连接半导体装置14。可由铜或铜合金形成金属线及通孔，且可利用熟知的金属镶嵌(damascene)工艺而形成。内连线层12可包括已知的层间介电层(inter-layerdielectric，ILD)及金属间介电层(inter-metal dielectrics，IMDs)。为了简化，基板10、内连线结构12、及半导体装置14并未显示于后续的附图中，虽然其可存在于各附图中。
在内连线结构12上形成金属焊盘28。金属焊盘28可包括铝、铜、银、金、镍、钨、前述的合金、和/或前述的多层。金属焊盘28可与半导体装置14电性耦接，例如通过其下的内连线结构12。可形成钝化层以覆盖部分金属焊盘28，钝化层可包括一或多层介电层包括钝化层30。在一实施例中，钝化层30由聚酰亚胺(polyimide)或其他已知介电质材料所形成。钝化层也可为包括氧化硅层、氮化硅层、聚酰亚胺层等的复合结构。
凸块底层金属(under-bump-metallurgy，UBM)32形成于金属焊盘28上，且与其电性相连。凸块底层金属32可包括钛层及在钛层上的铜层(未显示)。在凸块底层金属32上形成铜凸块34，其实质上可由纯铜或铜合金所形成。一实施例的电镀工艺包括形成毯覆凸块底层金属层(blanket under-bump-metallurgy layer)(未显示，其中凸块底层金属32为毯覆凸块底层金属层的一部分)、在毯覆凸块底层金属层上形成一掩模(未显示)、图案化掩模以形成开口、在开口中电镀铜凸块34、以及移除掩模及毯覆凸块底层金属层之前被掩模覆盖的部分。铜凸块34可由实质上的纯铜或铜合金所形成。
在铜凸块34的上表面上形成非铜金属层36，其不含或实质上不含铜，且其形成的金属材料可包括镍、钴、锡、钯、铋、银、镉、金、锌、或前述的组合。可在非铜金属层36上形成焊料帽40，其可包括不含铅的焊料材料，例如含有锡银(SnAg)、锡银铜(SnAgCu)等。但焊料帽40也可由共熔(eutectic)焊料材料所形成，例如含铅及锡。
参照图2，形成聚合物层42，例如由涂布形成。聚合物层42的上表面42a可高于铜凸块34的上表面34a，且可高于或低于非铜金属层36的上表面36a。此外，聚合物层42的上表面42a可高于或低于焊料帽40的上表面40a。聚合物层42由感光材料形成，其可为光致抗蚀剂和/或聚酰亚胺。另外，聚合物层42的材料可与铜反应，但不会与非铜金属层36反应。因此，聚合物层42可用的材料包括苯类(benzene-based)聚合物、二氧六环(dioxane-based)聚合物、甲苯类(toluene-based)聚合物、苯硫类(phenylthiol-based)聚合物、酚类(phenol-based)聚合物、环己烷类(cyclohexane-based)聚合物、对甲酚类(p-cresol-based)聚合物等，但非以此为限。聚合物层42的材料例如包括聚苯恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide)、2，3-二甲基酚(2，3-dimethylphenol)、2，4-二甲基酚(2，4-dimethylphenol)、2，6-二甲基酚(2，6-dimethylphenol)、3，4-二甲基酚(3，4-dimethylphenol)、1，3，5-对甲苯酚(1，3，5-xylenol)、对乙基酚(p-ethylphenol)等。
参照图3，在涂布聚合物层42后，将聚合物层42暴露于光下，而后进行固化步骤。固化步骤在低温下进行，其可低于约190℃，例如可介于150℃至190℃之间。固化可持续约一至二小时，但也可使用不同的固化温度及时间。借由低温固化，不会损害到下方的钝化层30，其可由聚酰亚胺所形成。在固化步骤中，聚合物层42与铜凸块34接触的表面部分的铜反应以形成保护层44，其为含铜聚合物类(copper-containing polymer-based)的化合物。在一实施例中，保护层44的厚度介于约5nm至约500nm。并且，保护层44可大体具相同厚度T。保护层44仅在铜凸块34的侧壁上。保护层44并未水平延伸至钝化层30的上表面。此外，保护层44环绕着铜凸块34。
聚合物层42不与非铜金属层36反应。因此，在非铜金属层36的上表面及边缘不会形成保护层44。并且，保护层44的上边缘44a大体上与铜凸块34的上表面34a等高，且大体上与非铜金属层36的底表面36b等高。保护层44的功能为保护铜凸块34在裸片对晶片接合工艺中不会被氧化。
图4显示移除聚合物层42。在移除聚合物层42时，并未移除下方的钝化层30。应注意因为钝化层30在暴露在光中之前，已于先前工艺步骤中固化，所以即使聚合物层42与钝化层30以相同光致抗蚀剂形成，钝化层30仍可保留而不会被移除。另外，钝化层30与聚合物层42也可由不同材料形成。因此，保护层44在铜凸块34的侧壁上，而不在其上表面。
图5至图9显示根据另一实施例的凸块结构的形成。除了特别指出的地方，在这些实施例中以图1至图4的附图标记表示类似的元件。在图5至图8中的工艺步骤与材料基本上与图1至图4相同，但是没有焊料帽40(图1)形成在非铜金属层36的上表面。在图5至图8中的工艺的细节与材料简略叙述如下。
在图5中，提供最初的结构包括凸块底层金属32、铜凸块34、及非铜金属层36。而后，在图6中，涂布聚合物层42，且将其暴露及固化而形成保护层44，如图7所示。接着，如图8所示，移除聚合物层42未反应的部分。
参照图9，在非铜金属层36上形成抛光金属(metal finish)50，例如利用无电镀。抛光金属50可具单一层结构或复合结构，其中复合结构包括由不同材料形成的多个次层。在一实施例中，形成抛光金属50的材料为无电镀镍钯金(electroless nickel electroless palladium immersion gold，ENEPIG)，其包括镍层、在镍层上的钯层、以及在钯层上的金层。金层可借由浸镀形成。在另一实施例中，可由其他已知抛光材料及方法形成抛光金属50，包括无电镀镍金(electroless nickel immersion gold，ENIG)、直接浸金(directimmersion gold，DIG)等，但并非以此为限。抛光金属50选择性的直接形成于非铜金属层36的上表面与侧壁，而不形成在保护层44的侧壁。
图10A显示工作件2(如图9所示)及工作件200的接合。图10B显示工作件2(如图5所示)及工作件200间的接合。工作件2可在未分割晶片内，而工作件200可为由各晶片切割的分割裸片。因此以裸片对晶片方式接合。工作件200可为元件裸片、转接板、封装基板等。工作件200可包括金属凸块如铜柱(copper pillar)凸块或焊料凸块。如图10A及图10B所示，在一实施例中，工作件200包括铜柱凸块202、在铜柱凸块202表面上的阻挡层204(如镍层)。焊料区206将阻挡层204及铜柱凸块202连接至非铜金属层36(或是若有抛光金属50，则接合至抛光金属50)。其中，借由回焊(reflow)焊料区206而连接。在工作件2与200接合后，于工作件2与200的间隙填入底部填充胶(underfill)54。因此，在底部填充胶54与铜凸块34不接触的情况下，保护层44可隔开底部填充胶54与铜凸块34。此外，聚合物层42(图2至图6)及底部填充胶54可由不同材料形成。
既然保护层44对于焊料不具湿润性(wettable)，在裸片对晶片接合工艺中，即使工作件2的温度(相对于晶片)高，在焊料区206的焊料仍不会滑动至保护层44的表面。因此焊料区206仍在抛光金属50(或非铜金属层36)的表面，其对于焊料具有良好的湿润性。据此，焊料区206的体积易于控制。这也同时减少了焊料区206的侧向延伸所导致相邻凸块结构短路的可能性。此外，在裸片对晶片接合工艺中，即使工作件2的温度高时，保护层44可避免铜凸块34的氧化。因此，在铜凸块34的侧壁上不需要助焊剂。
虽然本发明已以数个较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中具有普通知识的技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当以所附的权利要求所界定的范围为准。

Claims (10)

1.一种集成电路装置，包括：
一第一工作件，包括：
一铜凸块，具有一上表面及侧壁；以及
一保护层，在该铜凸块的该侧壁上，而不在该上表面，其中该保护层包括一铜的化合物及一聚合物，且其中该保护层为一介电层。
2.如权利要求1所述的集成电路装置，还包括一非铜金属层在该铜凸块的该上表面上且与其接触。
3.如权利要求2所述的集成电路装置，还包括一焊料帽在该非铜金属层上且与其接触。
4.如权利要求2所述的集成电路装置，还包括一抛光金属与该非铜金属层的一上表面及侧壁接触。
5.如权利要求1所述的集成电路装置，还包括：
一第二工作件，在该第一工作件上；
一焊料区，将该第二工作件接合至该第一工作件，其中该焊料区包括至少一部分直接在该铜凸块之上且与其电性耦接；以及
一底部填充胶，在该第一及第二工作件之间，其中该底部填充胶与该保护层接触。
6.一种集成电路的制造方法，包括：
提供一第一工作件，该第一工作件包括具有一上表面及侧壁的一铜凸块；
在该铜凸块的侧壁形成一聚合物层，且其不与该铜凸块的该上表面接触；
固化该聚合物层，其中该聚合物层部分与该铜凸块反应以在该铜凸块的该侧壁形成一保护层；以及
移除该聚合物层未反应的部分，且保留在该铜凸块的该侧壁上的该保护层。
7.如权利要求6所述的集成电路的制造方法，还包括在形成该聚合物层之前，形成一非铜金属层在该金属凸块的该上表面上，且与其接触。
8.如权利要求7所述的集成电路的制造方法，还包括在形成该聚合物层之前，形成一焊料帽在该非铜金属层上且与其接触。
9.如权利要求7所述的集成电路的制造方法，还包括在形成该保护层之后，形成一抛光金属与该非铜金属层的一上表面与侧壁接触，其中该抛光金属没有形成在该保护层上。
10.如权利要求6所述的集成电路的制造方法，还包括将一第二工作件接合至该第一工作件，且在该第一及第二工作件之间填入一底部填充胶，其中该底部填充胶与该保护层接触。
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