TWI651806B - 半導體封裝件與其形成方法 - Google Patents

半導體封裝件與其形成方法 Download PDF

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Publication number
TWI651806B
TWI651806B TW103146103A TW103146103A TWI651806B TW I651806 B TWI651806 B TW I651806B TW 103146103 A TW103146103 A TW 103146103A TW 103146103 A TW103146103 A TW 103146103A TW I651806 B TWI651806 B TW I651806B
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Taiwan
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layer
redistribution layer
package
bonding
wafer
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TW103146103A
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TW201537679A (zh
Inventor
陳憲偉
陳潔
葉德強
鄭心圃
余振華
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台灣積體電路製造股份有限公司
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Priority claimed from US14/222,475 external-priority patent/US9318452B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201537679A publication Critical patent/TW201537679A/zh
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Abstract

本揭露之實施方式包含半導體封裝件與其形成方法。實施方式之一為一種半導體封裝件，其包含第一封裝件，第一封裝件包含一或多個第一晶片，以及半導體封裝件包含第一重分佈層，其透過第一組接合點於第一封裝件之第一側邊耦合至一或多個的第一晶片，第一重分佈層包含設置於多於一個鈍化層中的多於一個金屬層，第一組接合點直接耦合至一或多個金屬層的其中至少一者，且第一組連接部耦合至第二重分佈層的第二側邊，第二側邊相對第一側邊。

Description

半導體封裝件與其形成方法
本發明是有關於一種半導體封裝件與其形成方法。
半導體裝置被使用於各種電子應用上面，例如，像是個人電腦、手機、數位相機與其他電子設備。半導體裝置之製作通常是透過依次沉積絕緣層或介電層、導電層以及半導體層的材料於半導體基板上，並將各種材料層透過曝光顯影在其上形成電路元件和元件圖案。
由於改善了各種電子元件(例如，電晶體、二極體，電阻、電容等)的整合密度，半導體工業已經有了快速發展。在大多數情況下，此種整合密度的改善是來自將半導體縮小(例如，將製程節點縮小至sub-20奈米等級)。對於微型化之需求中，更高的速度與更高的帶寬，以及較低的功耗與延遲時間之需求已經於近來增長，於半導體晶片中，其存在有更小且更創新之封裝技術的需求。
根據本揭露之實施方式，半導體封裝件包含第一封裝件，其包含一或多個第一晶片，以及半導體封裝件包含第一重分佈層，其於第一封裝件之第一側邊耦合至一或多個的第一晶片，第一重分佈層包含設置於多於一個鈍化層中的多於一個導體層。半導體封裝件更包含第二重分佈層，其於第一封裝件之第二側邊耦合至一或多個的第一晶片，第二側邊相對第一側邊，第二重分佈層包含一或多個導電圖案，以及半導體封裝件更包含一或多個對位結構，其位於第二重分佈層中，一或多個對位結構自第二重分佈層中的一或多個導電圖案電性解耦。
於其他的實施方式中，半導體封裝件包含晶片封裝件。晶片封裝件包含具有第一側邊的第一重分佈層，第一側邊具有第一區域與圍繞第一區域的第二區域，其中第一重分佈層包含位於第二區域中的對位結構，以及晶片封裝件包含第一晶片，其於第一區域中接合至第一重分佈層的第一側邊。半導體封裝件更包含第二重分佈層，其具有一第二側邊，其中第一晶片透過一組接合點接合至第二重分佈層的第二側邊，第二重分佈層包含複數個金屬層，設置於複數個鈍化層之中，每一組的接合點直接耦合至金屬層的第一金屬層。
於再一實施方式中，半導體封裝件的形成方法包含形成第一重分佈層於第一承載基板之上，第一重分佈層具有第一側邊，第一側邊具有第一區域與圍繞第一區域的第二區域，形成對位結構於第一重分佈層的第一側邊上之第二區域中，以及使用作為對位標記之對位結構，將第一晶片對位於第一重分佈層的第一側邊上之第一區域中。半導體封裝件的形成 方法更包含將第一晶片接合至第一重分佈層的第一側邊之第一區域中，形成第二重分佈層，以及使用一組接合結構將第二重分佈層接合至第一晶片，以形成一組接合點，接合點的其中至少一者接合至第一晶片。
100,700‧‧‧晶片封裝件
102,202,502‧‧‧承載基板
104,504‧‧‧介電層
106‧‧‧接合墊/焊球下金屬層
108,508‧‧‧電性連接部
108A,108B,112A,114A‧‧‧表面
110,510‧‧‧晶片
112,512‧‧‧接觸區域
114,416,514‧‧‧模制材料
204,518‧‧‧重分佈層
204A‧‧‧第一側邊
204B‧‧‧第二側邊
206‧‧‧鈍化層
208‧‧‧金屬線
210,630,810‧‧‧焊球下金屬層
212,408‧‧‧導電連接部
218‧‧‧切塊膠帶
220,302‧‧‧開口
222,600,600A,600B‧‧‧接合結構
224‧‧‧接合點
300,500‧‧‧半導體封裝件/封裝件
400,800‧‧‧封裝件
402‧‧‧基板
404,406,506‧‧‧接合墊
410‧‧‧堆疊晶片
412‧‧‧焊線
414‧‧‧接觸墊
516‧‧‧對位結構
602,602A,602B‧‧‧種子層
604,604A,604B‧‧‧導電層
606,606A,606B‧‧‧上蓋層
608,608A,608B,612,612A,612B‧‧‧金屬貼片層
620‧‧‧助焊劑
632‧‧‧焊料凸塊
701‧‧‧晶片區域
703‧‧‧第一邊緣
705‧‧‧第二邊緣
812‧‧‧連接部
AA’‧‧‧線段
L‧‧‧最大尺寸
D1‧‧‧第一距離
D2‧‧‧第二距離
D3‧‧‧第三距離
D4‧‧‧第四距離
H1‧‧‧高度
T1‧‧‧厚度
T2‧‧‧厚度
T3‧‧‧厚度
P1‧‧‧間距
W1‧‧‧寬度
W2‧‧‧寬度
W3‧‧‧第三寬度
M1‧‧‧金屬層
MN‧‧‧金屬層
細讀以下詳細敘述並搭配對應之圖式，可了解到本揭露之多個態樣。須注意的是，圖式中的多個特徵並未依照該業界領域之標準作法繪製實際比例。事實上，為了討論的清楚，所述之特徵的尺寸可以任意的增加或減少。
第1A圖至第1D圖繪示依照部分實施方式於形成晶片封裝件步驟中的中間步驟的剖面示意圖。
第2A圖至第2E圖繪示依照部分實施方式於形成重分佈層之步驟中的中間步驟的剖面示意圖。
第3A圖至第3D圖繪示依照部分實施方式於形成半導體封裝件步驟中的中間步驟的剖面示意圖，其中半導體封裝件包含自第1A圖至第1D的晶片封裝件與自第2A圖至第2E圖的重分佈層。
第4A圖至第4D圖繪示依照多個實施方式之自第1A圖至第1D的晶片封裝件與自第2A圖至第2E圖的重分佈層之間的接合介面。
第5A圖至第5C圖繪示依照部分實施方式於形成晶片封裝件步驟中的中間步驟的剖面示意圖。
第6A圖與第6B圖繪示依照部分實施方式中的半導體封裝件的剖面示意圖。
第7A圖至第7E圖繪示依照部分實施方式中的對位結構的平面圖。
本揭露將提供許多個實施方式或實施方法以實現本揭露之多個不同的特徵。許多元件與排列將以特定實施方法在以下敘述以簡化本揭露。當然，這些敘述僅止於範例，且不應用以限制本揭露。舉例而言，敘述「第一特徵形成於第二特徵上」包含多種實施方式，其中涵蓋第一特徵與第二特徵直接接觸，以及額外的特徵形成於第一特徵與第二特徵之間而使兩者不直接接觸。此外，本揭露在多個範例中會重複參考號碼與字母。這樣的重複方式是為了簡單與明瞭的目的而其本身並不會決定多個範例以及/或所討論的配置之間的關係。
此外，方位相對詞彙，如「在...之下」、「下面」、「下」、「上方」或「上」或類似詞彙，在本文中為用來便於描述繪示於圖式中的一個元件或特徵至另外的元件或特徵之關係。方位相對詞彙除了用來描述裝置在圖式中的方位外，其包含裝置於使用或操作下之不同的方位。當裝置被另外設置(旋轉90度或者其他面向的方位)，本文所用的方位相對詞彙同樣可以相應地進行解釋。
實施方式將對於具體上下文之中的實施方式作描述，亦即對三維(3D)積體扇出(fan-out；InFO)之堆疊式封裝 (package-on-package；PoP)裝置作描述。然而，其他實施方式也可以應用於其他電性連接元件，包括但不限於，堆疊式封裝組件、晶片對晶片組件、晶圓對晶圓組件、晶片對基板組件、於組裝封裝之中、於加工基板之中、內插件、基板或類似物，或固定輸入元件、電路板、晶片或其他元件，或用於任何類型之積體電路或電子元件的連接封裝或固定之組合。
第1A圖至第1D圖繪示依照部分實施方式於形成晶片封裝件100步驟中的中間步驟的剖面示意圖。第1A圖中的晶片封裝件100包含位於承載基板102之上的介電層104，以及位於介電層104上的接合墊106與電性連接部108。承載基板102可以是適合的基板，其為提供(於製造程序中的中間程序期間)承載基板102上之層狀物機械性的支撐。承載基板102可以是晶圓，包含玻璃、矽(例如矽晶圓)、氧化矽、金屬貼片、陶瓷材料或是類似物。
介電層104形成於承載基板102之上。介電層可以是氮化矽、碳化矽、氧化矽、低k(low-k)介電材料，如摻雜碳的氧化物、極低k介電材料，如摻雜碳的多孔二氧化矽、聚合物、如環氧樹脂、聚酰亞胺、苯並環丁烯(benzocyclobutene；BCB)、聚苯並噁唑(polybenzoxazole；PBO)等，或其的組合，然而其他相對軟質的材料，像是有機材料與介電材料也可以被使用。介電層104可以透過化學氣相沉積(chemical vapor deposition；CVD)、物理氣相沉積(physical vapor deposition；PVD)、原子層疊沉積(atomic layer deposition；ALD)、介電質旋塗製程、類似物或其組合沉積。
接合墊106形成於介電層104之上。於部分實施方式中，接合墊106透過形成凹槽(未繪示)而形成於介電層104內。凹槽之形成可以使接合墊106被埋入於介電層104內。於部分實施方式中，當接合墊106可以形成於介電層104的第一側邊104A上時，凹槽將被省略。接合墊106將隨後的接合晶片110電性且/或物理性耦合至隨後的接合封裝件400(請見第3D圖)以及/或電性連接部108。於部分實施方式中，接合墊106包含薄種子層(未繪示)，其材料為銅、鈦、鎳、金、類似物或是其組合。接合墊106的導電材料可以沉積於種子層之上。導電材料可以透過化學電鍍製程、化學氣相沉積、物理氣相沉積、原子層疊沉積、類似物或是其組合形成。於部分實施方式中，接合墊106的導電材料為銅、鎢、鋁、銀、金、類似物或其組合。
於一實施方式中，接合墊106為焊球下金屬層(underbump metallizations；UBMs)，其包含三層的導電材料，如一層鈦、一層銅與一層鎳。然而，本發明所屬技術領域中具有通常知識者可以理解到，有其他適合的材料與層狀物配置，如鉻/鉻銅合金/銅/金的配置、鈦/鎢鈦/銅的配置，或是銅/鎳/金的配置，其也可以適合形成焊球下金屬層106。於當前的應用範圍之內，其完全地包括可用於焊球下金屬層106的任何合適材料或層狀物。
電性連接部108為形成於介電層104之上，並於實質上與介電層104的第一側邊104A垂直的方向自介電層104延伸。電性連接部108可以是柱形凸起物體，其透過線接合方 式形成於接合墊上，並以接合線之一部分留存於相應的接合球方式將接合線切斷。舉例而言，第1A圖中，電性連接部108包含下部部分與上部部分，其中下部部分可以是於線接合中形成的接合球，而上部部分可以是留存的接合線。電性連接部108的上部部分可以具有均勻寬度與均勻的形狀，其為遍及上段部分、中段部分、下段部分的均勻形狀。電性連接部108之形成為透過可以被引線接合器接合的非焊料材料。於部分實施方式中，電性連接部108之材料為銅線、金線、類似物或是其組合，且也可以具有包含多個層狀物的複合物。
於替代的實施方式中，電性連接部108透過電鍍形成。於這樣的實施方式中，電性連接部之材料為銅、鋁、鎳、金、銀、鈀、類似物或其組合，且也可以具有包含多個層狀物的複合物。於這樣的實施方式中，犧牲層(未繪示)形成於承載基板之上。多個開口形成於犧牲層中，以暴露底層的接合墊。鍍膜步驟接著履行，以鍍上電性連接部108。在電性連接部108形成之後，犧牲層將會被移除。
電性連接部108與接合墊106可以一起作為用於晶片封裝件100的重分佈層背側。重分佈層背側可以用來耦合其他封裝件或是元件(請見第3D圖中的封裝件400)至晶片封裝件100。
第1B圖繪示將一或多個晶片110接合至接合墊106。晶片110的第一側邊可以耦合至接合墊106。晶片110可以是單一個晶片或可以是超過兩個的晶片。晶片110可以包含邏輯晶片，如中央處理單元(central processing unit；CPU)、 圖形處理單元(graphics processing unit；GPU)、類似物或是其組合。於部分實施方式中，晶片110包含堆疊晶片(未繪示)，其可以同時包含邏輯晶片與記憶體晶片。晶片110可以包含輸入/輸出(I/O)晶片，如廣泛輸入/輸出晶片，其提供晶片封裝件100與隨後依附之封裝件400(請見第3D圖)之間的連接。
晶片110包含於晶片110之第二側邊的接觸區域112。於部分實施方式中，接觸區域112相似於前述之接合墊106，而相同敘述於此不再贅述。於其他實施方式中，接觸區域112為自晶片之第二側邊的一部分延伸至晶片110之中的通孔，或是於部分實施方式中，通孔為完全穿過晶片110。通孔112可以是透過蝕刻製程形成，以形成孔洞(未繪示)於晶片110中，且孔洞可以被像是銅、鋁、鎳、金、銀、鈀、類似物或是其組合之導電材料填充，且也可以具有包含多個層狀物的複合物。通孔112也可以包含種子層、阻障層、內管、類似物或是其組合。
第1C圖繪示晶片110與電性連接部108之封裝。於部分實施方式中，晶片110與電性連接部108藉由模制材料114封裝。模制材料114可以成形於晶片110與電性連接部108上，舉例而言，使用壓縮成形。於部分實施方式中，模制材料114之材料為模制化合物、高分子、環氧樹脂、矽氧化物填充物、類似物或是其組合。可以履行固化步驟，以固化模制材料114，其中固化步驟可以是熱致固化、紫外光(UV)致固化、類似物或是其組合。
於部分實施方式中，晶片110、接觸區域112與電性連接部108為掩埋於模制材料114之中，而於固化模制材料114之後，平坦化步驟將會施行於模制材料114上，其例如為研磨，如第1D圖所示。平坦化步驟用以移除多餘部分的模制材料114，且此多餘部分為高於接觸區域112與電性連接部108的上表面。於部分實施方式中，接觸區域112的表面112A與電性連接部108的表面108A為暴露出來的，且其與模制材料114的表面114A為共水平面。電性連接部108可以作為穿越式模制通孔(through molding vias；TMVs)、穿越式封裝件通孔(through package vias；TPVs)、與/或穿越式積體扇出型通孔(through InFO vias；TIVs)，而其於此將作為穿越式積體扇出型通孔108。
第2A圖至第2E圖繪示依照部分實施方式於形成重分佈層204之步驟中的中間步驟的剖面示意圖。第2A圖繪示承載基板202上的重分佈層204。重分佈層204以第一側邊204A遠離承載基板202且第二側邊204B近於承載基板202之方式形成。
重分佈層204包含多於一個的金屬層，亦即標示為M與MN，其中金屬層M1為直接相鄰於承載基板202的金屬層，且金屬層MN(其有時將作為上金屬層MN)為直接相鄰於焊球下金屬層210(請見第2B圖)的金屬層。於本文之中，用語“金屬層”是指在相同的層中的金屬線208之集合。重分佈層204更包含多於一個的鈍化層206，其中多於一層的金屬層(M1至MN)為設置於多於一個的鈍化層206之中。
鈍化層206可以是氮化矽、碳化矽、氧化矽、低k(low-k)介電材料，如摻雜碳的氧化物、極低k介電材料，如摻雜碳的多孔二氧化矽、聚合物、如環氧樹脂、聚酰亞胺、苯並環丁烯、聚苯並噁唑等，或其的組合，然而其他相對軟質的材料，像是有機材料與介電材料也可以被使用。介電層104可以透過化學氣相沉積、物理氣相沉積、原子層疊沉積、介電質旋塗製程、類似物或其組合沉積。於部分實施方式中，每一個鈍化層206所形成之厚度為大約介於5微米至15微米之間。鈍化層206可以是經過固化步驟，以固化鈍化層206，其中固化步驟可以是熱致固化、紫外光(UV)致固化、類似物或是其組合。
金屬層M1與MN可以透過使用單或是對鑲嵌製程、先鑽孔製程或是先金屬製程。金屬層(M1與MN)與通孔可以是透過導電材料，如銅、鋁、鈦、類似物或是其組合形成，並具有或未具有阻障層。於一實施方式中，每一個M1至MN的金屬層中具有之厚度為大約介於5微米至15微米之間。
鑲嵌製程之形成為將圖案化層埋入於其他層之中，以致於兩個層狀物之上表面為共平面。僅建造溝槽或是通孔的鑲嵌製程被稱作為單鑲嵌製程。一次同時建造溝槽與通孔的鑲嵌製程被稱作為對鑲嵌製程。
於範例的實施方式中，金屬層M1與MN之形成為透過對鑲嵌製程。於此範例中，金屬層M1之形成位置可以始於於最低的鈍化層206上所形成的蝕刻終止層(未繪示)與始於蝕刻終止層上所接續的鈍化層206。一旦接續的鈍化層206沉 積後，接續的鈍化層206之一部分可以透過蝕刻移除以形成凹槽圖案，例如溝槽或是通孔，其可以被導電材料填充，以連接不同區域的重分佈層204並容納金屬線208與通孔。此製程可以重複進行，以將金屬層留存直至金屬層MN。
重分佈層204可以作為晶片封裝件100的重分佈層前側。此重分佈層204之前側可以用於使晶片封裝件100透過導體連接部212耦合至一或多個封裝件、封裝基板、元件、類似物或是其組合。
金屬層M1至MN的數量以及鈍化層206的數量僅為示意，而非以此為限，其數量可以是其他數量的層狀物，亦即多過或少過所繪的兩層金屬層。鈍化層的數量也可以是其他的數量，且其數量與金屬層的數量可以異於第2A圖所繪之數量。
第2B圖繪示電性耦合至金屬層MN並位於其上之焊球下金屬層210的形成。一組開口(未繪示)可以以穿過最高的鈍化層206之方式形成，以暴露金屬層MN之中的金屬線208。焊球下金屬層210可以以穿過開口的方式延伸於鈍化層206之中，且也沿鈍化層206之表面延伸。焊球下金屬層206可以包含三層的導電材料，如一層鈦、一層銅與一層鎳。然而，本發明所屬技術領域中具有通常知識者可以理解到，有其他適合的材料與層狀物配置，如鉻/鉻銅合金/銅/金的配置、鈦/鎢鈦/銅的配置，或是銅/鎳/金的配置，其也可以適合形成焊球下金屬層206。於當前的應用範圍之內，其完全地包括可用於焊球下金屬層206的任何合適材料或層狀物。
第2C圖繪示電性耦合至焊球下金屬層210並位於其上之一組導電連接部212的形成。導電連接部212可以是焊球、金屬柱、控制塌陷高度晶片連接(controlled collapse chip connection；C4)、微凸塊、無電鍍鎳無電鍍鈀淹漬金(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)技術所形成之凸塊或是類似物。導電連接部212可以包含導電材料，像是焊料、銅、鋁、金、鎳、銀、鈀、錫、類似物或是其組合。於導電連接部212為焊料凸塊的實施方式中，導電連接部212之形成為透過先形成一層焊料，焊料通常透過像是蒸鍍、電鍍、印刷、焊料轉移、焊球轉移或是類似物形成。當一層焊料已經形成在基板上，為了要將材料定形為所要求的凸塊形狀，將可以進行回焊步驟。於其他的實施方式中，導電連接部212為金屬柱(像是銅柱)，其透過濺鍍、印刷、電鍍、無電鍍、化學氣相沉積或類似物形成。金屬柱可以是空心焊料並具有實質的垂直側壁。於部分實施方式中，金屬蓋層(未繪示)形成於導電連接部(金屬柱)212之上部之上。金屬蓋層可以包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金，類似物或是其組合以及可以透過電鍍形成之物。
第2D圖繪示將重分佈層204翻轉並將其至於切塊膠帶218且移除承載基板202。於承載基板202移除之後，重分佈層204的第二側邊204B會被暴露出來。如第2D圖所示，一組開口220形成於至少一個的鈍化層206之中，以暴露金屬線208的一部分。開口220可以透過雷側鑽孔製程、蝕刻製程、類似物或是其組合形成。
第2E圖繪示電性耦合至重分佈層204之暴露的金屬線208並位於開口220之中的一組接合結構222的形成。接合結構222可以包含焊料貼片、微凸塊、焊球、焊球下金屬層、助焊劑、類似物或是其組合。接合結構將會於之後的第4A圖至第4D圖之中作更進一步的敘述。
第3A圖至第3D圖繪示依照部分實施方式於形成半導體封裝件300步驟中的中間步驟的剖面示意圖，其中半導體封裝件300包含自第1A圖至第1D的晶片封裝件100與自第2A圖至第2E圖的重分佈層204。
第3A圖繪示晶片封裝件100被翻轉至接觸區域112之上且穿越式積體扇出型通孔108對位於重分佈層204的接合結構222之上。第3B圖繪示將晶片封裝件100接合至重分佈層204。
於晶片封裝件100與重分佈層204之間的接合可以是焊料接合或是直接金屬對金屬(像是銅對銅或是錫對錫)的接合。於一實施方式中，晶片封裝件100透過回焊方式接合至重分佈層204。於回焊製程期間，接合結構222接觸於接觸區域112與穿越式積體扇出型通孔108，以將晶片封裝件100物理性或電性耦合至重分佈層並自接合結構222形成接合點。於部分實施方式中，於晶片封裝件100與重分佈層204接合於一起之前，可以有一個類似於接合結構222的接合結構(未繪示)形成於接觸區域112與穿越式積體扇出型通孔108之上。
於部分實施方式中，於接合製程之後，於晶片封裝件100與重分佈層204之間可以有因接合結構222之底座高 度所導致的小型間隙。於其他的實施方式中，晶片封裝件100與重分佈層204之間可以不具有間隙。
一般而言，重分佈層將直接形成於晶片封裝件上，而製程將因重分佈層之形成(例如鈍化層蝕刻、鈍化層固化、金屬線沉積等)會導致顯著的翹曲。然而，於所揭露的實施方式中，藉由形成重分佈層204於承載基板202上，並將所形成之重分佈層204接合至晶片封裝件100上，封裝件300的翹曲可以被縮減。舉例而言，於形成重分佈層204之期間，承載基板202可以被選擇為像是非常硬質且具有最小或沒有翹曲之型態。此外，承載基板202可以被選擇為像是具有與重分佈層204相似的熱膨脹係數(coefficient of thermal expansion；CTE)，亦即，此將縮減因熱膨脹係數不匹配而生的翹曲。
第3C圖繪示移除承載基板102以暴露介電層104的第二側邊104B。當承載基板102移除之後，開口302將自介電層104的第二側邊104B形成，以暴露穿越式積體扇出型通孔108的表面108B以及接合墊106的表面106B。開口220可以透過雷射鑽孔製程、蝕刻製程、類似物或是其組合形成。
第3D圖繪示封裝件400透過延伸穿過開口302的一組連接部408接合至封裝件300。封裝件400包含基板402與耦合至基板402的一或多個的堆疊晶片410。
基板402的材料為半導體材料，像是矽、鍺、金剛石、或是類似物。或是化合物材料也可以被使用，像是矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷鎵、磷化鎵銦、其組合或是類似物。此外，基板402可以是絕緣體上 矽(silicon-on-insulator；SOI)基板。通常來說，絕緣體上矽基板包含一層半導體材料，像是磊晶矽、鍺、矽鍺、絕緣體上矽、絕緣體上矽鍺(silicon germanium on insulator；SGOI)或是其組合。於一個替代的實施方式中，基板402為建立於絕緣基座上，例如像是玻璃纖維之增強式樹脂核心。核心材料的一個例子為玻璃纖維樹脂，像是FR4。核心材料的替代物包含雙馬來酰亞胺三嗪(bismaleimide-triazine；BT)樹脂，或者，其他的印刷電路板材料或膜。將膜增層可以使用於基板402，像是味之素社增層膜(Ajinomoto build-up film；ABF)或是其他層疊方式。基板402也可以作為基板(封裝件基板)402。
基板402可以包含主動與被動元件(未繪示於第3D圖)。本發明所屬技術領域中具有通常知識者可以理解到，各種的裝置，像是電晶體、電容器、電阻器，這些裝置的組合與類似物可以用來產生所設計之封裝件400的結構和功能要求。這些裝置可以透過合適的方法形成。
基板402可以包含金屬化層(未繪示)。金屬化層可以形成於主動或是被動元件上，並被設計成接觸於各種元件，以形成功能性電路。金屬化層之材料可以是介電(例如，低K介電材料)與導電材料(例如銅)的交替層，並具有互相連接導電材料之層與層間的通孔，且其可以透過適合的製程(像是沉積、鑲嵌、對鑲嵌或是類似物)形成。於部分實施方式中，基板402實質上不具有主動與被動元件。
基板可以具有位於基板402之第一側邊上的接合墊404，以耦合至堆疊晶片410，且具有位於基板402之第二側 邊上的接合墊406，以耦合至導電連接部408，第二側邊相對基板402的第一側邊。接合墊404與406可以相似於前述的接合墊406，而雖然接合墊404、406與106不需要為相同的，與之前相同的敘述不再贅述。
於所繪之實施方式中，堆疊晶片410為透過接觸墊414與焊線412耦合至基板402，然而其他連接方式也可以使用，像是導電凸塊。於一個實施方式中，堆疊晶片410被堆疊成記憶體晶片。舉例而言，堆疊晶片410可以包含低功耗雙倍數據速率記憶體模組，如LPDDR(low-power double data rate)1、LPDDR2、LPDDR3、或類似的記憶體模組。
於部分實施方式中，堆疊晶片410與焊線412藉由模制材料416封裝。模制材料416可以成形於堆疊晶片410與焊線412上，舉例而言，使用模制化合物。於部分實施方式中，模制材料416為模制化合物、高分子、環氧樹脂、矽氧化物填充物、類似物或是其組合。可以履行固化步驟，以固化模制材料416，其中固化步驟可以是熱致固化、紫外光(UV)致固化、類似物或是其組合。
於部分實施方式中，堆疊晶片410與焊線412為掩埋於模制材料416之中，而於固化模制材料416之後，平坦化步驟將會施行於模制材料416上，其例如為研磨，以移除多餘部分的模制材料416並提供封裝件400實質上的平面。
於封裝件400形成之後，封裝件400將藉由導電連接部408、接合墊406、接合墊106與穿越式積體扇出型通孔108接合至封裝件300。於部分實施方式中，堆疊晶片(堆疊記憶體 晶片)410可以透過接觸墊414、焊線412、接合墊406與404、導電連接部408、接合墊106與穿越式積體扇出型通孔108耦合至晶片110。
導電連接部408可以相似於前所述的導電連接部212，而雖然導電連接部408死212不需要為相同的，相同的描述在此不再贅述。
於封裝件400與封裝件300之間的接合可以是焊料接合或是直接金屬對金屬(像是銅對銅或是錫對錫)的接合。於一實施方式中，封裝件400透過回焊方式接合至封裝件300。於回焊製程期間，導電連接部408接觸於接合墊406與106與穿越式積體扇出型通孔108，以將封裝件400物理性或電性耦合至封裝件300。
底層填充材料(未繪示)可以注入或是形成於封裝件400與封裝件300之間的間隙，並圍繞導電連接部408。底層填充材料可以是，舉例而言，液態環氧樹脂、可變形凝膠，矽橡膠，或是類似物，其被分配至結構之間，並固化以硬化。於其他狀況中，底層填充材料使用以減少與保護導電連接部408。
應當理解，第3D圖所示的半導體晶片的數量(例如半導體晶片的110(晶片)與410(堆疊晶片))、穿越式積體扇出型通孔的數量(例如穿越式積體扇出型通孔108)、導電連接部的數量(例如導電連接部212與408)僅為示例。其為可以有許多變型、修改和替換。舉例而言，發明所屬技術領域中具有通常知識者可以理解到，半導體封裝件500可以容納任意數量的半導體晶片、穿越式積體扇出型通孔與導電連接部。
第4A圖至第4D圖繪示依照多個實施方式之自第1A圖至第1D的晶片封裝件100與自第2A圖至第2E圖的重分佈層204之間的接合介面。第3D圖所特別標示的區域為繪示於第4A圖至第4D圖所的封裝件500之一部分，亦即第3D圖之特別標示的區域被標記為第4A圖至第4D圖。第4A圖至第4D圖中的接合結構600(例如600A與600B)為封裝件100與重分佈層204接合於一起之前所繪示於第3A圖的接合結構222的多個實施方式。
第4A圖繪示晶片封裝件100的接合結構600與重分佈層204，其中接合結構600為微凸塊。接合結構600A耦合至接合墊106與晶片封裝件100的穿越式積體扇出型通孔108，而接合結構600B耦合至開口220(請見第2D圖)中之重分佈層204的金屬線208。於一個實施方式中，接合結構600A與600B被形成為具有高度H1，其介於大約10微米至大約40微米，以及具有寬度W2，其介於大約5微米至大約50微米。接合結構600A與600B可以被形成具有間距P1，其介於大約10微米至大約300微米。
於所繪之實施方式中，接合結構600A與600B皆為具有種子層602(602A與602B)、導電層604(604A與604B)、上蓋層606(606A與606B)的微凸塊。耦合至重分佈層204的接合結構600B為形成於開口220之中(請見第2D圖)，且鈍化層206之一部分形成使第4A圖所繪的兩個開口220被分開來。於一個實施方式中，開口220被形成為具有寬度W1，其介於大約25微米至大約150微米。
種子層602可以透過化學電鍍製程、化學氣相沉積、原子層疊沉積、物理氣相沉積、類似物或是其組合形成。種子層602可以是由鈦銅合金、鉭銅合金、類似物或是其組合形成。
導電層604可以透過化學電鍍製程、化學氣相沉積、原子層疊沉積、物理氣相沉積、類似物或是其組合形成於種子層602上。導電層604可以是由銅、鈦、鎳、金、類似物或是其組合形成以具有厚度T1，其介於大約2微米至大約10微米。
上蓋層606可以透過化學電鍍製程、化學氣相沉積、原子層疊沉積、物理氣相沉積、類似物或是其組合形成於導電層604上。導電層604可以是由錫、鎳、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或是其組合形成以具有厚度T2，其介於大約3微米至大約10微米。
接合結構600A透過回焊方式接合至接合結構600B。於回焊製程期間，接合結構600A的上蓋層606A之一部分接觸於接合結構600B的上蓋層606B之一部分，以將晶片封裝件100物理性或電性耦合至重分佈層204並自接合結構600A與600B形成接合點224。
第4B圖繪示晶片封裝件100的接合結構600與重分佈層204，其中接合結構600為具有金屬貼片層608的微凸塊。接合結構600A耦合至接合墊106與晶片封裝件100的穿越式積體扇出型通孔108，而接合結構600B耦合至開口220(請見第2D圖)中之重分佈層204的金屬線208。於一個實施方式中， 接合結構600A與600B被形成為具有高度H1，其介於大約50微米至大約120微米，以及具有寬度W2，其介於大約70微米至大約250微米。接合結構600A與600B可以被形成具有間距P1，其介於大約140微米至大約400微米。
於所繪之實施方式中，接合結構600A與600B皆為具有種子層602(602A與602B)、導電層604(604A與604B)、上蓋層606(606A與606B)的微凸塊。耦合至重分佈層204的接合結構600B為形成於開口220之中(請見第2D圖)，且鈍化層206之一部分形成使第4B圖所繪的兩個開口220被分開來。於一個實施方式中，開口220被形成為具有寬度W1，其介於大約90微米至大約400微米。
種子層602、導電層604與上蓋層606為相似於第4A圖中的描述，因此其敘述在此不再贅述。
金屬貼片層608可以透過應用於上蓋層606的金屬貼片印刷製程形成於上蓋層606之上。根據上蓋層606之位置，可以使用模具將金屬貼片印刷在上蓋層606的頂部上。於部分實施方式中，金屬貼片層608為形成於圖案化的圖案光阻(未繪示)的開口中，圖案光阻將於金屬貼片填充於其開口中後移除。金屬貼片層608之材料可以是焊料貼片、錫銀貼片、助焊劑、類似物或其組合，以形成具有厚度T3，其介於大約30微米至大約100微米。
接合結構600A透過回焊方式接合至接合結構600B。於回焊製程期間，接合結構600A的金屬貼片層608A之一部分接觸於接合結構600B的金屬貼片層608B之一部 分，以將晶片封裝件100物理性或電性耦合至重分佈層204並自接合結構600A與600B形成接合點224。
具有金屬貼片層608的接合結構600可以提昇接合點224的品質，然而自具有金屬貼片層608的接合結構600形成的接合點224也會具有增加的重量與寬度。
第4C圖繪示晶片封裝件100的接合結構600與重分佈層204，其中接合結構600為透過金屬貼片層形成。接合結構600A耦合至接合墊106與晶片封裝件100的穿越式積體扇出型通孔108，而接合結構600B耦合至開口220(請見第2D圖)中之重分佈層204的金屬線208。於一個實施方式中，接合結構600A與600B被形成為具有高度H1，其介於大約30微米至大約100微米，以及具有寬度W2，其介於大約70微米至大約250微米。接合結構600A與600B可以被形成具有間距P1，其介於大約140微米至大約400微米。
於所繪之實施方式中，接合結構600A與600B皆為金屬貼片層612(612A與612B)。耦合至重分佈層204的接合結構600B為形成於開口220之中(請見第2D圖)，且鈍化層206之一部分形成使第4C圖所繪的兩個開口220被分開來。於一個實施方式中，開口220被形成為具有寬度W1，其介於大約90微米至大約400微米。
金屬貼片層612可以透過應用於穿越式積體扇出型通孔108、接觸區域112、與/或金屬線208的金屬貼片印刷製程形成。根據穿越式積體扇出型通孔108之位置，可以使用模具將金屬貼片印刷在穿越式積體扇出型通孔108、接觸區域 112、與/或金屬線208的頂部上。於部分實施方式中，金屬貼片層612為形成於圖案化的圖案光阻(未繪示)的開口中，圖案光阻將於金屬貼片填充於其開口中後移除。金屬貼片層612之材料可以是焊料貼片、錫銀貼片、助焊劑、類似物或其組合，以形成具有高度H1。
接合結構600A透過回焊方式接合至接合結構600B。於回焊製程期間，接合結構600A的金屬貼片層612A之一部分接觸於接合結構600B的金屬貼片層612B之一部分，以將晶片封裝件100物理性或電性耦合至重分佈層204並自接合結構600A與600B形成接合點224。
第4D圖繪示晶片封裝件100的接合結構600與重分佈層204，其中接合結構600為透過焊料凸塊形成。接合結構600A耦合至接合墊106與晶片封裝件100的穿越式積體扇出型通孔108，而助焊劑層620形成於重分佈層204的開口220(請見第2D圖)中。於一個實施方式中，接合結構600A與600B被形成為具有高度H1，其介於大約20微米至大約50微米，以及具有寬度W2，其介於大約40微米至大約80微米。接合結構600A與600B可以被形成具有間距P1，其介於大約80微米至大約160微米。
於所繪之實施方式中，接合結構600A與600B皆為包含焊球下金屬層630與位於焊球下金屬層630上的焊料凸塊632。助焊劑層620為形成重分佈層204的於開口220之中(請見第2D圖)，且鈍化層206之一部分形成使第4D圖所繪的兩個 開口220被分開來。於一個實施方式中，開口220被形成為具有寬度W1，其介於大約25微米至大約150微米。
焊球下金屬層630可以相似於前述的焊球下金屬層210，因此其敘述在此不再贅述。焊料凸塊632可以相似於前述的連接部212，因此其敘述在此不再贅述。於部分實施方式中，一層的助焊劑(未繪示)可以於焊料凸塊632形成之前形成於接觸區域112與穿越式積體扇出型通孔108上。助焊劑層620形成於開口220之中，且於部分實施方式中，助焊劑層620實質上填充於開口220。
接合結構600A透過回焊方式接合至接合結構600B。於回焊製程期間，接合結構600A的焊料凸塊632之一部分接觸於接合結構600B的助焊劑層620之一部分，以將晶片封裝件100物理性或電性耦合至重分佈層204並自接合結構600A與助焊劑層620形成接合點224。
藉由形成重分佈層於承載基板202上，並將所形成之重分佈層接合至晶片封裝件上，封裝件的翹曲可以被縮減。一般而言，重分佈層將直接形成於晶片封裝件上，而製程將因重分佈層之形成(例如鈍化層蝕刻、鈍化層固化、金屬線沉積等)會導致顯著的翹曲。然而，於所揭露的實施方式中，於形成重分佈層之期間，用於重分佈層的承載基板可以被選擇為像是非常硬質且具有最小或沒有翹曲之型態。此外，承載基板可以被選擇為像是具有與重分佈層相似的熱膨脹係數，亦即，此將縮減因熱膨脹係數不匹配而生的翹曲。
第5A圖至第5C圖繪示依照部分實施方式於形成晶片封裝件700步驟中的中間步驟的剖面示意圖。除非另有說明，第5A圖至第5C圖的元件標號「5xx」指的是與第1A圖至第1D圖的元件標號「1xx」有相同的特徵和過程。第5A圖的晶片封裝件700包含位於承載基板502上的介電層504、接合墊506與位於介電層504上的電性連接部508。於所繪示的實施方式中，承載基板502、介電層504、接合墊506與電性連接部508透過與前述第1A圖的承載基板102、介電層104、接合墊106與電性連接部108相同的材料與方法形成，在此不再贅述。此外，電性連接部508可以作為穿越式模制通孔、穿越式封裝件通孔、與/或穿越式積體扇出型通孔，而其於此將作為穿越式積體扇出型通孔508。於部分實施方式中，穿越式積體扇出型通孔508可以具有大約100微米與大約300微米之間的寬度。
請參照第5A圖，對位結構516為形成於介電層504上。於部分實施方式中，對位結構516透過與前述第1A圖的對位結構106相同的材料與方法形成，在此不再贅述。於部分實施方式中，接合墊506與對位結構516為重分佈層518的背側之一部分。於以下所述之細節，對位結構516將被用於將重分佈層518的背側之上的一或多個晶片精準對位。於部分實施方式中，對位結構為於對位結構516未電性耦合至接合墊506與/或穿越式積體扇出型通孔508時，其為虛設結構。於其他實施方式中，對位結構516可以電性耦合至接合墊506並實質上的穿過穿越式積體扇出型通孔508與封裝件接觸。於所繪示的實施方式中，對位結構516為形成於與最近的一個穿越式積體 扇出型通孔508具有第一距離D1，並形成於與最近的一個接合墊506具有第二距離D2。於部分實施方式中，第一距離D1超過大約60微米，而第二距離超過大約40微米。
請參照第5B圖，一或多個的晶片510附於重分佈層518的背側。於部分實施方式中，晶片510相似於晶片110且透過與前述第1B圖相似的方法附於重分佈層518的背側，在此不再贅述。於其他的實施方式中，晶片510可以使用，例如黏膠層或類似物(未繪示)附於重分佈層518的背側。於部分實施方式中，晶片510可以使用，例如取放裝置附於於重分佈層518的背側。對位結構516用於使位於重分佈層518的背側上的晶片510精準對位，以避免例如晶片510的平移與/或轉動，此將造成晶片封裝件700的電性失真。如第5B圖所示，晶片510未接合至對位結構516上。於晶片附著之後，自上方觀察的對位結構516仍為可見的。
第5C圖繪示晶片510與穿越式積體扇出型通孔508的封裝。於部分實施方式中，晶片510與穿越式積體扇出型通孔508被模制材料514封裝。模制材料514可以透過相似於與前述第1C圖所述之方法成形於晶片510、穿越式積體扇出型通孔508與對位結構516，在此不再贅述。於部分實施方式中，模制材料514直接毗鄰對位結構516的上表面與側壁。於部分實施方式中，模制材料514可以透過與前述第1C圖所述的模制材料114相似的材料形成。實務上，模制材料514透過相似於前述第1D圖所述之方法進行平面化。
請參照第6A圖，重分佈層804之前側形成於封裝件700之上，以形成封裝件800。除非另有說明，第6A圖的元件標號「8xx」指的是與第2A圖至第2E圖的元件標號「2xx」有相同的特徵和過程。於部分實施方式中，重分佈層804之前側可以透過相似於前述第2A圖至第2E圖所述的重分佈層204的材料與方法形成，在此不再贅述。實務上，重分佈層804之前側可以透過相似於前述第3A圖與第3B圖所述的的方法形成，在此不再贅述。於其他的實施方式中，重分佈層804之前側可以直接形成於封裝件700上。
請參照第6A圖，焊球下金屬層810透過相似於前述第2C圖所述的重分佈層204方法附於形成於重分佈層804之前側上並與此電性耦合，在此不再贅述。實務上，連接部812可以透過相似於前述第2C圖所述的的方法形成於焊球下金屬層810上並與此電性耦合，在此不再贅述。
第6B圖繪示封裝件400接合至封裝件800以形成例如封裝件於封裝件上之裝置。封裝件400透過相似於前述第3B圖至第3D圖所述的方法附於封裝件800，在此不再贅述。
第7A圖至第7E圖繪示封裝件800(沿第6A圖中的線段AA’)的平面圖，其示出示例性的形狀和對位結構516的配置。為了清楚描述，接合墊506、電性連接部508與晶片510未繪示於第7A圖至第7E圖之中。應當理解，第7A圖至第7E圖所示的對位結構156的形狀與配置僅為示例，而其他的形狀與配置也是可以的。
請參照第7A圖至第7E圖，對位結構516為形成於重分佈層518之背側的晶片區域701之外側與周圍，晶片區域701為重分佈層518之背側之中固定有晶片510之區域(如前述的視圖)。於所繪示的實施方式中，對位結構516之位置與封裝件800的第一邊緣703具有第三距離D3，並與晶片區域701的第二邊緣705具有第四距離D4。於部分實施方式中，第三距離大於大約300微米，而第四距離介於大約20微米與50微米之間。此外，每一個對位結構516具有第三寬度W3，其大於大約10微米，以及最大尺寸L，其小於大約40微米。
於一個實施方式中，對位結構516具有如第7A圖所繪示的剖面形狀之結構，且其形成鄰於晶片區域701的角落。於其他的實施方式中，對位結構具有如第7B圖所繪示的L形之結構，且每一個的對位結構516具有第一區塊與第二區塊，第一區塊實質上垂直於第二區塊。於其他的實施方式中，對位結構具有如第7C圖至第7E圖所繪示的矩形之結構。應當理解，以上所述之對位結構516的形狀僅為示例，即對位結構516可以具有其他的形狀。
以上所述之對位結構可以用於將晶片於封裝製程期間精準對位，以形成積體電路封裝件。舉例而言，精準對位可以助於防止，例如晶片的平移或是轉動，亦即可以幫助積體電路封裝件因晶片的對位失真所產生的電性失真。
一實施方式為半導體封裝件，其包含具有一或多個晶片的第一封裝件、重分佈層，重分佈層透過第一組接合點耦合至位於第一封裝件之第一側邊的晶片。重分佈層包含多於 一個金屬層，其位於多於一個鈍化層之內，第一組接合點為直接耦合至一或多個金屬層的其中之一者，且第一組連接部耦合至重分佈層的第二側邊，第二側邊相對第一側邊。
其他實施方式為半導體封裝件，其包含具有第一側邊與第二側邊之晶片的晶片封裝件，第二側邊相對第一側邊，封裝材料圍繞第一晶片並具有第一側邊與第二側邊，第一側邊實質上與第一晶片的第一側邊同水平面，第二側邊實質上與第一晶片的第二側邊同水平面，且穿越式封裝件通孔自封裝材料的第一側邊至第二側邊延伸穿越封裝材料。半導體封裝件更包含重分佈層，其透過一組接合點接合至第一晶片的第一側邊與穿越式封裝件，重分佈層包含複數個金屬層，其設置於複數個鈍化層之中，每一組的接合點直接耦合至複數個金屬層的第一金屬層。
另外的實施方式為一種半導體封裝件的形成方法，其包含形成第一晶片封裝件於第一承載基板上，第一晶片封裝件包含第一晶片與第一電性連接部，形成重分佈層於第二承載基板上，重分佈層包含一或多個金屬層，金屬層設置於一或多個鈍化層之中，以及自重分佈層移除第二承載基板，以暴露一或多個鈍化層的第一鈍化層。半導體封裝件的形成方法更包含形成開口於第一鈍化層之中，以暴露一或多個金屬的的第一金屬層的一部分，於第一鈍化層中形成第一組接合結構於開口之中，第一組接合結構為耦合至第一金屬層，以及使用第一組接合屆夠將重分佈層接合至第一晶片封裝件，以形成第一組接合點，至少一個的第一組接合點為接合至第一晶片封裝件的 第一晶片，且至少另一個的第一組接合點為接合至第一電性連接部。
於一實施方式中，半導體封裝件包含第一封裝件，其包含一或多個第一晶片，以及半導體封裝件包含第一重分佈層，其於第一封裝件之第一側邊耦合至一或多個的第一晶片，第一重分佈層包含設置於多於一個鈍化層中的多於一個導體層。半導體封裝件更包含第二重分佈層，其於第一封裝件之第二側邊耦合至一或多個的第一晶片，第二側邊相對第一側邊，第二重分佈層包含一或多個導電圖案，以及半導體封裝件更包含一或多個對位結構，其位於第二重分佈層中，一或多個對位結構自第二重分佈層中的一或多個導電圖案電性解耦。
於其他的實施方式中，半導體封裝件包含晶片封裝件。晶片封裝件包含具有第一側邊的第一重分佈層，第一側邊具有第一區域與圍繞第一區域的第二區域，其中第一重分佈層包含位於第二區域中的對位結構，以及晶片封裝件包含第一晶片，其於第一區域中接合至第一重分佈層的第一側邊。半導體封裝件更包含第二重分佈層，其具有一第二側邊，其中第一晶片透過一組接合點接合至第二重分佈層的第二側邊，第二重分佈層包含複數個金屬層，設置於複數個鈍化層之中，每一組的接合點直接耦合至金屬層的第一金屬層。
於再一實施方式中，半導體封裝件的形成方法包含形成第一重分佈層於第一承載基板之上，第一重分佈層具有第一側邊，第一側邊具有第一區域與圍繞第一區域的第二區域，形成對位結構於第一重分佈層的第一側邊上之第二區域 中，以及使用作為對位標記之對位結構，將第一晶片對位於第一重分佈層的第一側邊上之第一區域中。半導體封裝件的形成方法更包含將第一晶片接合至第一重分佈層的第一側邊之第一區域中，形成第二重分佈層，以及使用一組接合結構將第二重分佈層接合至第一晶片，以形成一組接合點，接合點的其中至少一者接合至第一晶片。
上敘概述了多個實施方法的特徵，使得本技術領域中具有通常知識者更可以理解本揭露之技術態樣。本技術領域中具有通常知識者應當理解，其可以適當地以本揭露作為基礎以設計或修改其他製程以及結構以實現相同目的和/或達到本文所教示之實施方法的相同優點。本技術領域中具有通常知識者應該也要瞭解到，等效的構造並不脫離本揭露的精神和範圍，且作出各種改變、替換和變更仍不脫離本揭露的精神和範圍。

Claims (7)

  1. 一種半導體封裝件，包含：一第一封裝件，包含一或多個第一晶片；一第一重分佈層，於該第一封裝件之一第一側邊耦合至該一或多個第一晶片，該第一重分佈層包含設置於多於一個鈍化層中的多於一個導體層；一第二重分佈層，於該第一封裝件之一第二側邊耦合至該一或多個的第一晶片，且該一或多個第一晶片於該第二側邊上的垂直投影為一第一區域，該第二側邊相對該第一側邊，該第二重分佈層包含一或多個導電圖案；以及一或多個對位結構，位於該第二重分佈層中，該一或多個對位結構自該第二重分佈層中的該一或多個導電圖案電性解耦，且該一或多個對位結構於該第二側邊上的垂直投影落於該第一區域之外，其中該第一封裝件更包含：一電性連接部，自該第一重分佈層延伸至該第二重分佈層；以及一封裝材料，圍繞該一或多個第一晶片、該電性連接部以及該一或多個對位結構。
  2. 如申請專利範圍第1項之半導體封裝件，更包含一第二封裝件，接合至該第二重分佈層，該第二封裝件包含一或多個第二晶片。
  3. 一種半導體封裝件，包含：一晶片封裝件，包含：一第一重分佈層，具有一第一側邊，該第一側邊具有一第一區域與圍繞該第一區域的一第二區域，其中該第一重分佈層包含位於該第二區域中的一對位結構；以及一第一晶片，於該第一區域中接合至該第一重分佈層的該第一側邊，其中該第一晶片於該第一側邊上的垂直投影落於該第一區域內，且該對位結構於該第一側邊上的垂直投影落於該第一區域之外；一第二重分佈層，具有一第二側邊，其中該第一晶片透過一組接合點接合至該第二重分佈層的該第二側邊，該第二重分佈層包含複數個金屬層，設置於複數個鈍化層之中，每一組的該些接合點直接耦合至該些金屬層的一第一金屬層；一封裝材料，圍繞該第一晶片與該對位結構，該封裝材料插入於該第一重分佈層的該第一側邊之該第二區域以及該第二重分佈層的該第二側邊之間：以及一封裝件通孔，自該第一側邊穿過該封裝材料延伸至該第二側邊。
  4. 如申請專利範圍第3項之半導體封裝件，其中每一組的該些接合點包含：一種子層，該種子層之材料係選自於由鈦銅合金、鉭銅合金或其組合所組成之群組；一導電層，鄰於該種子層，該導電層之材料係選自於由銅、鈦、鎳、金或其組合所組成之群組；以及一上蓋層，鄰於該導電層，該上蓋層之材料係選自於由錫、鎳、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金或其組合所組成之群組。
  5. 一種半導體封裝件的形成方法，包含：形成一第一重分佈層於一第一承載基板之上，該第一重分佈層具有一第一側邊，該第一側邊具有一第一區域與圍繞該第一區域的一第二區域；形成一對位結構於該第一重分佈層的該第一側邊上之該第二區域中：使用作為一對位標記之該對位結構，將一第一晶片對位於該第一重分佈層的該第一側邊上之該第一區域中；將該第一晶片接合至該第一重分佈層的該第一側邊之該第一區域中；形成一第二重分佈層；以及使用一組接合結構將該第二重分佈層接合至該第一晶片，以形成一組接合點，該組接合點的其中至少一者接合至該第一晶片。
  6. 如申請專利範圍第5項之半導體封裝件的形成方法，其中形成該第二重分佈層之步驟包含：形成一或多個金屬層，設置於位於一第二承載基板之上的一或多個鈍化層中；移除該第二承載基板，以暴露該一或多個鈍化層的一第一鈍化層；於該第一鈍化層中形成多個開口，以暴露該一或多個金屬層的該第一金屬層，以及於該第一鈍化層中的該些開口之中形成該組接合結構，該組接合結構耦合至該第一金屬層。
  7. 如申請專利範圍第5項之半導體封裝件的形成方法，更包含：自該第一承載基板移除該第一重分佈層，以暴露該第一重分佈層的該第二側邊，該第二側邊相對該第一側邊；自該第一重分佈層的該第二側邊形成多個開口，以暴露該第一重分佈層的多個接合墊；以及使用一第一組之多個導電連接部將一第二封裝件接合至該第一重分佈層，該些導電連接部延伸穿過該第一重分佈層的該第二側邊中的該些開口。
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