CN102246312B - 结场效应晶体管装置结构及其制作方法 - Google Patents

结场效应晶体管装置结构及其制作方法 Download PDF

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CN102246312B
CN102246312B CN200980149820.4A CN200980149820A CN102246312B CN 102246312 B CN102246312 B CN 102246312B CN 200980149820 A CN200980149820 A CN 200980149820A CN 102246312 B CN102246312 B CN 102246312B
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钱德拉·穆利
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Micron Technology Inc
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Abstract

根据本发明技术，提供一种JFET装置结构及其制作方法。具体来说，提供包含具有源极(84)及漏极(86)的半导体衬底的晶体管(80)。所述晶体管(80)还包含形成于所述半导体衬底中所述源极(84)与所述漏极(86)之间的经掺杂沟道(88)，所述沟道(88)经配置以在所述源极(84)与所述漏极(86)之间传递电流。另外，所述晶体管(80)具有：栅极(90)，其包括形成于所述沟道(88)上方的半导体材料；及电介质间隔物(92)，其位于所述栅极(90)的每一侧上。所述源极(84)及所述漏极(86)在空间上与所述栅极(90)分离，使得所述栅极(90)不在所述漏极(86)及源极(84)上方。

Description

结场效应晶体管装置结构及其制作方法
技术领域
本发明的实施例大体来说涉及半导体装置领域。更特定来说，本发明的实施例涉及经改进半导体装置及用于制作经改进半导体装置的技术。
背景技术
当前，用于实施集成电路中的逻辑装置的最常用晶体管是金属氧化物半导体场效应晶体管(MOSFET)。举例来说，互补n型及p型MOSFET的组合(称为“CMOS”的技术)允许形成逻辑装置，例如AND门、NOR门、NAND门及OR门。在CMOS中，n-MOS与p-MOS装置串联连接且无漏极电流流动—除了两个不同状态之间的切换过程期间的小充电电流。MOSFET大小已通过通常称为“按比例缩放”的经改进制作技术而减小，此已导致更小、更快且更密集的电路。
然而，近来，通常与按比例缩放相关联的速度益处已因MOSFET中固有的基本物理限制而减弱。举例来说，为了切换MOSFET的电压状态，必须使所述MOSFET的栅极端子带充足电荷。将接通MOSFET的电荷量与MOSFET的栅极端子的电容成比例。按比例缩放的一个结果是减小栅极绝缘体的厚度以维持可接受小的短沟道效应。此外，为了抵抗可由减小的电介质厚度产生的增加的泄漏电流且借此保持栅极泄漏电流低于可接受水平，所述栅极绝缘体可由具有高于二氧化硅的介电常数(k为3.9)的介电常数“k”的电介质制成。减小的厚度及较高介电常数两者导致较高电容。因此，虽然对于经按比例缩放的CMOS装置，最大漏极电流可增加，但此益处在很大程度上受到增加的电容的限制。结果是，虽然CMOS装置的密度继续增加，但此些装置的速度性能大致不随世代增加。
另一方面，结场效应晶体管(JFET)不利用绝缘栅极。而是，在典型JFET中，栅极是经p掺杂或经n掺杂半导体材料且所述栅极直接接触半导体主体，从而在所述栅极与晶体管的导电沟道之间形成p-n结。由于JFET不利用绝缘栅极，因此JFET中的总栅极电容可大大地减小，此可导致与现有CMOS技术相比较高的晶体管切换速度。
然而，常规JFET因JFET的栅极与沟道之间的p-n结的低正向偏置接通电压(即，二极管接通电压)而具有有限的适用性。在典型JFET中，当栅极电位充分低时，栅极-沟道界面处的耗尽区防止导电。为了接通JFET，提升栅极电位，此使耗尽区变窄，从而允许电流在源极与漏极之间流动。当栅极电位提升到高于栅极与沟道之间的p-n结的正向偏置电位(通常0.6到0.7伏)时，电流接着开始从栅极流动到漏极，从而增加装置的功率消耗。因此，存在对可施加到JFET的电压的限制。因此，常规JFET在利用相对于JFET的二极管接通电压为高的电压的系统或装置中可能不适合。
因此，提供具有与现有CMOS技术相比减小的栅极电容及较快的切换速度的经改进低功率半导体装置可为有利的。具体来说，提供具有解决上文所论述限制的经改进电特性的JFET可为有利的。
附图说明
图1图解说明根据本发明的实施例的基于处理器的装置的框图；
图2图解说明根据本发明的实施例并入有存储器单元阵列的集成电路的部分示意性图解说明；
图3到图5是根据本发明的实施例并入有互补PIN栅极JFET的逻辑装置的电路示意图；
图6到图8是根据本发明的一个或一个以上实施例的JFET的横截面图；
图9图解说明根据本发明的实施例离子从绝缘体到半导体的外扩散；
图10到图12是根据本发明的实施例的多层级JFET结构的横截面图；且
图13是描绘根据本发明的一个或一个以上实施例用于制作JFET的工艺的流程图。
具体实施方式
本发明的实施例涉及JFET，其具有解决上文所论述限制的经改进电特性，从而使其更适合于各种各样的半导体装置，例如逻辑装置及存储器存取装置。具体来说，数个实施例涉及用于提升可施加到JFET的栅极的电压电平而不超过栅极与沟道之间的p-n结的二极管接通电压的方法及装置。数个实施例还涉及包含具有经改进电特性的JFET的系统及装置。
为清晰起见，注意，在论述所沉积材料之间的关系时，使用术语“在…上方”或“在…上面”来描述连接但可或可不直接接触的材料。相反，使用术语“直接在…上”来指示所述材料之间的直接接触。
现在转到图式，且首先参考图1，其图解说明描绘通常由参考编号10指定的基于处理器的系统的框图。系统10可为各种电子装置中的任一者，例如计算机、寻呼机、蜂窝式电话、个人记事本(personal organizer)、控制电路等。在典型的基于处理器的装置中，可包含一个或一个以上处理器的处理器12控制对系统10中系统功能及请求的处理。如将了解，处理器12可包含用于将组件耦合到其的嵌入式北桥或南桥(未展示)。或者，所述桥可与处理器12分离且耦合于处理器12与系统10的各种组件之间。
系统10通常包含电源14。例如，如果系统10是便携式系统，那么电源14可有利地包含永久电池、可替换电池及/或可再充电电池。电源14还可包含AC适配器，因此系统10可插入到(例如)壁式插座中。电源14还可包含DC适配器使得系统10可插入到(例如)车载点烟器中。取决于系统10执行的功能，各种其它装置可耦合到处理器12。例如，用户接口16可耦合到处理器12。用户接口16可包含(例如)按钮、开关、键盘、光笔、鼠标及/或话音辨识系统。显示器18也可耦合到处理器12。显示器18可包含(例如)LCD显示器、CRT、LED及/或音频显示器。此外，RF子系统/基带处理器20也可耦合到处理器12。RF子系统/基带处理器20可包含耦合到RF接收器且耦合到RF发射器(未展示)的天线。一个或一个以上通信端口22也可耦合到处理器12。举例来说，通信端口22可适于耦合到一个或一个以上外围装置24(例如调制解调器、打印机、计算机)或耦合到网络(例如本地区域网络、远程区域网络、内联网或因特网)。
由于处理器12通常通过实施软件程序来控制系统10的发挥作用，因此存储器以操作方式耦合到处理器12以存储并促进各种程序的执行。举例来说，处理器12可耦合到易失性存储器26，所述存储器可包含动态随机存取存储器(DRAM)及/或静态随机存取存储器(SRAM)。易失性存储器26可包含若干个存储器模块，例如单列直插式存储器模块(SIMM)或双列直插式存储器模块(DIMM)。如可了解，易失性存储器26可简单地称为“系统存储器”。易失性存储器26通常相当大使得其可存储以动态方式加载的应用程序及数据。
处理器12还可耦合到非易失性存储器28。非易失性存储器28可包含将结合所述易失性存储器使用的只读存储器(ROM)(例如EPROM)及/或快闪存储器。ROM的大小通常经选择以恰好大到足以存储任何必需操作系统、应用程序及固定数据。另外，非易失性存储器28可包含高容量存储器，例如磁带或磁盘驱动存储器。
系统10的一个或一个以上组件可包含根据本文中所描述的实施例制作的经改进JFET(本文中针对n型以参考编号“32”描绘且针对p型以参考编号“52”描绘)。图2到图5中图解说明其中经改进的JFET可有益的装置的一些实例。具体来说，图2图解说明具有经改进JFET的存储器装置，且图3到图5图解说明具有经改进JFET的集成电路逻辑装置。另外，图6到图13描述经改进的JFET及制作方法。
现在参考图2，其图解说明可在易失性存储器26中实施的集成电路(例如存储器装置29)的部分示意性图解说明。存储器装置29包含存储器单元阵列，所述存储器单元阵列具有可根据本文中所描述的技术制作的晶体管。在一个或一个以上实施例中，存储器装置29可包括动态随机存取存储器(DRAM)装置。存储器装置29包含布置成栅格图案且包括若干个行及列的若干个存储器单元30。存储器单元30(以及对应行及列)的数目可取决于系统要求及制作技术而变化。每一存储器单元30包含包括JFET 32的存取装置及包括电容器34的存储装置。实施所述存取装置以提供对所述存储装置的受控存取。JFET 32包含漏极端子36、源极端子38及栅极40。电容器34耦合到源极端子38。电容器34的不耦合到JFET 32的端子可耦合到接地平面。如下文进一步描述，漏极36耦合到位线(BL)且栅极40耦合到字线(WL)。
应注意，虽然以上描述将存取装置的耦合到电容器34的端子描绘为“源极”38且将存取装置的另一非栅极端子描绘为“漏极”36，但在读取及写入操作期间，JFET 32可经操作使得端子36及38中的每一者总有一个时间作为源极或漏极而操作。因此，出于进一步论述的目的，应认识到，每当将端子识别为“源极”或“漏极”时，此仅出于便利目的，且实际上在JFET 32的操作期间，取决于JFET 32正由施加到端子36、38及40的电压控制的方式，任一端子可为源极或漏极。另外，将了解，存储器装置29的实施例可包含p型JFET、n型JFET或两者的组合。
如先前所描述，存储器阵列布置成系列行及列。为了实施存储器单元30的数据存储能力，经由数据线或读出线(例如位线(BL))将电荷置于JFET 32的漏极36上。通过经由字线(WL)控制栅极40处的电压，可使栅极40与沟道之间的耗尽区变窄使得漏极36处的电荷可流动到电容器34。通过将电荷存储于电容器34中，可将所述电荷解释为存储器单元30中的二进制数据值。例如，对于单位存储装置，可将存储于电容器34中的高于已知阈值电压的正电荷解释为二进制“1”。如果电容器34中的电荷低于所述阈值，那么称二进制值“0”存储于存储器单元30中。出于上文所论述的原因，将了解，栅极40处的电压可限制于充分低于JFET的栅极-沟道结的二极管接通电压的电压。
位线BL用于从存储器单元30读取数据及将数据写入到存储器单元30。字线WL用于激活JFET 32以存取存储器单元30的特定行。因此，存储器装置29还包含外围部分，所述外围部分可包含地址缓冲器42、行解码器44及列解码器46。行解码器44及列解码器46响应于在读取、写入及刷新操作期间提供于地址总线48上的地址信号而选择性地存取存储器单元30。所述地址信号通常由外部控制器(例如，微处理器或另一类型的存储器控制器)提供。列解码器46还可包含读出放大器及输入/输出电路以进一步促进经由位线BL将数据传输到存储器单元30及从存储器单元30传输数据。
在一种操作模式中，存储器装置29于地址缓冲器42处接收特定存储器单元30的地址。地址缓冲器42识别对应于所请求地址的特定存储器单元30的字线WL中的一者并将所述地址传递到行解码器44。行解码器44选择性地激活特定字线WL以激活连接到选定字线WL的每一存储器单元30的JFET 32。列解码器46选择对应于所请求地址的存储器单元30的位线(或若干位线)BL。对于写入操作，由输入/输出电路接收的数据耦合到选定位线(或若干位线)BL且通过JFET 32实现选定存储器单元30的电容器34的充电或放电。电荷对应于二进制数据，如先前所描述。对于读取操作，存储于选定存储器单元30中的由存储于电容器34中的电荷表示的数据耦合到选定位线(或若干位线)BL、由读出放大器放大，且将对应电压电平提供到列解码器46中的输入/输出电路。
如下文所描述，使用根据某些所揭示实施例的经改进JFET的存储器装置29可展现与现有技术存储器装置相比优越的性能。举例来说，存储器装置29可因经改进JFET 32的切换速度的增加而展现增加的性能。此外，由于JFET 32可由与典型基于MOSFET的存储器装置相比较低的栅极电压激活，因此存储于电容器34上的电荷还可减少，此可减少电容器34的泄漏电流。
除存储器装置29以外，经改进的JFET也可用于系统10的其它部分中。举例来说，根据本文中所描述的技术制作的JFET可用于处理器12或系统10的使用集成电路逻辑装置的任一其它组件中。参考图3到图5，其描绘包含经改进JFET的集成电路逻辑装置的各种实施例。首先转到图3，其展示JFET反相器50的实施例。JFET反相器50包含串联耦合于高电压端子54与低电压端子56之间的p型JFET 52及n型JFET 32。所属领域的技术人员将了解，输出端子58将在输入端子60为低时电耦合到高电压端子54且将在输入端子60为高时电耦合到低电压端子56。
图4中图解说明JFET NAND门64且其包含如所展示耦合于高电压端子54与低电压端子56之间的两个p型JFET 52及两个n型JFET 32。输出端子66在输入端子68或70中的任一者为低时电耦合到高电压端子54且在输入端子68及70两者均为高时电耦合到低电压端子56。
图5中展示JFET NOR门72且其包含如所展示耦合于高电压端子54与低电压端子56之间的两个p型JFET 52及两个n型JFET 32。JFET NOR门72的输出端子74在输入端子76及78两者均为低时电耦合到高电压端子54且输出端子74在输入端子76或78中的任一者为高时电耦合到低电压端子56。
关于上文所论述的逻辑装置50、64及72，施加到JFET 32及52的栅极40及62的电压电平可保持低于栅极-沟道结的二极管接通电压以避免过多的栅极到漏极电流及所产生的功率耗散。为了增加可施加到JFET栅极40及62的电压而不引起栅极到漏极电流，可根据下文将论述的一个或一个以上实施例制作JFET 32及52。将了解，图3到图5中所描绘的集成电路逻辑装置仅为实例且利用本文中所揭示的经改进JFET结构及技术可能有许多其它JFET逻辑装置。
参考图6，其图解说明根据本发明的实施例的增强模式n-JFET 80的横截面图。增强模式n-JFET通常具有大于0伏的阈值电压，而耗尽模式晶体管具有小于或等于0伏的阈值电压。应理解，虽然以下描述是针对n-JFET结构，但可在不背离本发明的范围的情况下形成p-JFET结构。举例来说，增强模式n-JFET 80可为绝缘体上硅(SOI)或蓝宝石上硅(SOS)结构。在此些结构中，薄硅膜半导体82位于绝缘体83的表面上。如所图解说明，源极区84及漏极区86可形成于半导体82中。源极区84及漏极区86可经掺杂以形成n+区，如所图解说明。沟道区88可形成于半导体82中源极区与漏极区84与86中间。可根据已知技术对沟道88进行掺杂以形成具有p+栅极界面的n型沟道，如所展示。使沟道88掺杂水平保持低，即小于1e16/cm3。栅极90形成于沟道区88上方。栅极90可根据已知技术形成且可包含在此项技术中已知且通常用于栅极结构的材料。
常规JFET结构提供如下的源极区及漏极区：所述源极区及漏极区在栅极90的边缘内部延伸，使得栅极90的若干部分直接形成于源极区及漏极区84及86上。然而，根据此实施例，源极区及漏极区84及86不在栅极90下方延伸。而是，源极区及漏极区84及86与栅极90的边缘脱离开距离Δ。另外，间隔物92提供于栅极90的每一侧上。间隔物92可具有与距离Δ相当的宽度。具体来说，例如，对于0.1μ装置的典型栅极长度，间隔物92可具有在到的范围中的宽度/厚度。如此，所述宽度/厚度可约为栅极长度的1/3。另外，间隔物92可约为栅极90的长度的1/3。间隔物92以及源极区及漏极区84及86与栅极90之间的距离Δ使晶体管的接通电压偏移且有效地增加所述接通电压。因此，晶体管80可能够提供与较高操作速度相关的较高操作电流。
除提供偏移距离Δ及间隔物90以外，还可在沟道区88下方形成富离子氧化物。此可通过用离子掺杂绝缘体83来形成。举例来说，图7及图8分别图解说明p型及n型经掺杂绝缘体。首先参考图7，可用(例如)磷及/或砷掺杂绝缘体以形成p型绝缘体94。或者，如图8中所图解说明，可用(例如)硼掺杂绝缘体以形成n型绝缘体96。在已对绝缘体94及96进行掺杂之后，在所述绝缘体上方形成JFET结构的后续处理步骤导致掺杂剂外扩散到半导体中。此由图7及图8中所示的箭头98图解说明。另外，图9以图表方式图解说明掺杂剂离子从所述绝缘体到半导体中的外扩散。在图9中，掺杂剂的浓度由线100图解说明。垂直线102图解说明所述绝缘体与半导体的界面。如上文所提及，包含将热施加到所述结构的后续处理步骤导致掺杂剂外扩散到半导体中。如此，不添加额外处理步骤而导致所述掺杂离子的外扩散。所述绝缘体中的掺杂剂浓度可在1e18/cm3到5e18/cm3之间，且可通过任何适合手段来对所述绝缘体进行掺杂。特定来说，可在于所述绝缘体上形成所述半导体结构之前使用任一常规植入及/或固态扩散技术对所述绝缘体进行掺杂。此在沟道下方形成浅的p型或n型区。
在另一实施例中，上述结构可如图10中所图解说明彼此上下地分层以形成多层级装置。层级的堆叠允许装置的3D集成。举例来说，可以若干层级构建逻辑装置以提供额外密度。另外，如下文将更详细论述，例如静态随机存取存储器(SRAM)等存储器可添加于额外层级中或集成于一层级内以提供具有与存储器紧密接近的逻辑的嵌入式技术。另外，在此方案中可容易实现多核心处理设计。
如图10中所示，可根据上文所提及的技术形成JFET结构的第一层级110且可在第一层级110的顶部上形成第二层级112。举例来说，第一层级110的JFET结构可包含n型JFET且第二层级112可包含p型JFET，还涵盖其它配置。来自层级110及112中的每一者的晶体管可经电耦合以形成逻辑装置，例如上文所论述的逻辑装置。具体来说，不同层中的n型及p型晶体管可耦合在一起以形成互补逻辑。虽然图10中仅图解说明两个层级，但应理解，可将两个以上层级堆叠在一起。
在其它实施例中，层级的堆叠可包含减小较高层级的沟道的大小及/或减小较高层级的绝缘层级中的掺杂剂水平。也就是说，堆叠于另一层级的顶部上的层级可具有相对较短的沟道及栅极区。另外，堆叠于另一层级的顶部上的层级的绝缘层可掺杂有比下伏层级的绝缘层少的掺杂剂。图11图解说明具有比第一层级124的对应JFET结构122的沟道120短的沟道118的第二层级116的JFET结构114。第二层级116的沟道118可比第一层级124的沟道120短30％到40％之间。举例来说，假如沟道120约为0.20到0.30微米，那么沟道118的长度可约为0.05到0.15微米。第一层级124中的较长沟道120允许其承受住较高热应变，因为其将经历与后续层级的形成相关联的所有加热及冷却步骤。
另外，第一层级124的经掺杂绝缘体126可具有比第二层级116的绝缘体128高的掺杂剂浓度。第一层级124中的较高浓度可与随后将堆叠于其上的层级的数目相关。此又与热预算(即，晶体管可耐受多少热)有关。对较高浓度掺杂剂的额外热暴露帮助激活所述掺杂剂。具体来说，所植入掺杂剂在其从绝缘体外扩散到硅中时存在至少两种可能性。第一，举例来说，掺杂剂(例如硼)可进入到形成于绝缘体上的硅的晶格结构中。此通常称为掺杂剂以填隙方式定位于硅晶格中。或者，所述掺杂剂可替换或替代形成所述晶格结构的硅。此通常称为掺杂剂以替代方式定位于硅晶格中。所述掺杂剂仅在其以替代方式位于晶格中时被激活。一般来说，为了实现掺杂剂的替代定位需要热步骤。由于第一层级具有较高浓度，因此暴露到与对额外经堆叠层级的处理相关联的额外热步骤可帮助完全激活从绝缘体外扩散到硅晶格中的掺杂剂，即，帮助其以替代方式扩散到晶格中。
本文中所揭示的JFET结构可实施为存储器中的存取装置。如图12中所图解说明，经堆叠JFET结构114及122可耦合到存储器元件130。存储器元件130可为任何适当存储器元件，例如相变装置、电容器及/或自旋力矩技术(STT)装置。在存储器装置中使用经堆叠JFET结构不仅可增加所述存储器装置的密度(因为堆叠存储器单元会增加密度)，而且在与通常使用的MOS晶体管相比时可有利地减小功率消耗。此外，可使用多个层级作为与存储器单元相同的多层级堆叠中的嵌入式逻辑，因此提供具有与存储器紧密接近的逻辑的嵌入式技术。此外，在此方案中可容易实现多核心处理设计。
参考图13，流程图图解说明根据本发明制作晶体管的工艺150。工艺150通过对绝缘层进行掺杂而开始，如在框152处所指示。如上文所论述，可用硼、磷或砷掺杂所述绝缘层以提供绝缘材料的n型或p型掺杂。掺杂剂的浓度可取决于将堆叠于基底层级的顶部上的晶体管的层级的数目而变化。
接下来，在所述绝缘体上方形成半导体材料，如在框154处所指示。处理半导体层以在所述半导体中形成有源区域及隔离区域且形成经n掺杂阱及/或经p掺杂阱，如在框156处所指示。具体来说，常规光刻、氧化及掺杂剂植入技术形成所述有源区域及隔离区域。另外，通过已知技术，形成经n掺杂阱及/或经p掺杂阱以形成n型或p型JFET。所述处理步骤包含导致掺杂剂从绝缘体层外扩散到半导体中的多个加热及冷却步骤。
在框158处，使用已知技术在所述半导体上方形成栅极，且邻近于所述栅极形成间隔物，如在框160处所指示。如上文所论述，所述栅极不形成于所述半导体的源极区及漏极区上方。而是，所述源极区及漏极区从所述栅极移位。此距离可与邻近于所述栅极定位的间隔物的宽度相当。所述间隔物可约为所述栅极的长度的1/3，如上文所论述。
如果将形成额外层级(框162)，那么所述工艺通过在先前层级上方提供绝缘层而继续(如在框164处所指示)，且接着重复工艺150。如上文所描述，经堆叠层级可具有不同于其它层级的沟道长度且还可在相应绝缘层中具有不同掺杂浓度。具体来说，上部层级可具有较短沟道长度且其绝缘层可具有较少掺杂剂。
另外，不同层级可掺杂有不同于其它层级的离子电荷。举例来说，上部层级可经掺杂以提供n型晶体管，而下部层级经掺杂以提供p型晶体管。此外，所述层级可经电耦合以形成逻辑装置且可使用所述晶体管作为存储器单元的存取装置，如上文所描述。
尽管如上所述JFET结构通常提供低功率消耗的优点，但常规上，其已因低正向偏置接通电压将其限制于低电压操作及因此的低驱动电流能力而具有有限适用性。然而，根据本文中所揭示的实施例，JFET结构已呈现在不损害短沟道效应的情况下克服常规JFET结构的限制。
尽管可易于对本发明做出各种修改及替代形式，但已在图式中以实例方式展示了特定实施例并在本文中对所述特定实施例进行了详细描述。然而，应理解，并不打算将本发明限制于所揭示的特定形式。而是，本发明将涵盖归属于由以上所附权利要求书界定的本发明精神及范围内的所有修改、等效内容及替代方案。

Claims (30)

1.一种晶体管，其包括：
经掺杂绝缘体；
半导体衬底，其直接形成于所述经掺杂绝缘体的顶部，并包括源极及漏极；
经掺杂沟道，其形成于所述半导体衬底中所述源极与所述漏极之间，所述沟道经配置以在所述源极与所述漏极之间传递电流，其中所述半导体衬底包含第一掺杂区、包含所述沟道的第二掺杂区、以及第三掺杂区，所述第一、第二、第三掺杂区共同具有npn或pnp配置，且所述第一掺杂区由来自所述经掺杂绝缘体的外扩散形成；
栅极，其包括形成于所述沟道上方的半导体材料；及
电介质间隔物，其位于所述栅极的每一侧上，
其中所述源极及所述漏极在空间上与所述栅极分离，使得所述栅极不位于所述源极及漏极上方。
2.根据权利要求1所述的晶体管，其中所述源极及漏极与所述栅极分离约等于所述电介质间隔物的宽度的距离。
3.根据权利要求1所述的晶体管，其中所述电介质间隔物的所述宽度约为所述栅极的长度的1/3。
4.根据权利要求1所述的晶体管，其中所述电介质间隔物的所述宽度小于所述栅极的所述长度的1/3。
5.根据权利要求1所述的晶体管，其中所述半导体衬底为绝缘体上硅。
6.根据权利要求1所述的晶体管，其中所述半导体衬底为蓝宝石上硅。
7.根据权利要求5所述的晶体管，其中所述绝缘体是经掺杂的。
8.根据权利要求5所述的晶体管，其中所述绝缘体掺杂有硼以在所述沟道下方形成富硼氧化物。
9.一种晶体管，其包括：
经掺杂绝缘体；
硅，其形成于所述经掺杂绝缘体上方；
第一掺杂区，其形成于所述硅中的所述硅与所述经掺杂绝缘体的界面处，其中所述硅中的所述掺杂区由来自所述经掺杂绝缘体的外扩散形成，从而使得所述硅中的离子浓度在所述界面处为最高；
沟道，其形成于所述硅中，其中所述硅包含所述第一掺杂区、形成于所述第一掺杂区上方的包含所述沟道的第二掺杂区、以及第三掺杂区，所述第一、第二、第三掺杂区共同具有npn或pnp配置；
栅极，其形成于所述沟道上方；及
源极及漏极，其形成于所述硅中所述沟道的相对侧上，其中所述源极及漏极不在所述栅极下方延伸。
10.根据权利要求9所述的晶体管，其包括位于所述栅极的每一侧上的绝缘间隔物。
11.根据权利要求10所述的晶体管，其中所述漏极及源极在空间上与所述栅极分离约等于所述间隔物的宽度的距离。
12.根据权利要求11所述的晶体管，其中每一间隔物的所述宽度约为所述栅极的长度的1/3。
13.根据权利要求9所述的晶体管，其中所述绝缘体经掺杂以形成p型绝缘体。
14.根据权利要求9所述的晶体管，其中所述绝缘体经掺杂以形成n型绝缘体。
15.根据权利要求13所述的晶体管，其中所述沟道被掺杂为n型且所述栅极被掺杂为p型以形成n-JFET增强模式装置。
16.根据权利要求14所述的晶体管，其中所述沟道被掺杂为p型且所述栅极被掺杂为n型以形成p-JFET增强模式装置。
17.根据权利要求15所述的晶体管，其中沟道掺杂水平约小于1e16/cm3。
18.根据权利要求16所述的晶体管，其中所述沟道掺杂水平约小于1e16/cm3。
19.根据权利要求13所述的晶体管，其中所述硅的所述第一掺杂区包括位于所述硅与所述绝缘体的界面处的p型区，其中所述p型区在所述沟道下方。
20.根据权利要求13所述的晶体管，其中所述硅的所述第一掺杂区包括位于所述硅与所述绝缘体的所述界面处的n型区，其中所述n型区在所述沟道下方。
21.一种制作晶体管的方法，其包括：
对绝缘体进行掺杂；
在所述经掺杂绝缘体上方形成半导体衬底；
对所述半导体衬底的若干区进行掺杂以形成源极区、漏极区及沟道区，其中所述半导体衬底包含第一掺杂区、包含所述沟道区的第二掺杂区、以及第三掺杂区，所述第一、第二、第三掺杂区共同具有npn或pnp配置，且其中所述第一掺杂区由来自所述绝缘体的掺杂离子的外扩散形成；
在所述沟道区上方形成栅极；及
邻近于所述栅极形成间隔物，其中所述半导体的所述源极区及漏极区与所述栅极分离与所述间隔物的宽度相当的距离。
22.根据权利要求21所述的方法，其中所述间隔物约为所述栅极的长度的1/3。
23.根据权利要求22所述的方法，其包括用硼离子掺杂所述绝缘体。
24.根据权利要求22所述的方法，其包括用砷离子掺杂所述绝缘体。
25.根据权利要求22所述的方法，其包括用磷离子掺杂所述绝缘体。
26.一种制作多层级晶体管的方法，其中每一层级包括：
对绝缘体进行掺杂；
在所述经掺杂绝缘体上方形成半导体衬底；
对所述半导体衬底的若干区进行掺杂以形成源极区、漏极区及沟道区，其中所述半导体衬底包含第一掺杂区、包含所述沟道区的第二掺杂区、以及第三掺杂区，所述第一、第二、第三掺杂区共同具有npn或pnp配置，且其中所述第一掺杂区由来自所述绝缘体的掺杂离子的外扩散形成；
在所述沟道区上方形成栅极；及
邻近于所述栅极形成间隔物，其中所述半导体的所述源极区及漏极区与所述栅极分离与所述间隔物的宽度相当的距离。
27.根据权利要求26所述的方法，其中上部层级中的晶体管的沟道区比下部层级中的晶体管的沟道区短。
28.根据权利要求26所述的方法，其中上部层级的绝缘体具有比下部层级的绝缘体低的掺杂剂浓度。
29.根据权利要求26所述的方法，其中经堆叠层级中的至少一个层级包括耦合到存储器元件的晶体管。
30.根据权利要求26所述的方法，其中将晶体管耦合在一起以形成互补逻辑装置。
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US20130285124A1 (en) 2013-10-31
US9831246B2 (en) 2017-11-28
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US8481372B2 (en) 2013-07-09

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