CN102214563B - 一种金属栅极/高k栅介质叠层结构的制备和成形方法 - Google Patents

一种金属栅极/高k栅介质叠层结构的制备和成形方法 Download PDF

Info

Publication number
CN102214563B
CN102214563B CN201010145261.4A CN201010145261A CN102214563B CN 102214563 B CN102214563 B CN 102214563B CN 201010145261 A CN201010145261 A CN 201010145261A CN 102214563 B CN102214563 B CN 102214563B
Authority
CN
China
Prior art keywords
etching
layer
gate
hard mask
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010145261.4A
Other languages
English (en)
Other versions
CN102214563A (zh
Inventor
徐秋霞
李永亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ruili Flat Core Microelectronics Guangzhou Co Ltd
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201010145261.4A priority Critical patent/CN102214563B/zh
Priority to US13/002,079 priority patent/US8258063B2/en
Priority to PCT/CN2010/001456 priority patent/WO2011124003A1/zh
Publication of CN102214563A publication Critical patent/CN102214563A/zh
Application granted granted Critical
Publication of CN102214563B publication Critical patent/CN102214563B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Composite Materials (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种高金属栅极/高K栅介质叠层结构的制备和成形方法：1)在硅衬底上生成一层SiON和SiO2界面层；2)在界面层上沉积高K栅介质膜；3)对高K介质膜进行快速热退火；4)在高K介质上沉积TaN金属栅电极膜；5)在TaN金属栅极上沉积多晶硅栅层，然后沉积硬掩膜层；6)光刻形成胶膜图形，通过反应离子刻蚀对硬掩膜介质层进行各向异性刻蚀，将胶膜图形转移到硬掩膜层；7)去胶，以硬掩膜为掩蔽层，采用Cl2/HBr混合气体反应离子刻蚀多晶硅栅；8)以硬掩膜为掩蔽层，通过BCl3基刻蚀气体刻蚀对TaN金属栅/高K栅介质叠层进行各向异性和高选择比刻蚀。

Description

一种金属栅极/高K栅介质叠层结构的制备和成形方法
技术领域
本发明属于半导体技术领域，特别指一种金属栅极/高K栅介质叠层结构的制备方法。本发明适合于32纳米及以下技术代高性能互补型金属氧化物半导体(CMOS)器件的应用。
技术背景
随着CMOS器件特征尺寸的不断缩小，高介电常数(K)栅介质和金属栅电极的应用势在必行。采用高K介质，由于在同样的等效氧化物厚度(EOT)下有较厚的物理厚度，所以可大大降低栅极漏电流。而金属栅的采用可消除多晶硅栅的耗尽效应和硼的穿透效应，提高器件可靠性，减小栅电阻。但要把金属栅/高K介质工艺集成的CMOS技术中仍然面临着很多挑战。特别是在先栅工艺CMOS技术中，高K栅介质/金属栅极叠层结构的刻蚀成形难度很大，包括刻蚀速率、刻蚀选择比，叠层结构的刻蚀剖面的各向异性程度等都很难同时兼顾好。为降低刻蚀难度和防止后续源/漏区高剂量离子注入时离子穿透金属栅极，可以采用多晶硅/薄层金属栅叠层结构来代替单一的厚的金属栅极。即便如此，金属栅叠层结构的高度陡直的各向异性刻蚀剖面和对硅衬底和硬掩膜刻蚀的高选择比仍然是一个非常大的挑战。
发明内容
本发明的目的在于提供一种金属栅极/高K栅介质叠层结构的制备方法，不仅可以获得叠层结构陡直的刻蚀剖面，而且对衬底硅具有良好的刻蚀选择比，还与CMOS工艺完全兼容，成本低，便于集成电路产业化。
为实现上述目的，本发明提供的金属栅极/高K栅介质叠层结构的制备和成形方法，其主要步骤为：
步骤1)在硅衬底上生成一层SiON和SiO2界面层；
步骤2)在界面层上沉积高K栅介质膜；
步骤3)对高K介质膜进行快速热退火；
步骤4)在高K介质上沉积TaN金属栅电极膜；
步骤5)在TaN金属栅极上沉积多晶硅栅层，然后沉积硬掩膜层；
步骤6)光刻形成胶膜图形，通过反应离子刻蚀对硬掩膜介质层进行各向异性刻蚀，将胶膜图形转移到硬掩膜层；
步骤7)去胶，以硬掩膜为掩蔽层，采用Cl2/HBr混合气体反应离子刻蚀多晶硅栅；
步骤8)以硬掩膜为掩蔽层，通过BCl3基刻蚀气体刻蚀对TaN金属栅/高K栅介质叠层进行各向异性和高选择比刻蚀。
所述方法中，步骤1之前先将硅衬底于清洗液中浸泡2-10分钟进行清洗；清洗液按重量计，氢氟酸∶异丙醇∶水为0.2-1.5％∶0.01-0.10％∶1％。
所述方法中，步骤1中采用先注入氮再快速热氧化形成，或先氧化再等离子氮化形成SiON界面层。
所述方法中，步骤2中高K栅介质膜是Hf基掺杂氧化物：HfO2、HfON、HfSiO、HfSiON、HfTaON、HfAlO、HfAlON、HfSiAlON、HfLaO或HfLaON；所述高K栅介质层通过物理气相淀积、金属有机化学气相淀积或原子层淀积工艺形成。
所述方法中，步骤3中快速热退火温度600-1000℃，时间10-120秒。
所述方法中，步骤4中TaN金属栅采用N2/Ar气氛中反应溅射Ta靶形成，或用有机化学气相淀积或原子层淀积形成。
所述方法中，步骤5中硬掩膜介层是氧化硅、氮化硅或其叠层形成。
所述方法中，步骤6中硬掩膜的刻蚀采用氟基反应离子刻蚀；氟基反应离子刻蚀采用的是CF4、CHF3或SF6。
所述方法中，步骤8中BCl3基刻蚀气体为BCl3/Cl2/Ar/O2的混合气体；BCl3流量为20-120sccm，Cl2流量为5-30sccm，O2流量为2-15sccm，Ar流量为10-60sccm；刻蚀功率上电极为120-450W，下电极为30-200W；腔体工作压力为4-15mτ；腔体和电极温度50-150℃。
本发明不仅可以获得陡直的叠层结构刻蚀剖面，而且对衬底硅具有良好的刻蚀选择比。这是由于BCl3气体不仅可以产生Cl元素与金属形成挥发的产物，而且还可以通过形成BOClx挥发性产物达到刻蚀金属氧化物目的；另外，由于高K材料也与金属氧化物相关，所以BCl3气体也可以刻蚀Hf基高K材料。而且BCl3气体可与Si衬底形成起到钝化衬底作用的Si-B键，提高对Si衬底的选择比。本发明在高电场、低压力下采用BCl3/Cl2/Ar/少量O2混合气体作为TaN/高K介质叠层结构的刻蚀气体，Cl2和O2的加入有利于陡直刻蚀剖面的形成，高电场、低压力有利于陡直刻蚀剖面的形成，适当高的腔体和电极温度有利于反应副产物挥发被抽走。通过优化上、下电极的功率、气体的压强以及其比例，不仅可得到了陡直的刻蚀剖面，而且对硅衬底具有良好的刻蚀选择比，硅的损耗很小。而且该方法与CMOS工艺兼容，成本低，为金属栅极/高K栅介质叠层结构集成到先进的CMOS技术中攻克了难关，便于集成电路产业化。
附图说明
图1是本发明制备完成的硬掩膜/多晶硅/TaN金属栅极/高K介质层/SiO2界面层/硅衬底叠层结构的扫描电镜照片；
图2是本发明采用氟基反应离子刻硬掩膜，然后采用Cl2/HBr气体反应离子刻蚀多晶硅栅后的扫描电镜照片；
图3是本发明最后采用BCl3/Cl2/O2/Ar混合气体反应离子刻蚀TaN金属栅极/高K介质层完成的叠层结构的刻蚀后的扫描电镜照片。
具体实施方式
本发明是针对32nm/22nm CMOS技术节点中必须集成高K栅介质/金属栅极新工艺所面临的挑战，提出了一种金属栅极/高K栅介质叠层结构的制备和成形方法。
以下结合附图对本发明的特征进行说明，所举实例只用于解释本发明，并非用于限定本发明的范围。
步骤1)清洗：先用常规方法清洗，然后用氢氟酸/异丙醇/水混合溶液于室温中浸泡2-10分钟，氢氟酸/异丙醇/水混合溶液重量浓度比为0.2-1.5％∶0.01-0.10％∶1％；然后去离子水冲洗，甩干进炉；
步骤2)在硅衬底上生成一层超薄的SiON和SiO2界面层，界面层SiON采用先注入氮再快速热氧化形成或先氧化再等离子氮化形成；
步骤3)在界面层上沉积高K栅介质膜，即Hf基掺杂氧化物，如HfO2、HfON、HfSiO、HfSiON、HfTaON、HfAlO、HfAlON、HfSiAlON、HfLaO、HfLaON等；所述高K栅介质层通过物理气相淀积、金属有机化学气相淀积或原子层淀积工艺形成；
步骤4)对高K介质膜进行快速热退火，温度600-1000℃，时间10-120秒；
步骤5)沉积TaN金属栅电极膜，采用N2/Ar气氛中反应溅射Ta靶形成，也可用有机化学气相淀积或原子层淀积形成；
步骤6)在TaN金属栅电极上沉积多晶硅栅层，然后沉积硬掩膜层，硬掩膜介层可以是氧化硅、氮化硅或其叠层形成(图1为制备完成的硬掩膜/多晶硅栅/TaN金属栅极/高K介质/SiO2界面层/硅衬底叠层结构的扫描电镜照片)；
步骤7)光刻形成胶膜图形，通过氟基反应离子刻蚀，如CF4、CHF3或SF6等的反应离子刻蚀对硬掩膜介质层进行各向异性刻蚀，将胶膜图形转移到硬掩膜层；
步骤8)去胶后，以硬掩膜为掩蔽层，采用Cl2/HBr混合气体反应离子刻蚀多晶硅栅(图2为刻蚀多晶硅栅后的扫描电镜照片)；
步骤9)进一步以硬掩膜为掩蔽层，通过采用BCl3基刻蚀气体的干法刻蚀对TaN金属栅/高K栅介质叠层进行各向异性和高选择比刻蚀。BCl3基刻蚀气体为BCl3/Cl2/Ar/少量O2的混合气体，其中BCl3流量为20-120sccm，Cl2流量为5-30sccm，O2流量为2-15sccm，Ar流量为10-60sccm；刻蚀功率上电极为120-450W，下电极为30-200W；腔体工作压力为4-15mτ；腔体和电极温度50-150℃(图3为最后采用BCl3/Cl2/O2/Ar混合气体反应离子刻蚀TaN金属栅极/高K介质层完成的叠层结构刻蚀后的扫描电镜照片)。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种多晶硅栅/金属栅极/高K栅介质叠层结构的制备和成形方法，主要步骤为：
步骤1)在硅衬底上生成一层SiON和SiO2界面层；
步骤2)在界面层上沉积高K栅介质膜；
步骤3)对高K介质膜进行快速热退火；
步骤4)在高K介质上沉积TaN金属栅电极膜；
步骤5)在TaN金属栅极上沉积多晶硅栅层，然后沉积硬掩膜层；
步骤6)光刻形成胶膜图形，通过反应离子刻蚀对硬掩膜介质层进行各向异性刻蚀，将胶膜图形转移到硬掩膜层；
步骤7)去胶，以硬掩膜为掩蔽层，采用Cl2/HBr混合气体反应离子刻蚀多晶硅栅；
步骤8)以硬掩膜为掩蔽层，通过BCl3基刻蚀气体刻蚀对TaN金属栅/高K栅介质叠层进行各向异性和高选择比刻蚀；
BCl3基刻蚀气体为BCl3/Cl2/Ar/O2的混合气体；BCl3流量为20-120sccm，Cl2流量为5-30sccm，O2流量为2-15sccm，Ar流量为10-60sccm；刻蚀功率上电极为120-450W，下电极为30-200W；腔体工作压力为4-15mτ；腔体和电极温度50-150℃。
2.根据权利要求1所述方法，其特征在于，步骤1之前先将硅衬底于清洗液中浸泡2-10分钟进行清洗；清洗液按重量计，氢氟酸∶异丙醇∶水为0.2-1.5％∶0.01-0.10％∶1％。
3.根据权利要求1所述方法，其特征在于，步骤1中采用先注入氮再快速热氧化形成，或先氧化再等离子氮化形成SiON界面层。
4.根据权利要求1所述方法，其特征在于，步骤2中高K栅介质膜是Hf基掺杂氧化物：HfO2、HfON、HfSiO、HfSiON、HfTaON、HfAlO、HfAlON、HfSiAlON、HfLaO或HfLaON；所述高K栅介质层通过物理气相淀积、金属有机化学气相淀积或原子层淀积工艺形成。
5.根据权利要求1所述方法，其特征在于，步骤3中快速热退火温度600-1000℃，时间10-120秒。
6.根据权利要求1所述方法，其特征在于，步骤4中TaN金属栅采用N2/Ar气氛中反应溅射Ta靶形成，或用有机化学气相淀积或原子层淀积形成。
7.根据权利要求1所述方法，其特征在于，步骤5中硬掩膜介质层是氧化硅、氮化硅或其叠层形成。
8.根据权利要求1所述方法，其特征在于，步骤6中硬掩膜的刻蚀采用氟基反应离子刻蚀。
9.根据权利要求8所述方法，其特征在于，氟基反应离子刻蚀采用的是CF4、CHF3或SF6。
CN201010145261.4A 2010-04-09 2010-04-09 一种金属栅极/高k栅介质叠层结构的制备和成形方法 Active CN102214563B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201010145261.4A CN102214563B (zh) 2010-04-09 2010-04-09 一种金属栅极/高k栅介质叠层结构的制备和成形方法
US13/002,079 US8258063B2 (en) 2010-04-09 2010-09-21 Method for manufacturing a metal gate electrode/high K dielectric gate stack
PCT/CN2010/001456 WO2011124003A1 (zh) 2010-04-09 2010-09-21 一种金属栅极/高k栅介质叠层结构的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010145261.4A CN102214563B (zh) 2010-04-09 2010-04-09 一种金属栅极/高k栅介质叠层结构的制备和成形方法

Publications (2)

Publication Number Publication Date
CN102214563A CN102214563A (zh) 2011-10-12
CN102214563B true CN102214563B (zh) 2013-03-13

Family

ID=44745824

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010145261.4A Active CN102214563B (zh) 2010-04-09 2010-04-09 一种金属栅极/高k栅介质叠层结构的制备和成形方法

Country Status (3)

Country Link
US (1) US8258063B2 (zh)
CN (1) CN102214563B (zh)
WO (1) WO2011124003A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120244693A1 (en) * 2011-03-22 2012-09-27 Tokyo Electron Limited Method for patterning a full metal gate structure
CN102915917B (zh) * 2011-08-03 2015-02-11 中国科学院微电子研究所 一种互补型金属氧化物半导体场效应晶体管的制备方法
US8946002B2 (en) * 2012-07-24 2015-02-03 Semiconductor Components Industries, Llc Method of forming a semiconductor device having a patterned gate dielectric and structure therefor
CN103855007A (zh) * 2012-11-30 2014-06-11 中国科学院微电子研究所 P型mosfet的制造方法
CN103855006A (zh) 2012-11-30 2014-06-11 中国科学院微电子研究所 半导体器件的制造方法
CN104752153A (zh) * 2013-12-29 2015-07-01 北京北方微电子基地设备工艺研究中心有限责任公司 基片刻蚀方法
JP6163446B2 (ja) * 2014-03-27 2017-07-12 株式会社東芝 半導体装置の製造方法
CN113785382B (zh) * 2020-04-10 2023-10-27 株式会社日立高新技术 蚀刻方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1450656A (zh) * 2003-05-15 2003-10-22 上海集成电路研发中心有限公司 一种新的栅介质堆层结构
US6869868B2 (en) * 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
CN101136326A (zh) * 2006-08-31 2008-03-05 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN101447420A (zh) * 2007-11-28 2009-06-03 中国科学院微电子研究所 一种制备高介电常数栅介质薄膜铪硅氧氮的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4778532A (en) * 1985-06-24 1988-10-18 Cfm Technologies Limited Partnership Process and apparatus for treating wafers with process fluids
CN1327260A (zh) * 2001-06-13 2001-12-19 旺宏电子股份有限公司 半导体金属蚀刻工艺的方法
US20050081781A1 (en) * 2003-10-17 2005-04-21 Taiwan Semiconductor Manufacturing Co. Fully dry, Si recess free process for removing high k dielectric layer
US8791001B2 (en) * 2008-09-08 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. N2 based plasma treatment and ash for HK metal gate protection
CN101620997A (zh) * 2009-07-24 2010-01-06 中国科学院微电子研究所 一种高k金属栅结构的刻蚀方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869868B2 (en) * 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
CN1450656A (zh) * 2003-05-15 2003-10-22 上海集成电路研发中心有限公司 一种新的栅介质堆层结构
CN101136326A (zh) * 2006-08-31 2008-03-05 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN101447420A (zh) * 2007-11-28 2009-06-03 中国科学院微电子研究所 一种制备高介电常数栅介质薄膜铪硅氧氮的方法

Also Published As

Publication number Publication date
CN102214563A (zh) 2011-10-12
WO2011124003A1 (zh) 2011-10-13
US20110256704A1 (en) 2011-10-20
US8258063B2 (en) 2012-09-04

Similar Documents

Publication Publication Date Title
CN102214563B (zh) 一种金属栅极/高k栅介质叠层结构的制备和成形方法
CN102280376B (zh) 一种用于cmos器件的双金属栅双高介质的集成方法
CN102280375B (zh) 一种先栅工艺中叠层金属栅结构的制备方法
CN102915917B (zh) 一种互补型金属氧化物半导体场效应晶体管的制备方法
CN101924026B (zh) 降低界面层厚度的方法
CN101728257B (zh) 一种栅介质/金属栅集成结构的制备方法
CN102237269B (zh) 以氮化铝为势垒层的Mo基金属栅叠层结构的刻蚀方法
CN107591363B (zh) 半导体器件的形成方法
CN102237268B (zh) 一种插入式TiN金属栅叠层结构的制备和刻蚀方法
CN103219381B (zh) Ge基三栅器件及制造方法
CN102651313B (zh) Pmos器件叠层结构的制备和栅功函数调节方法
CN102054703B (zh) 一种无cmp的适用于后栅工艺的平坦化制备工艺
CN102655112B (zh) 实现锗基mos器件有源区之间隔离的方法
CN103855013A (zh) N型mosfet的制造方法
CN104299994B (zh) 晶体管及晶体管的形成方法
CN102064103A (zh) 高k栅介质层的制备方法
US8163620B2 (en) Method for etching Mo-based metal gate stack with aluminium nitride barrier
CN105374734A (zh) 半导体结构的形成方法
CN101404252A (zh) 全硅化物金属栅电极制造工艺
CN104465378A (zh) 半导体器件的制作方法
CN102468157A (zh) 一种高k栅介质的刻蚀方法
CN103871886B (zh) 晶体管的形成方法
CN103137460B (zh) 一种分子尺度界面SiO2的形成和控制方法
CN102315117B (zh) 一种Mo基/TaN金属栅叠层结构的刻蚀方法
CN103617949A (zh) 利用三氟化氮抑制高介电常数栅介质层和硅衬底之间界面层生长的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20201214

Address after: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province

Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd.

Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3

Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20220425

Address after: 510000 room 710, Jianshe building, No. 348, Kaifa Avenue, Huangpu District, Guangzhou, Guangdong

Patentee after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd.

Address before: 510000 601, building a, 136 Kaiyuan Avenue, Huangpu District, Guangzhou City, Guangdong Province

Patentee before: AoXin integrated circuit technology (Guangdong) Co.,Ltd.

TR01 Transfer of patent right