CN102203934B - 使用定向剥落在绝缘体结构上形成半导体的方法和装置 - Google Patents
使用定向剥落在绝缘体结构上形成半导体的方法和装置 Download PDFInfo
- Publication number
- CN102203934B CN102203934B CN200980143710.7A CN200980143710A CN102203934B CN 102203934 B CN102203934 B CN 102203934B CN 200980143710 A CN200980143710 A CN 200980143710A CN 102203934 B CN102203934 B CN 102203934B
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- China
- Prior art keywords
- semiconductor wafer
- depth
- donor semiconductor
- weakened
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/011—Division of wafers or substrates to produce devices, each consisting of a single electric circuit element
- H10D89/015—Division of wafers or substrates to produce devices, each consisting of a single electric circuit element the wafers or substrates being other than semiconductor bodies, e.g. insulating bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Physical Vapour Deposition (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/290,384 US8003491B2 (en) | 2008-10-30 | 2008-10-30 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
| US12/290,362 US7816225B2 (en) | 2008-10-30 | 2008-10-30 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
| US12/290,384 | 2008-10-30 | ||
| US12/290,362 | 2008-10-30 | ||
| PCT/US2009/062504 WO2010059361A2 (en) | 2008-10-30 | 2009-10-29 | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102203934A CN102203934A (zh) | 2011-09-28 |
| CN102203934B true CN102203934B (zh) | 2014-02-12 |
Family
ID=41559616
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200980143710.7A Expired - Fee Related CN102203934B (zh) | 2008-10-30 | 2009-10-29 | 使用定向剥落在绝缘体结构上形成半导体的方法和装置 |
| CN200980143709.4A Expired - Fee Related CN102203933B (zh) | 2008-10-30 | 2009-10-29 | 使用定向剥落在绝缘体结构上形成半导体的方法和装置 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200980143709.4A Expired - Fee Related CN102203933B (zh) | 2008-10-30 | 2009-10-29 | 使用定向剥落在绝缘体结构上形成半导体的方法和装置 |
Country Status (6)
| Country | Link |
|---|---|
| EP (2) | EP2359400A2 (cg-RX-API-DMAC7.html) |
| JP (2) | JP5650653B2 (cg-RX-API-DMAC7.html) |
| KR (2) | KR20110081318A (cg-RX-API-DMAC7.html) |
| CN (2) | CN102203934B (cg-RX-API-DMAC7.html) |
| TW (2) | TWI451534B (cg-RX-API-DMAC7.html) |
| WO (2) | WO2010059361A2 (cg-RX-API-DMAC7.html) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5703853B2 (ja) * | 2011-03-04 | 2015-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| FR3055063B1 (fr) * | 2016-08-11 | 2018-08-31 | Soitec | Procede de transfert d'une couche utile |
| CN111834205B (zh) * | 2020-07-07 | 2021-12-28 | 中国科学院上海微系统与信息技术研究所 | 一种异质半导体薄膜及其制备方法 |
| CN114975765A (zh) * | 2022-07-19 | 2022-08-30 | 济南晶正电子科技有限公司 | 复合单晶压电薄膜及其制备方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
| WO2004044975A1 (en) * | 2002-11-12 | 2004-05-27 | S.O.I. Tec Silicon On Insulator Technologies | Semiconductor structure, and methods for fabricating same |
| US20060220127A1 (en) * | 2003-04-22 | 2006-10-05 | Forschungszentrum Julich Gmbh | Method for producing a tensioned layer on a substrate, and a layer structure |
| US7148124B1 (en) * | 2004-11-18 | 2006-12-12 | Alexander Yuri Usenko | Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2714524B1 (fr) * | 1993-12-23 | 1996-01-26 | Commissariat Energie Atomique | Procede de realisation d'une structure en relief sur un support en materiau semiconducteur |
| US6048411A (en) * | 1997-05-12 | 2000-04-11 | Silicon Genesis Corporation | Silicon-on-silicon hybrid wafer assembly |
| TW437078B (en) * | 1998-02-18 | 2001-05-28 | Canon Kk | Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof |
| JP3031904B2 (ja) * | 1998-02-18 | 2000-04-10 | キヤノン株式会社 | 複合部材とその分離方法、及びそれを利用した半導体基体の製造方法 |
| US20010007790A1 (en) * | 1998-06-23 | 2001-07-12 | Henley Francois J. | Pre-semiconductor process implant and post-process film separation |
| FR2811807B1 (fr) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
| JP2002124652A (ja) * | 2000-10-16 | 2002-04-26 | Seiko Epson Corp | 半導体基板の製造方法、半導体基板、電気光学装置並びに電子機器 |
| FR2830983B1 (fr) * | 2001-10-11 | 2004-05-14 | Commissariat Energie Atomique | Procede de fabrication de couches minces contenant des microcomposants |
| EP1429381B1 (en) * | 2002-12-10 | 2011-07-06 | S.O.I.Tec Silicon on Insulator Technologies | A method for manufacturing a material compound |
| US7176528B2 (en) | 2003-02-18 | 2007-02-13 | Corning Incorporated | Glass-based SOI structures |
| JP2006324051A (ja) * | 2005-05-17 | 2006-11-30 | Nissin Ion Equipment Co Ltd | 荷電粒子ビーム照射方法および装置 |
| JP4977999B2 (ja) * | 2005-11-21 | 2012-07-18 | 株式会社Sumco | 貼合せ基板の製造方法及びその方法で製造された貼合せ基板 |
| US7691730B2 (en) * | 2005-11-22 | 2010-04-06 | Corning Incorporated | Large area semiconductor on glass insulator |
-
2009
- 2009-10-28 TW TW098136607A patent/TWI451534B/zh not_active IP Right Cessation
- 2009-10-28 TW TW098136605A patent/TWI430338B/zh not_active IP Right Cessation
- 2009-10-29 JP JP2011534755A patent/JP5650653B2/ja not_active Expired - Fee Related
- 2009-10-29 CN CN200980143710.7A patent/CN102203934B/zh not_active Expired - Fee Related
- 2009-10-29 WO PCT/US2009/062504 patent/WO2010059361A2/en not_active Ceased
- 2009-10-29 KR KR1020117012220A patent/KR20110081318A/ko not_active Abandoned
- 2009-10-29 EP EP09744304A patent/EP2359400A2/en not_active Withdrawn
- 2009-10-29 WO PCT/US2009/062531 patent/WO2010059367A2/en not_active Ceased
- 2009-10-29 KR KR1020117012221A patent/KR101568898B1/ko not_active Expired - Fee Related
- 2009-10-29 JP JP2011534746A patent/JP5650652B2/ja not_active Expired - Fee Related
- 2009-10-29 CN CN200980143709.4A patent/CN102203933B/zh not_active Expired - Fee Related
- 2009-10-29 EP EP09744303A patent/EP2356676A2/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
| WO2004044975A1 (en) * | 2002-11-12 | 2004-05-27 | S.O.I. Tec Silicon On Insulator Technologies | Semiconductor structure, and methods for fabricating same |
| US20060220127A1 (en) * | 2003-04-22 | 2006-10-05 | Forschungszentrum Julich Gmbh | Method for producing a tensioned layer on a substrate, and a layer structure |
| US7148124B1 (en) * | 2004-11-18 | 2006-12-12 | Alexander Yuri Usenko | Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102203934A (zh) | 2011-09-28 |
| JP5650652B2 (ja) | 2015-01-07 |
| CN102203933B (zh) | 2015-12-02 |
| JP5650653B2 (ja) | 2015-01-07 |
| KR101568898B1 (ko) | 2015-11-12 |
| WO2010059367A3 (en) | 2010-08-05 |
| TWI430338B (zh) | 2014-03-11 |
| TW201030815A (en) | 2010-08-16 |
| KR20110081318A (ko) | 2011-07-13 |
| TW201036112A (en) | 2010-10-01 |
| TWI451534B (zh) | 2014-09-01 |
| WO2010059367A2 (en) | 2010-05-27 |
| KR20110081881A (ko) | 2011-07-14 |
| JP2012507870A (ja) | 2012-03-29 |
| CN102203933A (zh) | 2011-09-28 |
| WO2010059361A3 (en) | 2010-08-12 |
| WO2010059361A2 (en) | 2010-05-27 |
| EP2356676A2 (en) | 2011-08-17 |
| JP2012507868A (ja) | 2012-03-29 |
| EP2359400A2 (en) | 2011-08-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140212 Termination date: 20161029 |