CN102157447B - 切割半导体晶片的方法、从半导体晶片切割的芯片以及从半导体晶片切割的芯片的阵列 - Google Patents

切割半导体晶片的方法、从半导体晶片切割的芯片以及从半导体晶片切割的芯片的阵列 Download PDF

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CN102157447B
CN102157447B CN201010620709.3A CN201010620709A CN102157447B CN 102157447 B CN102157447 B CN 102157447B CN 201010620709 A CN201010620709 A CN 201010620709A CN 102157447 B CN102157447 B CN 102157447B
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保罗·A·霍西尔
尼古拉斯·J·萨拉蒂诺
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Abstract

一种切割半导体晶片的方法，包括：在该晶片的背面主表面中切割基准槽；在该背面主表面中切割背槽，该背槽相对该基准槽定位；确定所需的芯片边缘相对该基准槽的位置；以及在某个路径中施加辐射能量，从而在该晶片内沿该路径形成一系列改造区域。该晶片的晶体结构在这一系列改造区域中被改变，并且该激光的边缘相对该芯片边缘的所需位置对齐且与该背槽对齐。该方法包括沿这一系列改造区域将该晶片分开成在这一系列改造区域任一侧上的该晶片的分割区域。

Description

切割半导体晶片的方法、从半导体晶片切割的芯片以及从半导体晶片切割的芯片的阵列
技术领域
本公开涉及切割半导体晶片的方法、从半导体晶片切割的芯片和从半导体晶片切割的芯片的阵列，具体地，使用辐射能量切割，更具体地，使用激光。
背景技术
图7是现有的切割晶片的方法的表述。该现有技术教导使用机械刀片来切割晶片以形成芯片或模片。例如，共有美国专利4,814,296教导利用刀片在晶片背面切割槽，然后利用刀片从正面切透晶片。如图7所示，在正面的切口对齐在该背槽的宽度内。为了抵消由于切割过程导致的机械应力(例如，破裂)，美国专利4,814,296教导使用额外的步骤来蚀刻正面以形成造成正面切口的凹槽。
美国专利7,498,238教导使用刀片来在晶片上部分刻凹痕，并且使用激光来在添加到该晶片以保护该基片上构造的硅帽部分生成改造层，例如，传感器或微机械。晶片和帽部分组成的复合结构受到应力而在该改造层之间产生破裂，从而分开该复合结构的各个部分。该激光并不是用来在晶片本身中切割或生成改造层。
发明内容
按照这里描述的多个方面，提供一种切割半导体晶片的方法，包括：在该晶片的背面主表面中切割基准槽；在该背面主表面中切割背槽，该背槽相对该基准槽定位；确定所需的第一芯片边缘相对该基准槽的位置；以及在第一路径中施加辐射能量，从而沿该第一路径在该晶片中形成第一系列改造区域。该晶片的晶体结构在该第一系列改造区域中被改变，并且将该激光的第一边相对该第一芯片边缘的所需位置对齐以及与该背槽对齐。该方法将该晶片沿该第一系列改造区域分成在该第一系列改造区域的任一侧上的该晶片的分割区域。
按照这里描述的多个方面，提供一种切割半导体晶片的方法，包括：在该晶片的背面主表面中切割基准槽；在该背面主表面中切割背槽，该背槽相对该基准槽定位；确定所需的第一芯片边缘相对该基准槽的位置；以及在第一路径中施加辐射能量，从而沿该第一路径在该晶片中形成第一系列改造区域。该晶片的晶体结构在该第一系列改造区域中被改变，并且该激光的第一边相对该第一芯片边缘的所需位置对齐以及与该背槽对齐。该方法包括确定所需的第二芯片边缘相对该基准槽的位置；以及在第二路径中施加辐射能量，从而沿该第二路径在该晶片中形成第二系列改造区域。该晶片的晶体结构在该第二系列改造区域中被改变，并且该激光的第二边相对该第二芯片边缘的所需位置对齐以及与该背槽对齐。该方法包括将该晶片沿该第一和第二系列改造区域分成在该第一和第二系列改造区域的任一侧上的该晶片的分割区域。
按照这里描述的多个方面，提供一种切割半导体晶片的方法，包括：在该晶片的背面主表面中切割基准槽；在该背面主表面中切割背槽，该背槽相对该基准槽定位；确定所需的芯片边缘相对该基准槽的位置；以及在某个路径中施加辐射能量，从而在该晶片内沿该路径形成一系列改造区域。该晶片的晶体结构在这一系列改造区域中被改变，并且该激光的边缘相对该芯片边缘的所需位置对齐且与该背槽对齐。该方法包括沿这一系列改造区域将该晶片分开成在这一系列改造区域任一侧上的该晶片的分割区域。
按照这里描述的多个方面，提供一种半导体芯片，包括：正面和背面主表面，以及形成在正面和背面主表面之间的端面。该端面包括与该正面和背面主表面相关的基本上平的部分，和多个基本上周期性隔开并同样大小的压痕。每个压痕各自的周界完全被该平的部分包围。
附图说明
图1是待切割成芯片的半导体晶片的通常晶片图；
图2是使用刀片切割和辐射能量的组合从半导体晶片切割的多个芯片的剖视图；
图3是示出使用刀片切割和辐射能量的组合的图2的一部分切割的图形表示；
图4是图3示出的部分的俯视图；
图5是示出使用刀片切割和辐射能量的组合的半导体晶片的一部分的切割的图形表示；
图6是使用刀片切割和辐射能量的组合从晶片切割的芯片的端面视图；以及
图7是现有的切割半导体晶片方法的表示。
具体实施方式
图1是待切割成芯片的半导体，例如硅，晶片100的通常晶片图。晶片100可以是本领域已知的任何半导体晶片。术语“模片”和“芯片”可以认为是可互换的；然而在下面的讨论中，使用术语“芯片”。图1示出通常的半导体晶片布局，具有待从晶片水平和垂直切割的阵列芯片，例如，传感器芯片。值得注意的是，需要在晶片的末端进行高精度、低损伤切割或划线，以便可用于线性多芯片阵列(芯片“对接”设置在该阵列中)，从而保持芯片之间希望的间距。为了保持希望的芯片间间隔，芯片必须在一定的公差内切割。在示例实施方式中，感光器芯片需要在大约+/-3微米(um)的公差内切割。另外，垂直划线(或垂直路)102必须保持在某最小宽度以上。在示例实施方式中，该宽度是80um，但是其他的宽度也可以。晶片代工厂所要求的监测和对齐结构需要小宽度以处理该晶片。
图2是使用刀片切割和辐射能量的组合从半导体晶片100切割的多个芯片104的剖视图。下面应当基准图1和2来考虑。在示例实施方式中，激光用来产生辐射能量。在下面的讨论中，激光和激光束用作辐射能量源的示例；然而，应当理解辐射能量的产生不限于激光。基准槽106在该晶片待切割成芯片的部分之外的晶片部分108中切割，例如，在图1中，该区域由垂直划线102A和线110界定。在示例实施方式中，基准槽106在该晶片背面主表面114中切割。本领域任何公知的方法(例如，利用刀片切割)可用来制作基准点切口。在示例实施方式中，基准槽106在该晶片正面主表面115切割用以作为基准正面切口使用。本领域任何公知的方法(例如，利用刀片切割)可用来制作该基准切口。
背槽(或背部切口)112切割在该晶片的背面114。在示例实施方式中，该背部切口利用刀片制作。如下面进一步所讨论的，辐射能量(例如，激光)用来产生改造区域。改造区域在下文进一步描述。将该晶片沿该改造区域分成晶片的分割区域，并形成芯片104。如下面进一步描述的，该背槽和改造区域相对该基准切口定位或设置，如现有技术中已知的。在示例实施方式中，该背槽和改造区域相对已知的位置设置，例如，基准点位置，如本领域所公知的。
图3是示出图2的部分使用刀片切割和辐射能量的组合切割的图形表示，该部分其由芯片104B和芯片104A的一部分形成。在示例实施方式中，背侧切口利用刀片120的一次通过或两次通过而形成，取决于刀片厚度和需要的背部切口宽度。在示例实施方式中，较大的背部切口宽度有助于与“对接”组件有关的多个公差，例如，接触图像传感器阵列组件。在示例实施方式中，该背部切口可以激光切割。例如，辐射能量(如激光)可能不能有效穿透该晶片的全部厚度；然而，激光对于减小的厚度124是有用的。在示例实施方式中，厚度124是大约200-300um。
图4是图3示出部分的俯视图。下面应当基准图3和4来考虑。为了完成晶片的切割，辐射能量沿一定路径施加，从而沿该路径在晶片内形成改造区域128。在示例实施方式中，沿该路径施加激光束126。在示例实施方式中，沿该路径周期性加载激光束126的脉冲。在示例实施方式中，聚焦的红外线激光用来产生激光束126。辐射能量束的边130相对芯片边缘所需要的位置132对齐，例如，该边与该位置对齐，或者与该位置间隔指定的距离。在示例实施方式中，边130是激光束126的边。在示例实施方式中，位置132相对该基准槽而确定。该辐射能量束也与该背槽对齐。例如，边130和槽112在图3中示出的方向134对齐。将该晶片沿该改造区域分成在该改造区域任一侧上的晶片的分割区域，例如，芯片104B和部分135。该晶片基本上沿所需的位置132分隔。该分隔可利用本领域任何公知的方式来实现，例如，使用切割膜(未示)以生成张应力。在示例实施方式中，该分隔包括破坏或破裂该晶片在该改造区域之间的部分。相对该所需的位置分隔的精度在下文中讨论。
在示例实施方式中，辐射能量沿某个路径施加，从而沿该路径在晶片内形成改造区域136。在示例实施方式中，激光束126沿该路径施加。在示例实施方式中，沿该路径周期性加载激光束126脉冲。辐射能量束的边138相对芯片边缘所需要的位置140对齐，例如，该边与该位置对齐，或者与该位置间隔指定的距离。在示例实施方式中，边138是激光束126的边。在示例实施方式中，位置140相对该基准槽而确定。该辐射能量束也与该背槽对齐。例如，边138和槽112在图3中示出的方向134对齐。将该晶片沿该改造区域分成在该改造区域任一侧上的晶片的分割区域，例如，芯片104A和部分135。该晶片基本上沿所需的位置140分隔。该分隔可利用本领域任何公知的方式来实现，例如，使用切割膜(未示)以生成张应力。在示例实施方式中，该分隔包括破坏或破裂该晶片在该改造区域之间的部分。相对该所需的位置分隔的精度在下文中讨论。
调节该辐射能量的焦点，从而在该晶片内形成改造区域。例如，利用该辐射能量加热与该改造区域对应的晶片部分，然后冷却以形成该改造区域。在示例实施方式中，与该改造区域对应的晶片部分至少部分被该辐射能量熔化。晶片的晶体结构在该改造区域内改变，例如，该晶体结构被弱化。在示例实施方式中，在该改造区域中基本上消除晶体结构，该改造区域中的晶片材料基本上是粒状的，例如，具有砂状结构。在示例实施方式中，该激光的焦点使得该晶片的正面和背面不会被该辐射能量显著加热或改变。所以，如这里使用的，“改造区域”是半导体晶片的任何部分，或半导体晶片表面的任何部分，其经历由于暴露于辐射能量而导致的分子级的物理变化。
基准图2至4，分隔该晶片产生该芯片的端壁142。在示例实施方式中，该晶片包括已知的基准位置，例如基准点位置，并且相对该基准点位置定位位置132和140之一或两者。可替换该晶片和产生该光束的激光之一或两者，以产生区域128和136。
在示例实施方式中，该背槽具有宽度144，以及位置132和140被小于宽度144的宽度146隔开。分隔该晶片至少部分从该晶片的其余部分分隔未受损伤的部分135。在示例实施方式中，该未受损伤的部分包括至少一个在晶片制造中使用的特征(未示)，例如，晶片代工厂所要求的监测和对齐结构以处理该晶片。由于存在上面提到的制造特征，部分135对于芯片104是没有用的，并且有利地，上面的过程使得可以为了制造的目的而存在特征，同时去除对于切割操作没有用的部分。
在示例实施方式中，根据晶片的厚度124确定或调节边130或138分别相对位置132和140的对齐，以解决各自的辐射能量束的传播。例如，对于较小的厚度，该边越靠近该位置对齐，对于较大的厚度则更远离该位置。这个调节解决这样的问题，124的值越大，光束在正交于方向134的方向上传播越远。
在示例实施方式中，区域128和136基本上正交于该晶片的正面，即，束126基本上正交于该正面以形成该改造区域。在示例实施方式中(未示)，区域128和136处于相对正面115的锐角，即，束126基本上处于相对该正面的锐角以形成该改造区域。例如，该切口从位置132和140向外朝向该背槽的边逐渐变小。通过将对接的芯片的部分(例如，直接接触的端壁142的表面148)限制在靠近表面115的部分，这会是有好处的，并且最小化在该对接部分中可能的突出或其他瑕疵，所述突出或其他瑕疵可能影响对接芯片之间的期望公差。在示例实施方式中，在该晶片的正面主表面和通过分隔该晶片形成的表面(例如，表面148)之间形成的角150基本呈直角。
在示例实施方式中，相对位置132或140产生一系列改造区域，即，使用重复工艺来形成芯片边缘。例如，第一改造区域形成在距位置132指定的位置，然后第二改造区域形成在距位置132的另一指定距离，小于该第一指定距离。该第一改造区域破裂以形成粗糙的边而不需要精确，并且留下更粗糙的表面。该第二改造区域基本上沿位置132破裂。
期望以最大可能的精度相对该晶片或各个芯片上已知的位置定位晶片的端面(例如，末端142)。对于使用图7示出的工艺的末端定位可能的公差是大约+/-3微米。有利地是，对于使用图1-4中示出的工艺的末端定位可能的公差是大约+/-1-2微米。该边定位提高的精度使得对接芯片之间有更精确的公差，其使得芯片或芯片阵列的制造具有更高的公差要求，例如，使得感光器芯片和阵列分辨率更高。
图5是示出使用刀片切割和辐射能量的组合的晶片100部分的切割的图形表示。在示例实施方式中，仅使用辐射能量束(例如，激光束126)的单次通过来将晶片100上毗连的芯片的末端分开。基准槽(例如，基准槽106)在该晶片待切割成芯片的部分之外的部分(例如，部分108)中切割。以类似于关于背槽112描述的方式在该晶片背面主表面114中切割背槽200。辐射能量沿某个路径施加，从而沿该路径在晶片内形成改造区域202。在示例实施方式中，激光束126沿该路径施加。在示例实施方式中，沿该路径周期性施加激光束126脉冲。辐射能量束相对芯片边缘所需的位置204对齐。在示例实施方式中，位置204相对该基准槽而确定。在示例实施方式中，该路径使得该辐射能量束的中心位置基本上定在芯片边缘所需的位置204，或至少覆盖该所需位置。该辐射能量束也与该背槽对齐，如前所述。将该晶片沿该改造区域分成在该改造区域任一侧上的晶片的分割区域，例如，芯片206A和206B。图5描述的工艺可适用于对于芯片末端的位置要求较低精度的应用。例如，图5示出的工艺的末端定位的通常公差是大约+/-5微米。
回到图1-4，在示例实施方式中，图1-4描述的工艺在垂直划线102和水平划线152上执行。这使得可将同类型的刀片和辐射能量操作用于垂直和水平划线两者。在示例实施方式中，例如，如图5所述，在例如边清晰度和精度不是那么重要的情况下，只有一个辐射能量操作用于垂直或水平划线。例如，沿芯片长度的通常的边清晰度比该芯片的“对接”端重要性低。然而，在有些应用中，沿垂直划线的单激光切割也可能是足够精确的。
使用至少两个辐射能量操作(例如，产生两组改造区域)以切割晶片100的各个部分，例如，如图1-4所述，至少具有下列优点：
1)根据工艺控制需要可使用任何宽度划线102，同时仍允许该芯片精确地切割到需要的长度而没有阻止精确对接的额外的边材料。即，该工艺解决并去除不希望的边材料；
2)不管该辐射能量束的宽度154，芯片的边(如在角150)可准确地形成于每个相邻芯片的位于硅片任何深度的所需位置；
3)可以为不同的厚度124调节该辐射能量束的对齐，例如相对位置132或140，以便解决该光束的任何“传播”，有些因为相邻芯片的侵蚀而使得不可能利用单辐射能量操作(沿图5中描述的路径的辐射能量束的单次通过)；
4)每个芯片边缘超过两个辐射能量操作可用作“粗”切割然后进行“精”切割。该粗切割去除大部分材料，但不是尽可能精确的边。
图6是使用刀片切割和辐射能量的组合从晶片切割的芯片的端面视图。在示例实施方式中，图6示出的芯片就是图2-4的芯片104或图5中示出的芯片206。芯片104在图6中示出，并且在下面描述。应当理解图6适用于任何使用刀片切割和辐射能量的组合形成的芯片。芯片104包括正面和背面主表面115和114，以及形成在正面和背面主表面之间的端面148。该端面包括与该正面和背面有关的基本上平的部分160和多个压痕162。在示例实施方式中，该压痕周期性隔开并且基本上同样大小。在示例实施方式中，该压痕基本上等距隔开。
该压痕对应改造区域128或136，该平的部分对应该改造区域的晶片部分。在示例实施方式中，改造区域128或136中的晶片材料具有粒状的、砂状结构，并且当分割晶片时，该改造区域暴露并且该改造区域的材料掉出该晶片或容易从该晶片去除，在该端面中留下后面的压痕。在示例实施方式中，每个压痕的周界164被该平的部分完全覆盖。在示例实施方式中(未示)，一个或多个压痕162与该正面和背面的一个或两个有关，即，该压痕向该正面和背面之一或两者靠口。在示例实施方式中，压痕166与垂直边168有关，即，该压痕向该边开口。
在示例实施方式中(未示)，压痕162是一系列在方向170隔开的单个压痕。即，该压痕不会重叠或不在方向134上。在示例实施方式中，这些压痕162在方向170等距隔开。
在示例实施方式中，压痕162是在方向170隔开的多个压痕组172。每个组172包括基本上在方向134上的两个或多个压痕162。尽管在图6中示出每个组有两个压痕，但是应当理解所述组172可包括别的数目的压痕。在示例实施方式中，每个172包括同样数目的压痕。在示例实施方式中，组中的压痕相对该晶片的正面和背面等距隔开，并且在方向134上等距隔开。在示例实施方式中，组172方向170上等距隔开。

Claims (2)

1.一种切割半导体晶片的方法，包括：
在该晶片的背面主表面中切割基准槽；
在该背面主表面中切割背槽，该背槽相对该基准槽定位；
确定所需的第一芯片边缘相对该基准槽的位置；
在第一路径中施加辐射能量，从而沿该第一路径在该晶片中形成第一系列改造区域，其中：
该晶片的晶体结构在该第一系列改造区域中被改变；以及
该辐射能量的第一边：
相对该第一芯片边缘的所需位置对齐；以及，
与该背槽对齐；以及
将该晶片沿该第一系列改造区域分成在该第一系列改造区域的任一侧上的该晶片的分割区域，其中：
确定第一芯片边缘相对该基准槽的所需位置包括将该第一边与该第一芯片边缘的所需位置对齐；
该晶片在该背槽中的正面主表面和背面主表面之间具有厚度，并且确定第一芯片边缘相对该基准槽的所需位置包括按照该厚度对齐该第一边；以及，
将该晶片沿该第一系列改造区域分开包括：
在正面和背面主表面之间的模片上形成端面；以及，
在该模片上的正面主表面与至少一部分该端面之间形成基本上直角。
2.一种切割半导体晶片的方法，包括：
在该晶片的背面主表面中切割基准槽；
在该背面主表面中切割背槽，该背槽相对该基准槽定位；
确定所需的第一芯片边缘相对该基准槽的位置；
在第一路径中施加辐射能量，从而沿该第一路径在该晶片中形成第一系列改造区域，其中：
该晶片的晶体结构在该第一系列改造区域中被改变；以及，
该辐射能量的第一边：
相对该第一芯片边缘的所需位置对齐；以及
与该背槽对齐；
确定所需的第二芯片边缘相对该基准槽的位置；
在第二路径中施加辐射能量，从而沿该第二路径在该晶片中形成第二系列改造区域：
该晶片的晶体结构在该第二系列改造区域中被改变；以及，
该辐射能量的第二边：
相对该第二芯片边缘的所需位置对齐；以及，
与该背槽对齐；以及，
将该晶片沿该第一和第二系列改造区域分成在该第一和第二系列改造区域的任一侧上的该晶片的分割区域，其中该背槽具有第一宽度，以及该第一和第二路径被分开小于该第一宽度的第二宽度。
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Publication number Priority date Publication date Assignee Title
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US9197804B1 (en) * 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
KR20120043933A (ko) * 2010-10-27 2012-05-07 삼성전자주식회사 반도체 장치의 제조방법
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US8828848B2 (en) * 2011-12-16 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Die structure and method of fabrication thereof
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US20140061864A1 (en) * 2012-09-04 2014-03-06 Samsung Electro-Mechanics Co., Ltd. Semiconductor substrate having crack preventing structure and method of manufacturing the same
CN103841506B (zh) * 2012-11-20 2017-09-01 清华大学 热致发声器阵列的制备方法
CN103841507B (zh) 2012-11-20 2017-05-17 清华大学 热致发声装置的制备方法
CN103841504B (zh) * 2012-11-20 2017-12-01 清华大学 热致发声器阵列
US8809166B2 (en) * 2012-12-20 2014-08-19 Nxp B.V. High die strength semiconductor wafer processing method and system
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
WO2017053329A1 (en) 2015-09-21 2017-03-30 Monolithic 3D Inc 3d semiconductor device and structure
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US10720360B2 (en) 2016-07-29 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die singulation and structures formed thereby
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US10943895B2 (en) 2019-01-14 2021-03-09 Xerox Corporation Method of fabricating a plurality of linear arrays with submicron y-axis alignment
US11025796B2 (en) 2019-01-14 2021-06-01 Xerox Corporation Plurality of linear sensor arrays comprising plural process direction widths and photosites with submicron y-axis alignment between arrays
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128282A (en) * 1991-11-04 1992-07-07 Xerox Corporation Process for separating image sensor dies and the like from a wafer that minimizes silicon waste
US5580831A (en) * 1993-07-28 1996-12-03 Fujitsu Limited Sawcut method of forming alignment marks on two faces of a substrate
CN101017791A (zh) * 2006-02-08 2007-08-15 株式会社瑞萨科技 制造半导体器件的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860075A (en) 1985-12-13 1989-08-22 Xerox Corporation Replaceable image sensor array
US4814296A (en) * 1987-08-28 1989-03-21 Xerox Corporation Method of fabricating image sensor dies for use in assembling arrays
US5153421A (en) 1991-11-04 1992-10-06 Xerox Corporation Architecture for analog and digital image sensor arrays
US6165813A (en) 1995-04-03 2000-12-26 Xerox Corporation Replacing semiconductor chips in a full-width chip array
JP2006086509A (ja) * 2004-08-17 2006-03-30 Denso Corp 半導体基板の分断方法
JP2007134454A (ja) * 2005-11-09 2007-05-31 Toshiba Corp 半導体装置の製造方法
JP2007235008A (ja) * 2006-03-03 2007-09-13 Denso Corp ウェハの分断方法およびチップ
JP2008147412A (ja) * 2006-12-11 2008-06-26 Matsushita Electric Ind Co Ltd 半導体ウェハ，半導体装置及び半導体ウェハの製造方法ならびに半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128282A (en) * 1991-11-04 1992-07-07 Xerox Corporation Process for separating image sensor dies and the like from a wafer that minimizes silicon waste
US5580831A (en) * 1993-07-28 1996-12-03 Fujitsu Limited Sawcut method of forming alignment marks on two faces of a substrate
CN101017791A (zh) * 2006-02-08 2007-08-15 株式会社瑞萨科技 制造半导体器件的方法

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