CN102117831A - 晶体管及其制造方法 - Google Patents
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Abstract
本发明为一种晶体管,其包括具有沟道区的基底;位于该基底沟道区两端的源区和漏区;界于所述源区和漏区之间的该沟道区上方基底顶层的栅极高K介质层;位于该栅极高K介质层下面的界面层,该界面层第一部分靠近源极,第二部分靠近漏极,且第一部分的等效氧化层厚度大于第二层。非对称替代的金属栅形成非对称界面层,在漏极侧较薄而在源极侧较厚。在较薄的漏极侧,短沟道效应比较重要,非对称的界面层有利于控制短沟道效应;在较厚的源极侧,载流子迁移率对器件影响较大,非对称的界面层可以避免载流子迁移速率下降。此外,非对称替代的金属栅也可以形成非对称的金属功函数。
Description
技术领域
本发明主要涉及关于一种晶体管,特别是一种具有非对称结构栅极的晶体管及其制造方法。
背景技术
限制金属氧化物半导体(MOS)晶体管尺寸进一步缩小的主要问题是短沟道效应(SCE),且该现象主要发生在沟道长度小于0.1微米时。器件失效包括但不仅限于DIBL(漏极感应载流子势垒降低,即低的源漏极击穿电压)、亚阈值泄露、和阈值不稳定等。这些问题统称为短沟道效应,主要与界面层的等效氧化层厚度(EOT)有关,而薄的EOT有利于控制短沟道效应(特别是在漏端),如引文High-Performance High-K/Metal Gatesfor 45nm CMOS and Beyond with Gate-First Processing(M.Chudziket al.VLSI 2007,IBM et al.)所述。如图1所示,当栅极氧化层厚度Tinv(等效氧化层厚度,EOT)的电学厚度减小时,DIBL随之减小。
此外,根据引文Extremely Scaled Gate-First High-K Metal GateStack with EOT of 0.55nm Using Novel Interfacial Layer ScavengingTechniques for 22nm Technology Node and Beyond(K.Choi et al.VLSI2009,IBM)所述,当等效氧化层厚度(EOT)继续减小时,电子迁移率(在Eeff=1MV/cm处)会继续降低,如图2所示。同时,当等效氧化层厚度(EOT)继续减小时,空穴迁移率(在Eeff=1MV/cm处)也会继续降低,如图3所示。这说明界面层会引起的载流子迁移率的下降。
综上所述,需要一种晶体管及其制造技术,在降低等效氧化层厚度(EOT)来抑制短沟道效应的同时控制载流子迁移率的下降。
发明内容
在本发明的具体实施方式中,晶体管包括:具有沟道区的基底;位于该基底沟道区两端的源区和漏区;界于所述源区和漏区之间的该沟道区上方基底顶层的栅极高K介质层;位于该栅极高K介质层下面的界面层,该界面层包括两部分,第一部分靠近源极,第二部分靠近漏极,且第一部分的等效氧化层厚度大于第二层。
根据该晶体管的具体实施方式,所述界面层第一部分的厚度大于0.5nm,而所述界面层第二部分的厚度小于0.5nm。
根据该晶体管的具体实施方式,所述界面层第一部分占据的长度小于界面层总长度的2/3,而所述第二部分占据了总长度剩余的部分。
根据该晶体管的具体实施方式,该晶体管还包括:位于所述栅极高K介质层顶层的氧吸收层;围绕该氧吸收层的掩蔽层。
根据该晶体管的具体实施方式,所述氧吸收层包括:位于所述漏极侧且与所述栅极高K介质层接触的第一氧吸收层;位于所述源极侧且与所述栅极高K介质层接触的第二氧吸收层;所述第一氧吸收层的氧吸收能力高于第二氧吸收层的氧吸收能力。
根据该晶体管的具体实施方式,所述第一氧吸收层为Ti,Hf,Ta,W和/或其氮化物。
根据该晶体管的具体实施方式,所述栅极高K介质层的介质常数大于4。
根据该晶体管的具体实施方式,所述栅极高K介质层为HfO2,ZrO2或者Al2O3。
根据该晶体管的具体实施方式,在所述栅极高K介质层上方还形成一层金属膜。
根据该晶体管的具体实施方式,此处所说的金属薄膜为Ti,Ta,Al或其氮化物。
非对称替代的金属栅形成非对称界面层,在漏极侧较薄而在源极侧较厚。在较薄的漏极侧,短沟道效应比较重要,非对称的界面层有利于控制短沟道效应;在较厚的源极侧,载流子迁移率对器件影响较大,非对称的界面层可以避免载流子迁移速率下降。
此外,非对称替代的金属栅也可以形成非对称的金属功函数。
本发明还提供一种晶体管的制造方法,包括:在硅片上制备源极,漏极,栅极高K介质层,多晶硅栅和覆盖多晶硅栅的掩蔽层;在所述掩蔽层、源极和漏极上淀积一层层间介质;进行平坦化处理去除所述层间介质的顶部直到露出所述掩蔽层的顶部;刻蚀去除所述掩蔽层的顶部直到露出所述多晶硅栅的顶部;刻蚀去除所述栅极高K介质层上面的多晶硅栅极形成一个空腔;在所述空腔内形成第一氧吸收层;在所述空腔剩余部分形成第二氧吸收层;此处所述的第一氧吸收层吸收氧的能力强于第二氧吸收层。
在此方法的其他备选方案中,刻蚀去除所述多晶硅栅后,还需要在所述高K层上形成一层金属薄膜。
在此方法的其他备选方案中,所述金属薄膜为Ti,Ta,Al和/或它们的氮化物。
在此方法的其他备选方案中,所述栅极高K介质层包括介电常数大于4的高K介质材料。
在此方法的其他备选方案中,所述掩蔽层为硅氧化物,硅氮化物或者两者的混合物。
在此方法的其他备选方案中,所述层间介质为二氧化硅。
在此方法的其他备选方案中,所述掩蔽层采用化学机械研磨或者反应离子刻蚀方法移除。
在此方法的其他备选方案中,第一种氧吸收材料是倾斜淀积在所述层间介质层,掩蔽层,所述空腔内漏极一侧的栅极高K介质层上的,一次形成所述第一氧吸收层。
在此方法的其他备选方案中,所述第一氧吸收层为Ti,Hf,Ta,W和/或其氮化物。
在此方法的其他备选方案中,第二种氧吸收材料淀积在所述空腔内剩余的部分,并用化学机械研磨法在空腔源极侧的栅极高K介质层上形成所述第二氧吸收层。其中,第二种氧吸收材料可以与第一种氧吸收材料相同。
本发明的上述技术方案与下面的描述和附图相结合能够得到更好的体会和理解。然而应该注意到,下面的描述是针对本发明的较佳实施方式和众多相关细节的,并通过举例方式来说明本发明的实现方式。在没有背离本发明精神的前提下,可以在本发明范围内做出其它改变和修改,这些改变和修改都是包含在本发明中的。
附图说明
图1显示在不同Tinv点处DIBL和Lgate的对比;
图2显示电子迁移率(在Eeff=1MV/cm处)相对EOT的变化趋势;
图3显示空穴迁移率(在Eeff=1MV/cm处)相对EOT的变化趋势;
图4为根据本发明具体实施方式的晶体管横截结构面示意图;
图5为根据本发明具体实施方式的制造晶体管方法步骤一的横截面结构示意图;
图6为根据本发明具体实施方式的制造晶体管方法步骤二的横截面结构示意图;
图7为根据本发明具体实施方式的制造晶体管方法步骤三的横截面结构示意图;
图8为根据本发明具体实施方式的制造晶体管方法步骤四的横截面结构示意图;
图9为根据本发明具体实施方式的制造晶体管方法步骤五的横截面结构示意图;
图10为根据本发明具体实施方式的制造晶体管方法步骤六的横截面结构示意图;
图11为根据本发明具体实施方式的制造晶体管方法步骤六的横截面结构示意图;
图12为根据本发明具体实施方式的制造晶体管方法步骤七的横截面结构示意图。
具体实施方式
以下将参照具体实施方式及其附图详细说明本发明的各种特征和优点。同时,请注意附图中的各项特征并非按比例绘出。将公知部件和处理技术的描述省略从而使本发明更为明晰。此处所述具体实施方式仅用于更好的理解本发明并帮助本领域技术人员实施本发明。因此,具体实施方式不应限制本发明的范围。
如上所述,本发明涉及到一种晶体管,更确切的说是一种带有非对称替代栅的晶体管,其相关特性将在这里具体描述。请注意,相似或相应的部分将用相同的标号注明。
根据图4,根据本发明的一个示例性的晶体管结构包括:拥有沟道区的基底100;源区101;漏区102;采用常见工艺在基底100顶面形成的栅极高K介质层103,其介电常数大于4;位于栅极高K介质层103顶面的氧吸收层,包括位于漏极一侧的接触栅极高K介质层103的第一氧吸收层104和位于源极一侧的接触栅极高K介质层103的第二氧吸收层105;包围氧吸收层的掩蔽层109。
第一氧吸收层104和第二氧吸收层105可以吸收氧,因而能够通过吸收氧来降低下面界面层的等效氧化层厚度(EOT)。第一氧吸收层104吸氧能力强于第二氧吸收层105,因而形成的界面层包括具有不同等效氧化层厚度(EOT)的106部分和107部分。界面层107部分厚度大于106部分,因而界面层106部分有利于控制漏极一侧的短沟道效应,界面层107部分有利于避免源极一侧的载流子迁移率降低。同时,非对称栅极可以利用不同的材料实现不同的有效功函数。
关于界面层的厚度,界面层106部分厚度小于0.5nm且优选厚度小于0.3nm;界面层107部分厚度大于0.5nm。关于界面层的长度,界面层106部分位于界面层接近漏极的一侧并占据界面层不小于其总长度的1/3;107部分占据剩下的界面层。
所述层的例子可以包括但不限于以下材料:栅极高K介质层103可为HfO2、ZrO2、Al2O3等;第一氧吸收层104可为纯金属Ti、Hf、Ta、W和/或其氮化物等(请参考美国专利申请文件2009/0152651)。
可选的,在形成吸氧层前,在栅极高K介质层103上形成金属膜103’,它可以用来调节晶体管的阈值电压VT。金属膜103’可为纯金属Ti、Ta、Al和/或其氮化物,例如AlN、TaAlN等。
如上所述,本发明同时涉及晶体管的制造方法,特别涉及非对阵替代栅的晶体管的制造方法。
该晶体管制造方法可以公知工艺进行。代表本发明具体实施方式的组成部分如图5到图11中的示意图所示。
根据本发明的晶体管结构的示例制造方法可以包括以下步骤:
步骤一,在硅片上生成源极、漏极、栅极高K介质层、多晶硅栅极以及覆盖在多晶硅栅极上的掩蔽层:参见图5,一个半导体器件具有基底100、源极101、漏极102、栅极高K介质层103、多晶硅栅极108、以及掩蔽层109。使用业界公知的方法将栅极介质层103形成于基底的上表面;该栅极高K介质层103包括具有高于4的介质常数的高K介质材料。通过如多晶硅的化学气相沉积法,将多晶硅栅极108形成于该栅极高K介质层103上。经过适当的沉积和方向性刻蚀,在多晶硅栅极108周围形成掩蔽层109。该掩蔽层109包括例如硅氧化物、硅氮化物或所述两者的混合物的介质材料。通过离子掺杂注入形成源极101和漏极102。
步骤二,沉积间隔层介质:参见图6,通过如化学气相沉积法,间隔层介质(ILD)110形成于源极101、漏极102和掩蔽层109上。该间隔层介质110可以为硅氧化物,如SiO2、掺杂硼磷的硅玻璃(BPSG)、硼硅酸盐玻璃(BSG)、磷硅酸玻璃(PSG)、以及未掺杂的硅玻璃(USG)。
步骤三,处理间隔层介质:参见图7,通过化学机械研磨(CMP),部分移除该间隔层介质(ILD)110,直至掩蔽层109显现。
步骤四,移除掩蔽层:参见图8,通过化学机械研磨(CMP)或反应离子刻蚀(RIE),部分移除掩蔽层109的上部,直至多晶硅栅极108显现。
步骤五,刻蚀去除多晶硅栅极108:参见图9,将多晶硅栅极108去除并在栅极高K介质层103上形成一个空腔。
步骤五’,可选的,在栅极高K介质层103上形成金属膜103’,用来调节晶体管的阈值电压。金属膜103’可为纯金属Ti、Ta、Al和/或其氮化物,例如,AlN、TaAlN等。
步骤六,形成第一氧吸收层:参见图10,通过在间隔层介质(ILD)110和掩蔽层109上进行倾斜沉积,在栅极高K介质层103的漏极侧的空腔中覆盖第一氧吸收材料111,该第一氧吸收材料可为纯金属Ti、Hf、Ta、W和/或其氮化物等(美国专利文件2009/0152651),所述材料将吸收氧气并可通过吸收氧气将下方的界面层减薄;同时参见图11,通过各向异性蚀刻,在栅极高K介质层103的漏极侧的空腔中形成第一氧吸收层104。
步骤七,形成第二氧吸收层:参见图12,在所述空腔的其他部分覆盖第二氧吸收材料,然后通过化学机械研磨(CMP)在栅极高K介质层103的漏极侧的空腔中形成第二氧吸收层105。其中,该第二种氧吸收材料可以与第一种氧吸收材料相同。
第一氧吸收层104和第二氧吸收层105将吸收氧气从而通过吸收氧气来降低下方界面层的等效氧厚度(EOT),第一氧吸收层104具有较第二氧吸收层105更强的氧吸收能力,从而形成界面层,而该界面层包括具有不同等效氧厚度的106部分和107部分,其中界面层107部分厚于106部分,所以,界面层106部分有益于漏极侧的短沟道控制,而界面层107部分避免源极侧的载流子迁移率降低。
此外,非对称栅极还可利用不同材料产生不同的有效功函数。
根据优选具体实施方式,本发明得到详细的解释,而本领域技术人员开在不脱离本发明精神和范围的前提下可以在形式和细节上对本发明进行改变。因此,本发明的保护范围以权利要求为准。
Claims (11)
1.一种晶体管,包括:
基底,所述基底具有沟道区;
源区和漏区,其位于该基底沟道区的两端;
栅极高K介质层,其界于所述源区和漏区之间,并位于该沟道区上方处的基底顶层;
界面层,其位于该栅极高K介质层的下方,
其中,该界面层包括两部分,第一部分靠近源极,第二部分靠近漏极,且所述第一部分的等效氧化层厚度大于所述第二部分的等效氧化层厚度。
2.如权利要求1所述的晶体管,其特征在于,所述界面层第一部分的厚度大于0.5nm,而所述界面层第二部分的厚度小于0.5nm。
3.如权利要求1所述的晶体管,其特征在于,所述界面层第一部分占据的长度小于界面层总长度的2/3,而所述第二部分占据了总长度剩余的部分。
4.如权利要求1所述的晶体管,其特征在于,该晶体管还包括:
氧吸收层,其位于所述栅极高K介质层的顶部。
5.如权利要求4所述的晶体管,其特征在于,所述氧吸收层包括:
第一氧吸收层,其位于所述漏极一侧;
第二氧吸收层,其位于所述源极一侧;
其中,所述第一氧吸收层的氧吸收能力高于第二氧吸收层的氧吸收能力。
6.如权利要求5所述的晶体管,其特征在于,所述第一氧吸收层为Ti,Hf,Ta,W和/或其氮化物。
7.如权利要求4所述的晶体管,其特征在于,在所述栅极高K介质层和所述氧吸收层之间还有金属层。
8.一种晶体管的制造方法,其特征在于,包括以下步骤:
在硅片上制备源极,漏极,栅极高K介质层,多晶硅栅极和覆盖多晶硅栅的掩蔽层;
在所述掩蔽层、源极和漏极上淀积层间介质;
进行平坦化处理去除所述层间介质的顶部直到露出所述掩蔽层的顶部;
刻蚀去除所述掩蔽层的顶部直到露出所述多晶硅栅极的顶部;
刻蚀去除所述栅极高K介质层上面的多晶硅栅极,以形成一个空腔;
采用第一种氧吸收材料在所述空腔内形成第一氧吸收层;
采用第二种氧吸收材料在所述空腔剩余部分形成第二氧吸收层;
所述的第一氧吸收层吸收氧的能力强于第二氧吸收层。
9.如权利要求8所述的晶体管的制造方法,其特征在于,将第一种氧吸收材料倾斜淀积,一次形成所述第一氧吸收层。
10.如权利要求8所述的晶体管的制造方法,其特征在于,所述第一氧吸收层为Ti,Hf,Ta,W和/或它们的氮化物。
11.如权利要求9所述的晶体管的制造方法,其特征在于,将第二种氧吸收材料淀积在所述空腔内剩余的部分,并用化学机械研磨法在空腔内源极侧的栅极高K介质层上形成所述第二氧吸收层。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102969237A (zh) * | 2011-08-31 | 2013-03-13 | 中芯国际集成电路制造(上海)有限公司 | 形成栅极的方法、平坦化层间介质层的方法 |
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Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8716095B2 (en) * | 2010-06-03 | 2014-05-06 | Institute of Microelectronics, Chinese Academy of Sciences | Manufacturing method of gate stack and semiconductor device |
US8658518B1 (en) | 2012-08-17 | 2014-02-25 | International Business Machines Corporation | Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices |
US8673731B2 (en) | 2012-08-20 | 2014-03-18 | International Business Machines Corporation | Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices |
US8669167B1 (en) | 2012-08-28 | 2014-03-11 | International Business Machines Corporation | Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices |
US9177820B2 (en) * | 2012-10-24 | 2015-11-03 | Globalfoundries U.S. 2 Llc | Sub-lithographic semiconductor structures with non-constant pitch |
US9412667B2 (en) | 2014-11-25 | 2016-08-09 | International Business Machines Corporation | Asymmetric high-k dielectric for reducing gate induced drain leakage |
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Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10214964A (ja) * | 1997-01-30 | 1998-08-11 | Oki Electric Ind Co Ltd | Mosfet及びその製造方法 |
DE19704026B4 (de) * | 1997-02-04 | 2007-12-27 | Deutsche Telekom Ag | Türfreisprechanlage |
US6225669B1 (en) * | 1998-09-30 | 2001-05-01 | Advanced Micro Devices, Inc. | Non-uniform gate/dielectric field effect transistor |
US6312995B1 (en) * | 1999-03-08 | 2001-11-06 | Advanced Micro Devices, Inc. | MOS transistor with assisted-gates and ultra-shallow “Psuedo” source and drain extensions for ultra-large-scale integration |
JP2002299609A (ja) * | 2001-03-29 | 2002-10-11 | Nec Corp | 半導体装置及びその製造方法 |
US6465307B1 (en) * | 2001-11-30 | 2002-10-15 | Texas Instruments Incorporated | Method for manufacturing an asymmetric I/O transistor |
US6791106B2 (en) * | 2001-12-26 | 2004-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US6630720B1 (en) * | 2001-12-26 | 2003-10-07 | Advanced Micro Devices, Inc. | Asymmetric semiconductor device having dual work function gate and method of fabrication |
CN1269222C (zh) * | 2003-02-20 | 2006-08-09 | 北京大学 | 一种非对称栅场效应晶体管 |
US7285829B2 (en) * | 2004-03-31 | 2007-10-23 | Intel Corporation | Semiconductor device having a laterally modulated gate workfunction and method of fabrication |
US7422936B2 (en) * | 2004-08-25 | 2008-09-09 | Intel Corporation | Facilitating removal of sacrificial layers via implantation to form replacement metal gates |
US8110465B2 (en) * | 2007-07-30 | 2012-02-07 | International Business Machines Corporation | Field effect transistor having an asymmetric gate electrode |
US20090152651A1 (en) * | 2007-12-18 | 2009-06-18 | International Business Machines Corporation | Gate stack structure with oxygen gettering layer |
US7977181B2 (en) * | 2008-10-06 | 2011-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for gate height control in a gate last process |
US20100127331A1 (en) * | 2008-11-26 | 2010-05-27 | Albert Ratnakumar | Asymmetric metal-oxide-semiconductor transistors |
US20110147837A1 (en) * | 2009-12-23 | 2011-06-23 | Hafez Walid M | Dual work function gate structures |
US8551874B2 (en) * | 2010-05-08 | 2013-10-08 | International Business Machines Corporation | MOSFET gate and source/drain contact metallization |
-
2009
- 2009-12-31 CN CN200910249095XA patent/CN102117831B/zh active Active
-
2010
- 2010-06-28 WO PCT/CN2010/074607 patent/WO2011079605A1/zh active Application Filing
- 2010-06-28 US US12/937,502 patent/US20110298018A1/en not_active Abandoned
- 2010-06-28 GB GB1121913.6A patent/GB2489067B/en active Active
- 2010-06-28 CN CN2010900007970U patent/CN202585424U/zh not_active Expired - Fee Related
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