CN111640673A - 一种双栅薄膜晶体管及其制作方法 - Google Patents
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Abstract
本发明涉及薄膜晶体管技术领域,尤其涉及一种双栅薄膜晶体管及其制作方法,该双栅薄膜晶体管,包括:衬底、位于所述衬底上的有源层、位于所述有源层上的介质层、位于所述介质层两侧的源电极和漏电极;还包括:并排位于所述介质层上的第一栅电极和第二栅电极,且所述第一栅电极的功函数和所述第二栅电极的功函数间存在功函数差,由于第一栅电极的材料和第二栅电极的材料不同,即存在功函数差,因此,在沟道中形成加速电场,进而有利于增加载流子的迁移率,降低亚阈值摆幅,改善器件的偏置稳定性并减少器件的关态电流,能够在亚阈值区域表现较佳效果。
Description
技术领域
本发明涉及薄膜晶体管技术领域,尤其涉及一种双栅薄膜晶体管及其制作方法。
背景技术
薄膜晶体管被广泛的应用于屏幕显示中,包括非晶硅薄膜晶体管、多晶硅薄膜晶体管,金属氧化物薄膜晶体管等。
现有的薄膜晶体管采用在顶栅型和底栅型的双栅结构来对器件进行优化,以保证屏幕显示的质量。具体地,顶栅型和底栅型的双栅结构为上下结构,这种上下结构的双栅晶体管在亚阈值区域性能并不佳。
发明内容
鉴于上述问题,提出了本发明以便提供一种克服上述问题或者至少部分地解决上述问题的
一方面,本发明提供了一种双栅薄膜晶体管的制作方法,包括:
在衬底上形成有源层;
在所述有源层上的两端分别形成源电极和漏电极;
在所述源电极和所述漏电极之间形成介质层;
在所述介质层上并排形成第一栅电极和第二栅电极,且所述第一栅电极的功函数与所述第二栅电极的功函数间存在功函数差。
进一步地,所述第一栅电极和所述第二栅电极分别对应如下任意两种材料:
钼、铜、金、钛、钨和镍。
另一方面,本发明还提供了一种双栅薄膜晶体管,包括:
衬底、位于所述衬底上的有源层、位于所述有源层上的介质层、位于所述介质层两侧的源电极和漏电极;
还包括:并排位于所述介质层上的第一栅电极和第二栅电极,且所述第一栅电极的功函数和所述第二栅电极的功函数间存在功函数差。
进一步地,所述第一栅电极和所述第二栅电极分别对应如下任意两种材料:
钼、铜、金、钛、钨和镍。
进一步地,所述介质层的厚度均大于所述源电极的厚度和所述漏电极的厚度,并覆盖所述源电极顶部的部分区域和所述漏电极顶部的部分区域。
进一步地,所述衬底具体为如下任意一种:
硅衬底、玻璃衬底。
进一步地,所述有源层具体为如下任意一种:
非晶硅层、多晶硅层和金属氧化物层。
进一步地,所述源电极所述漏电极为如下任意一种:
钼、铜和金。
进一步地,所述介质层具体为如下任意一种:
二氧化硅层、三氧化铝层、氮化硅层和二氧化氟层。
进一步地,所述介质层的厚度为100nm~10μm。
本发明实施例中的一个或多个技术方案,至少具有如下技术效果或优点:
本发明提供的一种双栅薄膜晶体管,包括:衬底,位于衬底上的有源层,位于有源层上的介质层,位于该介质层两侧的源电极和漏电极;还包括:并排位于介质层上的第一栅电极和第二栅电极,且第一栅电极的功函数和第二栅电极的功函数间存在功函数差,由于第一栅电极的材料和第二栅电极的材料不同,即存在功函数差,因此,在沟道中形成加速电场,进而有利于增加载流子的迁移率,降低亚阈值摆幅,改善器件的偏置稳定性并减少器件的关态电流,能够在亚阈值区域表现较佳效果。
附图说明
通过阅读下文优选实施方式的详细描述,各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的,而并不认为是对本发明的限制。而且在整个附图中,用相同的参考图形表示相同的部件。在附图中:
图1示出了本发明实施例一中双栅薄膜晶体管的结构示意图;
图2示出了本发明实施例一中一种优选的双栅薄膜晶体管的结构示意图;
图3示出了本发明实施例二中双栅薄膜晶体管的制作方法的流程示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反,提供这些实施例是为了能够更透彻地理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的,其中为了清楚表达的目的,放大了某些细节,并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的,实际中可能由于制造公差或技术限制而有所偏差,并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中,当将一层/元件称作位于另一层/元件“上”时,该层/元件可以直接位于该另一层/元件上,或者它们之间可以存在居中层/元件。另外,如果在一种朝向中一层/元件位于另一层/元件“上”,那么当调转朝向时,该层/元件可以位于该另一层/元件“下”。
本发明实施例提供了一种双栅薄膜晶体管,如图1所示,包括:衬底101、位于衬底101上的有源层102、位于有源层102上的介质层103、位于介质层103两侧的源电极S和漏电极D。
该双栅薄膜晶体管还包括:并排位于介质层103上的第一栅电极104和第二栅电极105,且该第一栅电极104的功函数和第二栅电极105的功函数间存在功函数差。
由于第一栅电极104采用的电极材料与该第二栅电极105的电极材料不同,比如,第一栅电极104采用金(Au),而第二栅电极105采用钼(Mo),因此,第一栅电极104的功函数和第二栅电极105的功函数之间存在功函数差。
当然,在具体的实施方式中,该第一栅电极104和第二栅电极105分别对应如下任意两种材料,即这两种栅电极选取的材料不同:
钼(Mo)、铜(Cu)、金(Au)、钛(Ti)、钨(W)和镍(Ni)。
由于第一栅电极104的功函数与第二栅电极105的功函数间存在功函数差,因此,第一栅电极104下的沟道表面电势和第二栅电极105下的沟道表面电势之间的电势差为如下:
其中,该ψ1、ψ2分别表示第一栅电极下的沟道表面电势和第二栅电极下的沟道表面电势,t0表示有源层的厚度,δ表示与器件材料有关的参数,KB表示玻尔兹曼常数,T表示绝对温度,q表示电荷常量,Bn1、Bn2表示由边界条件求出得到的数值解参数,数值解方程为:
在Bni的解附近,VGi∝Bni。随着第一栅电极104与第二栅电极105之间的功函数差的增加,导致第一栅电极104与第二栅电极105的沟道表面电势差的增加。在器件开启时,通过该沟道中的加速电场,使得电流快速增加,提高了器件的亚阈值摆幅。
另外,还可以通过降低器件的漏电极电场,减弱漏致势垒效应的影响,增加器件的偏置稳定性。沿着沟道方向,该第二栅电极下的电场可以为:
其中,x表示沟道的位置,其取值为0~L1+L2,L1和L2分别对应第一栅电极的长度和第二栅电极的长度,在x=L1+l2时:
其中,n20,n2L2分别表示拟合参数,λ表示特征长度,通过函数的边界调节求解数值得到,VBI表示漏电极与源电极的势垒电压,VDS为漏电极的电压,VG′2=VGS-Vfb2表示栅电极电压减去第二栅电极的平带电压后的电压值,VSUB为衬底电压,d为耗尽区宽度,ε为有源区的介电常数,NA为有源层的电荷密度。
根据上述公式,可以得到,随着第二栅电极的功函数减小,漏电极的电场也会随之减小。
因此,在选取第二栅电极的材料时,可以根据上述的吻戏,选择功函数较小的材料结构,进而可以提高器件性能。
该第一栅金属104和第二栅金属105可以相接触,当然,也可以不相接触。优选地,该第一栅金属104与第二栅金属105之间相接触,即第一栅金属104和第二栅金属105之间的距离为0,当然,若对准工艺中使得第一栅电极104与第二栅电极105之间留有间隙,对该器件的影响也并不是很大,且该第一栅电极104和第二栅电极105接触的位置位于源电极S和漏电极D的正中间。
在一种可选的实施方式中,如图2所示,该介质层103的厚度均大于源电极S的厚度和漏电极D的厚度,且该介质层103覆盖该源电极S顶部的部分区域和漏电极D顶部的部分区域。
在一种可选的实施方式中,该介质层103的厚度还可以与源电极S的厚度和漏电极D的厚度均相等。
上述两种方式中,两种栅电极与源电极S和漏电极D不接触即可。
在一种可选的实施方式中,衬底101具体为如下任意一种:
硅衬底、玻璃衬底。在本发明中,优选玻璃衬底。其厚度为300μm~500μm。
在一种可选的实施方式中,该有源层具体为如下任意一种:
非晶硅层、多晶硅层和金属氧化物层。其中,该金属氧化物可以选择氧化镓(Ga2O3),氧化锌(ZnO),氧化铟(In2O3)按照1:1:1的比例的混合物作为有源层102的材料。
在一种可选的实施方式中,该有源层102的图形通过湿法刻蚀的方式得到。有源层102的厚度不能太厚,也不能太薄,太厚会导致生长时间太长,成本增加,太薄会导致器件性能损失,该有源层102的厚度为100nm~10μm,优选的,为100nm。
在一种可选的实施方式中,该源电极S和漏电极D为如下任意一种:
钼(Mo)、铜(Cu)和金(Au)。
优选地,源电极采用钼,漏电极采用金。
该漏电极的厚度和源电极的厚度均为100nm,且源电极和漏电极的图形都可以采用湿法刻蚀的方式得到。
在一种可选的实施方式中,该介质层具体为如下任意一种:
二氧化硅层、三氧化铝层、氮化硅层和二氧化氟层。优选的,在本发明实施例中采用二氧化硅层。
由于该介质层103的厚度太厚会导致栅控能力减弱,太薄会导致泄漏电流增加,因此,器件容易被击穿,因此,该介质层103的厚度为100nm~10μm,优选的为150nm。
由于该介质层103的厚度均大于源电极S的厚度和漏电极D的厚度,因此,会覆盖该源电极S顶部的部分区域和漏电极D顶部的部分区域。使得该介质层103在源电极S以及漏电极D的上表面形成一定的拓展,可以有效避免栅电极与两侧的源电极S和漏电极接触的发生,实现有效隔离。
本发明实施例中的一个或多个技术方案,至少具有如下技术效果或优点:
本发明提供的一种双栅薄膜晶体管,包括:衬底,位于衬底上的有源层,位于有源层上的介质层,位于该介质层两侧的源电极和漏电极;还包括:并排位于介质层上的第一栅电极和第二栅电极,且第一栅电极的功函数和第二栅电极的功函数间存在功函数差,由于第一栅电极的材料和第二栅电极的材料不同,即存在功函数差,因此,在沟道中形成加速电场,进而有利于增加载流子的迁移率,降低亚阈值摆幅,改善器件的偏置稳定性并减少器件的关态电流。
实施例二
基于相同的发明构思,本发明还提供了一种双栅薄膜晶体管的制作方法,如图3所示,包括:
S301,在衬底上形成有源层;
S302,在所述有源层上的两端分别形成源电极和漏电极;
S303,在所述源电极和所述漏电极之间形成介质层;
S304,在所述介质层上并排形成第一栅电极和第二栅电极,且所述第一栅电极的功函数与所述第二栅电极的功函数间存在功函数差。
进一步地,所述第一栅电极和所述第二栅电极分别对应如下任意两种材料:
钼、铜、金、钛、钨和镍。
上述的制作方法中,对步骤的先后顺序并不作限定。
进一步地,所述衬底具体为如下任意一种:
硅衬底、玻璃衬底。
进一步地,所述有源层具体为如下任意一种:
非晶硅层、多晶硅层和金属氧化物层。
进一步地,所述有源层的厚度为100nm~10μm。
进一步地,,所述源电极所述漏电极为如下任意一种:
钼、铜和金。
进一步地,所述介质层具体为如下任意一种:
二氧化硅层、三氧化铝层、氮化硅层和二氧化氟层。
进一步地,所述介质层的厚度为100nm~10μm。
在以上的描述中,对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解,可以通过各种技术手段,来形成所需形状的层、区域等。另外,为了形成同一结构,本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外,尽管在以上分别描述了各实施例,但是这并不意味着各个实施例中的措施不能有利地结合使用。
尽管已描述了本发明的优选实施例,但本领域内的技术人员一旦得知了基本创造性概念,则可对这些实施例作出另外的变更和修改。所以,所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (10)
1.一种双栅薄膜晶体管的制作方法,其特征在于,包括:
在衬底上形成有源层;
在所述有源层上的两端分别形成源电极和漏电极;
在所述源电极和所述漏电极之间形成介质层;
在所述介质层上并排形成第一栅电极和第二栅电极,且所述第一栅电极的功函数与所述第二栅电极的功函数间存在功函数差。
2.如权利要求1所述的方法,其特征在于,所述第一栅电极和所述第二栅电极分别对应如下任意两种材料:
钼、铜、金、钛、钨和镍。
3.一种双栅薄膜晶体管,其特征在于,包括:
衬底、位于所述衬底上的有源层、位于所述有源层上的介质层、位于所述介质层两侧的源电极和漏电极;
还包括:并排位于所述介质层上的第一栅电极和第二栅电极,且所述第一栅电极的功函数和所述第二栅电极的功函数间存在功函数差。
4.如权利要求3所述的双栅薄膜晶体管,其特征在于,所述第一栅电极和所述第二栅电极分别对应如下任意两种材料:
钼、铜、金、钛、钨和镍。
5.如权利要求3所述的双栅薄膜晶体管,其特征在于,所述介质层的厚度均大于所述源电极的厚度和所述漏电极的厚度,并覆盖所述源电极顶部的部分区域和所述漏电极顶部的部分区域。
6.如权利要求3所述的双栅薄膜晶体管,其特征在于,所述衬底具体为如下任意一种:
硅衬底、玻璃衬底。
7.如权利要求3所述的双栅薄膜晶体管,其特征在于,所述有源层具体为如下任意一种:
非晶硅层、多晶硅层和金属氧化物层。
8.如权利要求3所述的双栅薄膜晶体管,其特征在于,所述源电极所述漏电极为如下任意一种:
钼、铜和金。
9.如权利要求3所述的双栅薄膜晶体管,其特征在于,所述介质层具体为如下任意一种:
二氧化硅层、三氧化铝层、氮化硅层和二氧化氟层。
10.如权利要求3所述的双栅薄膜晶体管,其特征在于,所述介质层的厚度为100nm~10μm。
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Application publication date: 20200908 |