CN102074572A - 集成电路结构 - Google Patents

集成电路结构 Download PDF

Info

Publication number
CN102074572A
CN102074572A CN201010528793.6A CN201010528793A CN102074572A CN 102074572 A CN102074572 A CN 102074572A CN 201010528793 A CN201010528793 A CN 201010528793A CN 102074572 A CN102074572 A CN 102074572A
Authority
CN
China
Prior art keywords
semiconductor
fin
channel isolation
shallow channel
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201010528793.6A
Other languages
English (en)
Other versions
CN102074572B (zh
Inventor
袁锋
李宗霖
陈宏铭
张长昀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102074572A publication Critical patent/CN102074572A/zh
Application granted granted Critical
Publication of CN102074572B publication Critical patent/CN102074572B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

一种集成电路结构，包括一基底，其具有一第一部分于一第一元件区中与一第二部分于一第二元件区中；以及两个隔离区于该第一元件区中且于该基底上。所述两个隔离区包括一第一介电材料其具有一第一k值。一半导体条介于所述两个隔离区之间并与所述两个隔离区邻接，随着该半导体条的一顶部部分形成一半导体鳍状物于所述两个隔离区的顶部表面上。一额外的隔离区于该第二元件区中且于该基底上。该额外的隔离区包括一第二介电材料其具有大于该第一k值的一第二k值。通过使用低介电常数材料来形成元件内浅沟槽隔离区，减少了鳍式场效应晶体管的寄生栅极电容并且增加分别的鳍式场效应晶体管的速度。

Description

集成电路结构
技术领域
本发明大体涉及集成电路，且更特别涉及半导体鳍状物与鳍式场效应晶体管(Fin field-effect transistor，FinFET)及其形成方法。
背景技术
随着增加集成电路的缩小尺寸与增加对集成电路速度的高要求，晶体管必须具有较高的驱动电流与越来越小的尺寸。鳍式场效应晶体管(Finfield-effect transistor，FinFET)因此被发展。图1显示一常见鳍式场效应晶体管的剖面图，其中该剖面图由横跨鳍状物而非源极与漏极区来制作。将鳍状物100形成为垂直的硅鳍状物延伸高于基底102并用以形成源极与漏极区(未显示)及介于其间的通道区。鳍状物100的形成包括使基底102凹陷以形成凹陷处、以一介电材料填满凹陷处、执行一化学机械研磨(chemical mechanicalpolish，CMP)以移除介电材料高于鳍状物的超出部分，及使介电材料的顶部层凹陷以使于凹陷处中的介电材料的剩余部分形成浅沟槽隔离区(shallowtrench isolation，STI)120。浅沟槽隔离区120通常包括氧化硅。栅极108形成于鳍状物100上。形成栅极介电质106以分隔鳍状物100与栅极108。
寄生电容器110被产生于栅极108与鳍状物100之间，其中浅沟槽隔离区120作为寄生电容器110的绝缘体。寄生电容器110的电容值(capacitancevalue)为浅沟槽隔离区120的形状与浅沟槽隔离区120的材料(例如k值)的函数。寄生电容不利地影响分别的集成电路的性能并需要被减少。
发明内容
本发明的目的在于克服现有技术中的缺陷。
根据实施例的一态样，一种集成电路结构包括一基底，其具有一第一部分于一第一元件区中与一第二部分于一第二元件区中；以及两个隔离区于该第一元件区中且于该基底上。所述两个隔离区包括一第一介电材料其具有一第一k值。一半导体条介于所述两个隔离区之间并与所述两个隔离区邻接，随着该半导体条的一顶部部分形成一半导体鳍状物于所述两个隔离区的顶部表面上。一额外的隔离区于该第二元件区中且于该基底上。该额外的隔离区包括一第二介电材料其具有大于该第一k值的一第二k值。
根据本发明另一实施例，一种集成电路结构，包括：
一半导体基底，其包括一第一部分于一元件内区中与一第二部分于一元件间区中；
一元件内浅沟槽隔离区于该半导体基底上，其中该元件内浅沟槽隔离区由具有一第一k值的一低介电常数介电材料所形成；
一第一鳍式场效应晶体管，包括：
一半导体鳍状物与该元件内浅沟槽隔离区邻接且于该元件内浅沟槽隔离区上；
一栅极介电质于该半导体鳍状物上；以及
一栅极电极于该栅极介电质上，其中该栅极电极包括一部分直接于该元件内浅沟槽隔离区上；以及
一元件间浅沟槽隔离区于该半导体基底上，其中没有栅极电极直接形成于该元件间浅沟槽隔离区上，且其中该元件间浅沟槽隔离由一非低介电常数介电材料所形成，该非低介电常数介电材料具有大于该第一k值的一第二k值。
也公开其他实施例。
通过使用低介电常数材料来形成元件内浅沟槽隔离区，减少了鳍式场效应晶体管的寄生栅极电容并且增加分别的鳍式场效应晶体管的速度。
为了让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举优选实施例，并配合附图，进行详细说明。
附图说明
图1显示一常见鳍式场效应晶体管的剖面图；
图2至图10A为根据一实施例在鳍式场效应晶体管制造中的中间阶段的剖面图；
图10B显示于图10A中所示结构的俯视图。
其中，附图标记说明如下：
100～鳍状物
102～基底
106～栅极介电质
108～栅极
110～寄生电容器
120～浅沟槽隔离区(shallow trench isolation，STI)
20～半导体基底
100～元件内区(intra-device region)
200～元件间区(inter-device region)
22～焊垫层
24～掩模层
26～光致抗蚀剂
28～开口
32～沟槽
D～沟槽32的深度
W～沟槽32的宽度
33～半导体条
34～低介电常数材料
34’～元件内浅沟槽隔离区(intra-device shallow trench isolation region)
L1、L1’、L1”～元件内浅沟槽隔离区34’的长度
38、45～凹陷处
40～鳍状物
H～鳍状物40的高度
L2～鳍状物40的长度
44～硬掩模
48、70、72～虚线
50～介电材料
50’～元件间浅沟槽隔离区(inter-device shallow trench isolation region)
62～栅极介电质
64～栅极电极
66～鳍式场效应晶体管
80～电容器
具体实施方式
提供形成鳍式场效应晶体管(Fin field-effect transistor，FinFET)的新颖方法。以图解说明在一实施例的制造中的中间阶段。实施例的变化被讨论。遍及于不同附图与说明的实施例中，相同的标号用来代表相同的元件。
参见图2，提供半导体基底20。在一实施例中，半导体基底20包括硅。其他一般使用的材料，例如碳、锗、镓、砷、氮、铟及/或磷与其类似物也可被包括于半导体基底20中。半导体基底20可为一块状基底(bulk substrate)或一绝缘层上半导体(semiconductor-on-insulator)基底。半导体基底20包括于元件内区(intra-device region)100的部分与元件间区(inter-device region)200的部分。可使用每个元件内区100来形成一鳍式场效应晶体管，同时可通过元件间区200来将元件内区100彼此分离，元件间区200可不具有鳍式场效应晶体管形成于其中。元件间区200可或可不直接介于两个鳍式场效应晶体管之间。
焊垫层22与掩模层24可形成于半导体基底20上。焊垫层22，可为例如使用热氧化工艺(thermal oxidation process)来形成的一包括氧化硅的薄膜。焊垫层22可作为介于半导体基底20与掩模层24之间的一附着层(adhesionlayer)。焊垫层22也可作为蚀刻掩模层24的一蚀刻终止层。在一实施例中，掩模层24为例如使用低压化学气相沉积(low pressure chemical vapordeposition，LPCVD)由氮化硅所形成。在其他实施例中，掩模层24通过硅的热氮化(thermal nitridation)、等离子体辅助化学气相沉积(plasma enhancedchemical vapor deposition，PECVD)或等离子体阳极氮化(plasma anodicnitridation)来形成。在随后的光微影(photolithography)工艺中将掩模层24作为一硬掩模。光致抗蚀剂26形成于掩模层24上且之后将其图案化，形成开口28于光致抗蚀剂26中。
参见图3，经由开口28来蚀刻掩模层24与焊垫层22，露出下方的半导体基底20。之后蚀刻露出的半导体基底20以形成沟槽32与半导体条33，半导体条33为半导体基底20介于沟槽32之间的部分。沟槽32可为互相平行的条带(于俯视中)且被彼此紧密地设置。之后移除光致抗蚀剂26。接着可执行一清洁以移除半导体基底20的自生氧化层(native oxide)。可使用经稀释的氢氟酸(hydrofluoric acid，HF)来执行清洁。
沟槽32的深度D可介于约
Figure BSA00000329520000051
与约
Figure BSA00000329520000052
之间，而宽度W可介于约
Figure BSA00000329520000053
与约
Figure BSA00000329520000054
之间。在一示范实施例中，沟槽32的深宽比(aspectratio)(D/W)为大于约7.0。在其他示范实施例中，深宽比可甚至大于约8.0，然而其也可低于约7.0，或介于7.0与8.0之间。然而，本领域技术人员可了解于说明书全文中所列举的尺寸与数值仅为示例，且可被改变以适合集成电路的不同尺寸。
参见图4，将低介电常数材料34填入沟槽32中。视需要而定，可形成一衬底氧化层(liner oxide)(未显示)于沟槽32中。在一实施例中，衬底氧化层可为一热氧化层(thermal oxide)。在其他实施例中，可使用临场蒸气产生(in situ steam generation，ISSG)来形成衬底氧化层。在又其他实施例中，可使用选择区域化学气相沉积(selective area chemical vapor deposition，SACVD)或其他一般使用的化学气相沉积方法来形成衬底氧化层。衬底氧化层的形成环绕沟槽32的边角，其减低电场并因此改善所产生的集成电路的性能。
低介电常数材料34具有一k值小于3.9。低介电常数材料34的k值也可小于约3.5、3.0、2.5，或甚至小于约2.0。在一实施例中，低介电常数材料34包括含碳的低介电常数材料。在其他实施例中，低介电常数材料包括其他一般已知低介电常数材料，例如硼磷硅玻璃(boro-phospho-silicate glass，BPSG)、磷硅玻璃(phospho-silicate glass，PSG)及/或其类似物。
之后执行一化学机械研磨以使低介电常数材料34的顶部表面与掩模层24的顶部表面同水平。所产生的结构显示于图5中。之后通过一蚀刻步骤使低介电常数材料凹陷，产生如图6中所示的凹陷处38。焊垫层22与掩模层24的剩余部分也被移除。半导体条33延伸出剩余的低介电常数材料34的顶部表面的部分因此变成鳍状物40。鳍状物40的高度H可介于15nm与约50nm之间，然而其也可较大或较小。
接着，如图6中所示，形成硬掩模44以覆盖元件内区100，而留下元件间区200未覆盖，硬掩模44可由氮化硅所形成。之后执行一蚀刻工艺以自元件间区200移除低介电常数材料34的露出部分，形成凹陷处45，如图7中所示。低介电常数材料34在元件内区100中的部分不被移除，且于此之后被称为元件内浅沟槽隔离区(intra-device shallow trench isolationregion)34’。
在图8中，将介电材料50填入凹陷处45内。介电材料50具有一k值大于低介电常数材料34的k值。在一实施例中，介电材料50由一非低介电常数材料所形成，非低介电常数材料具有等于或大于3.9的k值。介电材料50的k值也可大于约5.0。在一示范实施例中，介电材料50包括氧化硅，其可由化学气相沉积，例如次常压化学气相沉积(sub-atmospheric CVD，SACVD)、高密度等离子体化学气相沉积(high density plasma CVD，HDPCVD)或其类似方法来形成。介电材料50的顶部表面为高于硬掩模44的顶部表面。
执行化学机械研磨以使介电材料50的顶部表面与硬掩模44的顶部表面呈水平。之后执行一蚀刻以更进一步使剩余的介电材料50的顶部表面凹陷。所产生的结构显示于图9中。于说明书全文中，介电材料50的剩余部分被二择一地称为元件间浅沟槽隔离区(inter-device shallow trench isolationregion)50’。在一实施例中，在蚀刻步骤之后，元件间浅沟槽隔离区50’的经凹陷的顶部表面实质上与元件内浅沟槽隔离区34’呈水平。在替代实施例中，如以虚线48所示，元件间浅沟槽隔离区50’的经凹陷的顶部表面实质上与鳍状物40的顶部表面呈水平，或在介于鳍状物40的表面与元件内浅沟槽隔离区34’的顶部表面之间的任何水平面。元件间浅沟槽隔离区50’与元件内浅沟槽隔离区34’的底部表面可彼此呈水平。之后移除硬掩模44。在产生的结构中，元件间浅沟槽隔离区50’与元件内浅沟槽隔离区34’也可被视为在半导体基底20上(尽管它们原始被形成于半导体基底20内)。
虽然于上述实施例中，在形成元件间浅沟槽隔离区50’之前形成元件内浅沟槽隔离区34’，然而也可在形成元件间浅沟槽隔离区50’之后形成元件内浅沟槽隔离区34’。在此实施例中，在于图4中所示的步骤中，将非低介电常数材料50填入沟槽32。在步骤7与8中，将非低介电常数材料50的部分自元件内区100移除以形成凹陷处，并且将低介电常数材料34填入凹陷处中。本领域技术人员可了解通过于先前附图中所提供的实施教示。
参见图10A，形成栅极介电质62以覆盖鳍状物40的顶部表面与侧壁。栅极介电质62可通过热氧化形成且因此可包括热氧化硅。于此实施例中，栅极介电质62被形成于鳍状物40的顶部表面上，而不在元件内浅沟槽隔离区34’的顶部表面上。或者，栅极介电质62可通过沉积步骤来形成。因此，栅极介电质62被形成于鳍状物40的顶部表面与元件内浅沟槽隔离区34’的顶部表面上。之后于栅极介电质62上形成栅极电极64。在一实施例中，如图10A中所示，栅极电极64不只覆盖鳍状物40，以使每个所产生的鳍式场效应晶体管66包括多于一个鳍状物40。在替代实施例中，每个鳍状物40可被用来形成一个鳍式场效应晶体管。
图10B显示于图10A中所示结构的俯视图，其中图10A中的剖面图获得自于图10B中的平面横跨线10A-10A。观察到元件内浅沟槽隔离区34’可被元件间浅沟槽隔离区50’所包围。然而，随着分别由虚线70与72所示的对应边界，元件内浅沟槽隔离区34’的大小可为较大或较小。在一实施例中，元件内浅沟槽隔离区34’的长度L1等于鳍状物40的长度L2。在其他实施例中，如由虚线72所示，元件内浅沟槽隔离区34’的长度L1’小于鳍状物40的长度L2。在又其他实施例中，如由虚线70所示，元件内浅沟槽隔离区34’的长度L1”大于鳍状物40的长度L2。之后在鳍状物40不被栅极电极64覆盖的部分上形成鳍式场效应晶体管66的剩余构件，包括源极与漏极区及源极与漏极硅化物(未显示于图10A与图10B中)。这些构件的形成工艺为本技术领域所知，且因此不于此重复。
实施例具有一些优点特征。由于电容器的电容与电容器绝缘体的k值成比例，因此通过使用低介电常数材料来形成元件内浅沟槽隔离区，减少了鳍式场效应晶体管的寄生栅极电容(如图10A中的电容器80所示)并且增加分别的鳍式场效应晶体管的速度。然而，由于元件间浅沟槽隔离区仍可使用一般浅沟槽隔离材料来形成，因此可将由于在元件内浅沟槽隔离区中使用低介电常数材料所引起的应力最小化。
虽然本发明已以优选实施例揭露如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (10)

1.一种集成电路结构，包括：
一基底，其包括一第一部分于一第一元件区中与一第二部分于一第二元件区中；
两个隔离区于该第一元件区中且于该基底上，其中所述两个隔离区包括一第一介电材料其具有一第一k值；
一第一半导体条介于所述两个隔离区之间并与所述两个隔离区邻接，其中该第一半导体条的一顶部部分形成一第一半导体鳍状物于所述两个隔离区的顶部表面上；以及
一额外的隔离区于该第二元件区中且于该基底上，其中该额外的隔离区包括一第二介电材料其具有大于该第一k值的一第二k值。
2.如权利要求1所述的集成电路结构，其中所述两个隔离区的底部表面与该额外的隔离区的底部表面接触该基底。
3.如权利要求1所述的集成电路结构，其中该第一介电材料为一低介电常数介电材料，且该低介电常数介电材料的k值小于3.5。
4.如权利要求1所述的集成电路结构，其中所述两个隔离区之一被该额外的隔离区所包围。
5.如权利要求1所述的集成电路结构，还包括：
一栅极介电质于该第一半导体鳍状物的一顶部表面与侧壁上；以及
一栅极电极于该栅极介电质上，其中该栅极电极包括一部分直接于所述两个隔离区的一部分上。
6.如权利要求1所述的集成电路结构，还包括一第二半导体条，其包括一第二半导体鳍状物于所述两个隔离区的该顶部表面上，其中所述两个隔离区之一介于该第一半导体条与该第二半导体条之间并与该第一半导体条及该第二半导体条邻接。
7.一种集成电路结构，包括：
一半导体基底，其包括一第一部分于一元件内区中与一第二部分于一元件间区中；
一元件内浅沟槽隔离区于该半导体基底上，其中该元件内浅沟槽隔离区由具有一第一k值的一低介电常数介电材料所形成；
一第一鳍式场效应晶体管，包括：
一半导体鳍状物与该元件内浅沟槽隔离区邻接且于该元件内浅沟槽隔离区上；
一栅极介电质于该半导体鳍状物上；以及
一栅极电极于该栅极介电质上，其中该栅极电极包括一部分直接于该元件内浅沟槽隔离区上；以及
一元件间浅沟槽隔离区于该半导体基底上，其中没有栅极电极直接形成于该元件间浅沟槽隔离区上，且其中该元件间浅沟槽隔离由一非低介电常数介电材料所形成，该非低介电常数介电材料具有大于该第一k值的一第二k值。
8.如权利要求7所述的集成电路结构，还包括一第二鳍式场效应晶体管于该半导体基底上，其中该元件间浅沟槽隔离区为水平介于该第一鳍式场效应晶体管与该第二鳍式场效应晶体管之间。
9.如权利要求7所述的集成电路结构，其中该元件间浅沟槽隔离区包围该元件内浅沟槽隔离区。
10.如权利要求7所述的集成电路结构，还包括一半导体条垂直介于该半导体鳍状物与该半导体基底之间且与该半导体鳍状物及该半导体基邻接，且其中该半导体鳍状物、该半导体条与该半导体基底由相同半导体材料所形成。
CN201010528793.6A 2009-10-28 2010-10-25 集成电路结构 Active CN102074572B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US25572409P 2009-10-28 2009-10-28
US61/255,724 2009-10-28
US12/843,658 2010-07-26
US12/843,658 US8592918B2 (en) 2009-10-28 2010-07-26 Forming inter-device STI regions and intra-device STI regions using different dielectric materials

Publications (2)

Publication Number Publication Date
CN102074572A true CN102074572A (zh) 2011-05-25
CN102074572B CN102074572B (zh) 2013-01-30

Family

ID=43897660

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010528793.6A Active CN102074572B (zh) 2009-10-28 2010-10-25 集成电路结构

Country Status (5)

Country Link
US (2) US8592918B2 (zh)
JP (1) JP5377456B2 (zh)
KR (1) KR101229709B1 (zh)
CN (1) CN102074572B (zh)
TW (1) TWI424528B (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102437179A (zh) * 2011-12-07 2012-05-02 中国科学院上海微系统与信息技术研究所 一种抗总剂量辐射加固深亚微米器件的版图结构
CN103828037A (zh) * 2011-07-29 2014-05-28 美商新思科技有限公司 具有块间绝缘体的n沟道和p沟道finfet单元架构
US9691764B2 (en) 2011-07-29 2017-06-27 Synopsys, Inc. FinFET cell architecture with power traces
CN107293588A (zh) * 2016-03-30 2017-10-24 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
CN107731751A (zh) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN104157604B (zh) * 2013-05-14 2018-03-20 格罗方德半导体公司 用于集成电路产品的密集封装的标准单元及其制法
CN108074869A (zh) * 2016-11-14 2018-05-25 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010199161A (ja) * 2009-02-23 2010-09-09 Renesas Electronics Corp 半導体集積回路装置及びその製造方法
TWI587382B (zh) * 2011-10-19 2017-06-11 聯華電子股份有限公司 半導體結構及其製程
US9318431B2 (en) * 2011-11-04 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a MOM capacitor and method of making same
US9893163B2 (en) * 2011-11-04 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3D capacitor and method of manufacturing same
US8735991B2 (en) * 2011-12-01 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. High gate density devices and methods
KR20170121335A (ko) 2011-12-30 2017-11-01 인텔 코포레이션 반도체 구조물
US8969974B2 (en) 2012-06-14 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET device
US8946014B2 (en) 2012-12-28 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device structure and methods of making same
US9093566B2 (en) * 2012-12-31 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. High efficiency FinFET diode
US9000522B2 (en) * 2013-01-09 2015-04-07 International Business Machines Corporation FinFET with dielectric isolation by silicon-on-nothing and method of fabrication
KR102013842B1 (ko) * 2013-02-08 2019-08-26 삼성전자주식회사 반도체 소자의 제조 방법
US8895446B2 (en) 2013-02-18 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Fin deformation modulation
US9953975B2 (en) * 2013-07-19 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming STI regions in integrated circuits
US9023705B1 (en) * 2013-11-01 2015-05-05 Globalfoundries Inc. Methods of forming stressed multilayer FinFET devices with alternative channel materials
US9209178B2 (en) * 2013-11-25 2015-12-08 International Business Machines Corporation finFET isolation by selective cyclic etch
US9196499B2 (en) * 2014-03-26 2015-11-24 Globalfoundries Inc. Method of forming semiconductor fins
US9842944B2 (en) * 2014-07-14 2017-12-12 Intel Corporation Solid-source diffused junction for fin-based electronics
US9236308B1 (en) * 2014-08-19 2016-01-12 Globalfoundries Inc. Methods of fabricating fin structures of uniform height
KR102204387B1 (ko) * 2014-12-17 2021-01-18 삼성전자주식회사 매립형 게이트 구조체를 갖는 반도체 소자 및 그 제조 방법
US9461043B1 (en) * 2015-03-20 2016-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9793403B2 (en) 2015-04-14 2017-10-17 Samsung Electronics Co., Ltd. Multi-layer fin field effect transistor devices and methods of forming the same
KR102393321B1 (ko) 2015-06-25 2022-04-29 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102323943B1 (ko) 2015-10-21 2021-11-08 삼성전자주식회사 반도체 장치 제조 방법
DE112015007241T5 (de) * 2015-12-26 2019-01-24 Intel Corporation Begrenztes und skalierbares helmelement
US9704994B1 (en) * 2016-10-10 2017-07-11 International Business Machines Corporation Different shallow trench isolation fill in fin and non-fin regions of finFET
US9899396B1 (en) * 2016-12-01 2018-02-20 Macronix International Co., Ltd. Semiconductor device, fabricating method thereof, and fabricating method of memory
WO2019066768A1 (en) * 2017-09-26 2019-04-04 Intel Corporation DIRECTIONAL SPACER REMOVAL FOR INTEGRATED CIRCUIT STRUCTURES
KR20200083981A (ko) * 2017-11-30 2020-07-09 인텔 코포레이션 진보된 집적 회로 구조체 제조를 위한 핀 패터닝
US11004748B2 (en) * 2019-06-05 2021-05-11 Globalfoundries U.S. Inc. Semiconductor devices with wide gate-to-gate spacing

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20070228425A1 (en) * 2006-04-04 2007-10-04 Miller Gayle W Method and manufacturing low leakage MOSFETs and FinFETs
US20080081404A1 (en) * 2006-09-29 2008-04-03 Texas Instruments Incorporated Recessed STI for wide transistors
US20090008716A1 (en) * 2007-06-27 2009-01-08 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11163329A (ja) 1997-11-27 1999-06-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
KR100513405B1 (ko) * 2003-12-16 2005-09-09 삼성전자주식회사 핀 트랜지스터의 형성 방법
JP5170958B2 (ja) 2004-01-30 2013-03-27 ルネサスエレクトロニクス株式会社 電界効果型トランジスタおよびその製造方法
WO2006006438A1 (ja) 2004-07-12 2006-01-19 Nec Corporation 半導体装置及びその製造方法
US20060134846A1 (en) * 2004-12-16 2006-06-22 Macronix International Co., Ltd. Method of fabricating a semiconductor structure
JP2006269975A (ja) * 2005-03-25 2006-10-05 Toshiba Corp 半導体装置及びその製造方法
US7859065B2 (en) * 2005-06-07 2010-12-28 Nec Corporation Fin-type field effect transistor and semiconductor device
US7190050B2 (en) * 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
US7247887B2 (en) * 2005-07-01 2007-07-24 Synopsys, Inc. Segmented channel MOS transistor
US7265008B2 (en) * 2005-07-01 2007-09-04 Synopsys, Inc. Method of IC production using corrugated substrate
US7807523B2 (en) * 2005-07-01 2010-10-05 Synopsys, Inc. Sequential selective epitaxial growth
US7508031B2 (en) * 2005-07-01 2009-03-24 Synopsys, Inc. Enhanced segmented channel MOS transistor with narrowed base regions
US8466490B2 (en) * 2005-07-01 2013-06-18 Synopsys, Inc. Enhanced segmented channel MOS transistor with multi layer regions
US7605449B2 (en) * 2005-07-01 2009-10-20 Synopsys, Inc. Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material
KR100657964B1 (ko) * 2005-07-22 2006-12-14 삼성전자주식회사 한 쌍의 핀-타입 채널 영역들에 대응하는 단일 게이트전극을 갖는 반도체 소자 및 랜덤 액세스 메모리
JP2007180362A (ja) * 2005-12-28 2007-07-12 Toshiba Corp 半導体装置
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US7939862B2 (en) * 2007-05-30 2011-05-10 Synopsys, Inc. Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers
EP2073267A1 (en) * 2007-12-19 2009-06-24 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) Method of fabricating multi-gate semiconductor devices and devices obtained

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20070228425A1 (en) * 2006-04-04 2007-10-04 Miller Gayle W Method and manufacturing low leakage MOSFETs and FinFETs
US20080081404A1 (en) * 2006-09-29 2008-04-03 Texas Instruments Incorporated Recessed STI for wide transistors
US20090008716A1 (en) * 2007-06-27 2009-01-08 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103828037A (zh) * 2011-07-29 2014-05-28 美商新思科技有限公司 具有块间绝缘体的n沟道和p沟道finfet单元架构
CN103828037B (zh) * 2011-07-29 2017-03-01 美商新思科技有限公司 具有块间绝缘体的n沟道和p沟道finfet单元架构
US9691764B2 (en) 2011-07-29 2017-06-27 Synopsys, Inc. FinFET cell architecture with power traces
US10990722B2 (en) 2011-07-29 2021-04-27 Synopsys, Inc. FinFET cell architecture with insulator structure
CN102437179A (zh) * 2011-12-07 2012-05-02 中国科学院上海微系统与信息技术研究所 一种抗总剂量辐射加固深亚微米器件的版图结构
CN104157604B (zh) * 2013-05-14 2018-03-20 格罗方德半导体公司 用于集成电路产品的密集封装的标准单元及其制法
CN107293588A (zh) * 2016-03-30 2017-10-24 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US10608112B2 (en) 2016-03-30 2020-03-31 Semiconductor Manufacturing International (Beijing) Corporation FinFET device having FinFET structure and filled recesses that partially extend underneath the Fin structure
CN107731751A (zh) * 2016-08-12 2018-02-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN107731751B (zh) * 2016-08-12 2020-06-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN108074869A (zh) * 2016-11-14 2018-05-25 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
US10707134B2 (en) 2016-11-14 2020-07-07 Semiconductor Manufacturing International (Shanghai) Corporation Fin field-effect transistor and fabrication method thereof

Also Published As

Publication number Publication date
US8846466B2 (en) 2014-09-30
KR101229709B1 (ko) 2013-02-05
US8592918B2 (en) 2013-11-26
US20140004682A1 (en) 2014-01-02
KR20110049679A (ko) 2011-05-12
TWI424528B (zh) 2014-01-21
JP5377456B2 (ja) 2013-12-25
TW201133704A (en) 2011-10-01
CN102074572B (zh) 2013-01-30
US20110095372A1 (en) 2011-04-28
JP2011097058A (ja) 2011-05-12

Similar Documents

Publication Publication Date Title
CN102074572B (zh) 集成电路结构
JP5307783B2 (ja) バルクＦｉｎＦＥＴを形成するＳＴＩ領域中のボイド
US10269901B2 (en) Semiconductor liner of semiconductor device
CN102054741B (zh) 形成集成电路结构的方法
US7652331B2 (en) Semiconductor device and method for fabricating the same
CN103985711B (zh) 具有减少的寄生电容量的FinFET及其制造方法
US7612405B2 (en) Fabrication of FinFETs with multiple fin heights
CN103367442B (zh) 鳍式场效应晶体管的栅极堆叠件
US9006786B2 (en) Fin structure of semiconductor device
US9112033B2 (en) Source/drain structure of semiconductor device
CN100593860C (zh) 具有凹陷通道晶体管的半导体器件
US10854602B2 (en) FinFET device and method for fabricating the same
CN102034868A (zh) 半导体装置及场效应晶体管
CN104332410A (zh) 一种鳍式场效应晶体管的制造方法
CN101916783A (zh) 一种凹陷沟道的横向和纵向扩散型场效应晶体管及其制造方法
US20230052056A1 (en) Transistor structure with metal interconnection directly connecting gate and drain/source regions
CN104362097A (zh) 一种鳍式场效应晶体管的制造方法
KR101163909B1 (ko) 벌크 ＦｉｎＦＥＴ에서 Ｓｉ 핀의 핀 하부 부근의 ＳＴＩ 형상

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant