CN102064120A - 一种基于铟凸点的无助焊剂回流工艺方法 - Google Patents

一种基于铟凸点的无助焊剂回流工艺方法 Download PDF

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CN102064120A
CN102064120A CN2010105154440A CN201010515444A CN102064120A CN 102064120 A CN102064120 A CN 102064120A CN 2010105154440 A CN2010105154440 A CN 2010105154440A CN 201010515444 A CN201010515444 A CN 201010515444A CN 102064120 A CN102064120 A CN 102064120A
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indium
salient point
layer
described method
silver
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CN102064120B (zh
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黄秋平
罗乐
徐高尉
袁媛
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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Priority to CN2010105154440A priority Critical patent/CN102064120B/zh
Publication of CN102064120A publication Critical patent/CN102064120A/zh
Priority to PCT/CN2011/081091 priority patent/WO2012051960A1/zh
Priority to US13/880,451 priority patent/US8900986B2/en
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Abstract

本发明涉及一种基于铟凸点的无助焊剂回流的工艺方法，其特征在于包括基板金属化、钝化层开口、凸点下金属化层增厚、电镀铟凸点、电镀银层包覆铟凸点、凸点回流。采用本发明提供的工艺可实现铟凸点阵列的无助焊回流，该工艺可应用于某些特殊的光电芯片，MEMS芯片和生物检测芯片中的倒装互连中。

Description

一种基于铟凸点的无助焊剂回流工艺方法
技术领域
本发明涉及到一种基于铟凸点阵列的无助焊剂回流工艺方法，主要用于需进行免助焊剂的微机电(MEMS)系统，光电芯片(Photoelectric chip)与生物芯片(Bio-chip)等倒装焊接工艺中，属于微电子封装领域。
背景技术
焊料在微电子封装中是必定要用到的，它主要实现器件内部及器件间信号传输与机械支撑等。常用的金属焊料，如锡基焊料，由于其表面极易形成一层金属氧化层，在用它对器件进行封装焊接时，该氧化层会阻碍焊接过程的顺利进行，在不去除该氧化层的情况下焊接，往往很难获得高质量的互连效果。为得到好的互连效果，通常需在焊接时使用助焊剂而去除焊料表层氧化层从而得到高质量的焊接。但是在某些特殊的应用中，如某些光电芯片(带光学镜头)，微机电系统和生物检测芯片的焊接中，焊接过程中如果引入助焊剂将会不可避免地给器件带来污染，这些污染对器件性能的影响通常是致命的，因此在此类应用中，助焊剂一般是禁用的。为达到上述要求，开发一些可实现免助焊剂情况下可实现良好焊接的工艺技术是必须的。实现该技术的可用方案有两种：采取特殊的助焊剂(如用氢气等还原性强的气体或用等离子对焊料表面进行清洗)，采取特殊方法防止焊料表面发生氧化。
对无助焊剂的倒装焊工艺而言，第一步是如何实现焊料凸点在无助焊剂情况下成功实现回流。迄今为止，Chin C.Lee领导的课题组对基于锡基焊料的免助焊剂焊接工艺做出了一些研究，实现了两片状芯片间无助焊剂的键合[Chin C.Lee，Ricky W.Chuang，Fluxless Non-Eutectic Joints Fabricated Using Gold-Tin Multilayer Composite，IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES，VOL.26，NO.2，JUNE 2003.]；Jeong-Won Yoon等利用顺次序电镀工艺实现了锡基凸点阵列的凸点阵列回流工艺，为利用凸点阵列实现无助焊剂回流提供了一种思路[Jeong-Won Yoon，Hyun-Suk Chun，Seung-Boo Jung，Reliability evaluation of Au-20Sn flip chip solder bump fabricated by sequential electroplating method with Sn and Au.Materials Science and Engineering A 473(2008)119-125.]。本发明试图实现基于铟无助焊剂凸点回流工艺，我们知道，铟是一种性能极佳的低温焊料，也是锡基等常用焊料所没有的特性，被广泛用于光电芯片等的封装中。本发明提出一种基于两次电镀，并选择适当的方式保持了铟焊料的特性。基于此方法既可实现其无助焊剂回流，而且还可以使回流温度保持在较低的温度范围内。此工艺尚未见报道。
发明内容
本发明的目的在于提供一种基于铟凸点的无助焊剂回流的工艺方法，常用的阻止氧化的金属材料是金和银。实际工艺中，在铟的表层引入一层金层来阻止铟的氧化而实现其在较低温度下回流成球是不现实的。这是因为从金-铟平衡相图可知，在铟中引入少量的金，就会使其熔点急剧上升，而这一点是不希望看到的，因为这样会失去铟作为一种性能优良的低温焊料的优势。而如果在铟的表面引入银层则不会出现这种情况，显然可以避免这种情况：但从铟-银平衡相图知，向铟中引入银后，其焊料熔点先降低，当铟银质量比约为96％∶4％时到达共晶点，此时焊料熔点为144℃，比铟的熔点156.6℃C还低，其后随着银含量的增加，In-Ag焊料熔点缓慢上升。由此可见，用银对铟包覆既可防止铟凸点表面氧化，同时还能保证焊料熔点不会迅速上升，从而可实现低温回流。
因此，本发明中设计出了一种工艺方法以实现银对铟凸点阵列的包覆，该工艺步骤的设计是本发明的关键点。所以本发明是以在硅基板上的制作流程为例说明具体的工艺过程。
该发明的具体工艺过程如下：
A.基板金属化
(a)对硅片进行热氧化，以得到绝缘的基板；
(b)在基板上溅射种子层，如溅射Ti/Cu/Ti，在铜表面溅射Ti层是为了增强钝化层与该金属层间的附着力且避免铜层的氧化；铜与钝化层间的粘附力很差，Ti与SiO2的粘附力较强；
B.钝化层开口
(a)用PECVD(plasma-enhanced chemical vapor deposition，离子增强型气相沉积法)沉积SiO2作为钝化层；
(b)涂覆薄胶(厚度为1-3μm，此厚度是为了利用电镀铜来实现铜UBM制作)并光刻，之后对光刻胶清边，用BOE(bufferrd-oxide-etch，缓冲氧化层腐蚀)湿法腐蚀或RIE(reaction ion etching，反应离子刻蚀)实现钝化层进行开口和硅片边缘的接触电极的形成，钝化层开口直径是根据凸点直径而定，一般为30-50μm；
C.凸点下金属化层增厚
(a)利用电镀法对Ti/Cu UBM层进行铜增厚。因溅射的铜层不能做得较厚，一般只做到1000
Figure BSA00000313942800031
-6000
Figure BSA00000313942800032
间；较薄的铜层极易导致凸点在回流过程发生脱落，增加铜层厚度可以改善焊球脱落发生脱落的现象；通常增厚后厚度为3-4μm；
D.电镀铟凸点
(a)丙酮去胶(也可在凸点回流前进行)；
(b)电镀铟凸点，电镀过程以及电镀完成后应避免铟凸点与空气的直接接触，将电镀完成的硅片置于去离子水或酒精等中可实现其与空气的接触；
E.电镀银层包覆铟凸点
(a)铟凸点表面镀银；镀层厚度通过电镀电流大小和电镀时间控制，最终结果是用银层实现对铟凸点表层的完全包覆；但同时要保证银镀层较薄，从而使得In-Ag焊料熔点不会太高；银铟原子比例接近Ag-In共晶点；
F.凸点回流
(a)选择恰当的回流曲线，将凸点阵列置于氮气气氛或氢气气氛退火炉中进行回流，回流峰值温度在180-220℃之间；在回流峰值温度上回流3-8min，使之回流成球；
(b)对回流好的凸点进行切片等后期处理。
由此可见，本发明提出了可实现凸点在无助焊剂帮助下成功实现回流的工艺方法。以性能优良、熔点低的铟焊料为主要成分；采取比较简单的按次序两次电镀工艺，即先电镀出铟凸点，再在其表层电镀一层用于阻止氧化的银镀层；较低的回流峰值温度，由于铟-银在一个较大的原子比例范围内均保持较低的熔点，因此实现了银对铟的包覆后，凸点仍可在较低的温度下实现回流成球，范例中的回流峰值温度为200℃，此特点可满足某些需低温焊接的应用场合。采用本发明提供的工艺可实现铟凸点阵列的无助焊回流，该工艺可应用于某些特殊的光电芯片，MEMS芯片和生物检测芯片中的倒装互连中。
本发明的特征在于：
①对衬底进行金属化和实现钝化层开口后，采取依次顺序电镀的方式实现凸点制备的工艺步骤，这是本发明的关键之处；
②用Ti/Cu/Ti对基板进行金属化；
③用PECVD制作SiO2作为凸点钝化层，用BOE湿法腐蚀对其进行开口；
④通过控制电镀条件来实现银层对铟凸点表层的完美包覆；
⑤凸点回流：将需回流的芯片放于温度过程可控的退火炉中，且回流设备提供氮气或氢气等保护氛围。
附图说明
图1为本发明提供的无助焊剂回流工艺流程图。
具体实施方式
为了能使本发明的优点和积极效果得到充分体现，下面结合附图1，有8个步骤，包括实现衬底金属化，钝化层开口，电镀铜、铟和银，凸点回流成球等工艺，具体描述了在硅片上实现直径为40μm左右的铟凸点无助焊回流工艺之一例。
步骤1基板金属化，在硅基板上热氧化一层做绝缘用的氧化层101，厚度为5000
Figure BSA00000313942800041
再在其上溅射Ti/Cu/Ti(200
Figure BSA00000313942800042
/2000
Figure BSA00000313942800043
/200
Figure BSA00000313942800044
)的复合金属薄膜，以作为电镀的种子层和UBM(under bump metallization，凸点下金属化层)；
步骤2钝化层制作，PECVD(plasma-enhanced chemical vapor deposition，离子增强型气相沉积法)沉积一层5000的SiO2103作为钝化层；
步骤3，涂覆并光刻1.7μm的S1912104，为钝化层开口做准备，S1912是一种成熟的、常用的薄胶光刻胶，用它很容易获得均匀且厚度1-3μm的涂覆效果；
步骤4钝化层开口，采用BOE湿法腐蚀SiO2和Ti露出溅射的铜层105，钝化层开口直径为40μm左右；
步骤5金属化层增厚，利用铜电镀液对铜层增厚，电镀铜106层厚度约为3-4μm；铜层增厚后，用丙酮去除薄胶S1912；用丙酮去胶工艺也可放在步骤8凸点回流前进行。
步骤6电镀铟凸点，在电流密度为5-20mA/cm2下电镀铟，通过控制电镀时间来控制电镀铟的量，最后电镀出铟凸点107；将电镀完铟凸点的硅片置于去离子水中，以避免铟凸点表层发生氧化；
步骤7，在铟凸点表层利用电镀的方法实现银层108对铟凸点的包覆，银层厚度需控制在一定的范围内，以避免银铟原子比例偏离共晶点太远而致使其熔点高于铟熔点太多；所以应选择接近共晶点；
步骤8，将电镀完成的硅片置于氮气气氛的回流炉中进行回流，控制生成的合金成分，其中回流时峰值温度为200℃，在此温度上回流5min，最后得到经过回流所得的109凸点；进行切点后处理。

Claims (10)

1.一种基于铟凸点的无助焊剂回流工艺方法，其特征在于包括以下各步：
A.基板金属化
(a)对硅片进行热氧化，以得到绝缘的基板；
(b)在基板上溅射Ti/Cu/Ti种子层；
B.钝化层开口
(a)用离子增强型气相沉积法沉积SiO2作为钝化层；
(b)涂覆薄胶并光刻，之后对光刻胶清边，用缓冲氧化层腐蚀湿法腐蚀或反应离子刻蚀实现钝化层开口和硅片边缘形成接触电极；
C.凸点下金属化层增厚
(a)利用电镀法对Ti/Cu UBM层进行铜增厚；
D.电镀铟凸点
(a)在上述步骤C铜层增厚后，丙酮去胶；
(b)电镀铟凸点，电镀过程以及电镀完成后应避免铟凸点与空气的直接接触，将电镀完成的硅片置于去离子水或酒精中实现其与空气的接触；
E.电镀银层包覆铟凸点
铟凸点表面镀银，使银层实现对铟凸点表层的包覆，铟凸点仍可在较低温度下实现成球；
F.凸点回流
(a)将步骤E的包覆银层的铟凸点，在氮气或氢气氛退火炉中进行回流成球，回流峰值温度为180-220℃之间；
(b)对回流后成球的凸点进行切片后处理。
2.按权利要求1所述的方法，其特征在于在基板上溅射Ti/Cu/Ti种子层厚度依次为200/2000/200
Figure FSA00000313942700013
3.按权利要求1所述的方法，其特征在于步骤B中(b)所述的涂覆薄胶厚度为1-3μm，所述的薄胶为S1912。
4.按权利要求1所述的方法，其特征在于步骤B中(b)所述的钝化层开口直径根据凸点直径而定，通常为30-50μm。
5.按权利要去1所述的方法，其特征在于步骤E中所述的铜层增厚后厚度为3-4μm。
6.按权利要求1所述的方法，其特征在于铜层增厚后用丙酮去胶步骤或放在步骤F凸点回流前进行。
7.按权利要求1所述的方法，其特征在于：
①电镀铟凸点的电流密度为5-20mA/cm2；
②步骤E中银层对铟层的包覆是通过电镀电流大小和时间控制的，银铟原子比例接近Ag-In的共晶点。
8.按权利要求1所述的方法，其特征在于步骤F中在所述的回流峰值温度时回流时间为3-8分钟，使之回流成球。
9.按权利要求1所述的方法，其特征在于步骤E中回流峰值温度为200℃。
10.按权利要求8或9所述的方法，其特征在于在200℃峰值温度回流时间为5分钟。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012051960A1 (zh) * 2010-10-22 2012-04-26 中国科学院上海微系统与信息技术研究所 一种基于铟凸点的无助焊剂回流工艺方法
CN102543783A (zh) * 2012-03-28 2012-07-04 上海交通大学 一种使用铟和微针锥结构的热压缩芯片低温互连方法
WO2013004083A1 (zh) * 2011-07-01 2013-01-10 中国科学院微电子研究所 一种基于柔性基板封装的屏蔽结构及其制作工艺
CN109817515A (zh) * 2017-11-22 2019-05-28 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN110660690A (zh) * 2019-09-29 2020-01-07 中国电子科技集团公司第十一研究所 红外探测器读出电路铟凸点制备方法
TWI689631B (zh) * 2014-10-10 2020-04-01 日商石原化學股份有限公司 合金凸塊的製造方法
CN114420798A (zh) * 2021-12-07 2022-04-29 深圳市思坦科技有限公司 接触电极的制备方法、Mirco-LED阵列器件及其制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170167042A1 (en) * 2015-12-14 2017-06-15 International Business Machines Corporation Selective solder plating

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071778A (zh) * 2006-05-08 2007-11-14 中芯国际集成电路制造(上海)有限公司 焊料凸点制作方法
US20080050905A1 (en) * 2006-05-29 2008-02-28 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
CN101330065A (zh) * 2007-06-22 2008-12-24 中芯国际集成电路制造(上海)有限公司 凸点制作方法、凸点下金属层及制作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6742701B2 (en) * 1998-09-17 2004-06-01 Kabushiki Kaisha Tamura Seisakusho Bump forming method, presoldering treatment method, soldering method, bump forming apparatus, presoldering treatment device and soldering apparatus
US20040140219A1 (en) * 2003-01-21 2004-07-22 Texas Instruments Incorporated System and method for pulse current plating
KR100512971B1 (ko) * 2003-02-24 2005-09-07 삼성전자주식회사 솔더볼을 이용한 마이크로 전자 기계 시스템의 제조 방법
US20050253282A1 (en) * 2004-04-27 2005-11-17 Daoqiang Lu Temperature resistant hermetic sealing formed at low temperatures for MEMS packages
JP4490861B2 (ja) * 2005-04-25 2010-06-30 日立協和エンジニアリング株式会社 基板
TWI414580B (zh) * 2006-10-31 2013-11-11 Sumitomo Bakelite Co 黏著帶及使用該黏著帶而成之半導體裝置
US8546930B2 (en) * 2008-05-28 2013-10-01 Georgia Tech Research Corporation 3-D ICs equipped with double sided power, coolant, and data features
JP5335931B2 (ja) * 2008-12-26 2013-11-06 メギカ・コーポレイション 電力管理集積回路を有するチップ・パッケージおよび関連技術
WO2011099934A1 (en) * 2010-02-10 2011-08-18 Agency For Science, Technology And Research A method of forming a bonded structure
CN102064120B (zh) * 2010-10-22 2012-02-15 中国科学院上海微系统与信息技术研究所 一种基于铟凸点的无助焊剂回流工艺方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101071778A (zh) * 2006-05-08 2007-11-14 中芯国际集成电路制造(上海)有限公司 焊料凸点制作方法
US20080050905A1 (en) * 2006-05-29 2008-02-28 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
CN101330065A (zh) * 2007-06-22 2008-12-24 中芯国际集成电路制造(上海)有限公司 凸点制作方法、凸点下金属层及制作方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012051960A1 (zh) * 2010-10-22 2012-04-26 中国科学院上海微系统与信息技术研究所 一种基于铟凸点的无助焊剂回流工艺方法
US8900986B2 (en) 2010-10-22 2014-12-02 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Method to realize flux free indium bumping
WO2013004083A1 (zh) * 2011-07-01 2013-01-10 中国科学院微电子研究所 一种基于柔性基板封装的屏蔽结构及其制作工艺
CN102543783A (zh) * 2012-03-28 2012-07-04 上海交通大学 一种使用铟和微针锥结构的热压缩芯片低温互连方法
CN102543783B (zh) * 2012-03-28 2015-06-24 上海交通大学 一种使用铟和微针锥结构的热压缩芯片低温互连方法
TWI689631B (zh) * 2014-10-10 2020-04-01 日商石原化學股份有限公司 合金凸塊的製造方法
CN109817515A (zh) * 2017-11-22 2019-05-28 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
CN110660690A (zh) * 2019-09-29 2020-01-07 中国电子科技集团公司第十一研究所 红外探测器读出电路铟凸点制备方法
CN110660690B (zh) * 2019-09-29 2021-12-17 中国电子科技集团公司第十一研究所 红外探测器读出电路铟凸点制备方法
CN114420798A (zh) * 2021-12-07 2022-04-29 深圳市思坦科技有限公司 接触电极的制备方法、Mirco-LED阵列器件及其制备方法

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