CN101924058A - 用于减小芯片翘曲度的方法 - Google Patents

用于减小芯片翘曲度的方法 Download PDF

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CN101924058A
CN101924058A CN2009102123965A CN200910212396A CN101924058A CN 101924058 A CN101924058 A CN 101924058A CN 2009102123965 A CN2009102123965 A CN 2009102123965A CN 200910212396 A CN200910212396 A CN 200910212396A CN 101924058 A CN101924058 A CN 101924058A
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organic material
photoresist
chip
wafer
opening
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CN101924058B (zh
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吴汀淏
郑创仁
李久康
蔡尚颖
彭荣辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种用于减小芯片翘曲度的方法。其中，一种形成集成电路结构的方法包括：提供包括正面和背面的晶片，其中，该晶片包括芯片；形成从背面延伸到芯片的开口；将有机材料填充到开口中，其中，有机材料基本上都不在该开口的外部，而是在晶片的背面上；以及对有机材料进行烘培以使有机材料收缩。

Description

用于减小芯片翘曲度的方法
本申请要求于2008年11月12日提交的题为“Flat Plane WaferControl Method by MEMS Process(利用MEMS处理的平面晶片控制方法)”的第61/113,872号美国临时专利申请，其全部内容结合于此作为参考。
技术领域
本发明总体涉及集成电路，更具体地，涉及用于减小晶片和芯片的翘曲度的方法和结构。
背景技术
在本领域中所众所周知的，大多数集成电路被制造在晶片(通常为半导体晶片，更典型地为硅晶片)上。经过过去几十年，晶片的直径已从仅两英寸增至八英寸，而且近年来，直径增至十二英寸，也被称为300mm晶片。尽管现在制造的一些器件被制造在八英寸晶片上，但是大多数新的集成器件制造设备将被设计成制造在十二英寸晶片上。
由于圆的面积与其直径的平方相关，所以直径百分之五十的增长(如从八英寸晶片移至十二英寸晶片)导致多于两倍的用于制造装置的可用表面面积。
集成电路器件制造的另一个趋势涉及封装技术。随着向表面黏着技术的发展以及所谓的低轮廓封装件(low profile package)，作为封装处理(process，也称工艺)的一部分，晶片被研磨成不断减小的厚度。
随着晶片的直径变大以及厚度变薄，之前未知或至少不重视的力起到更重要的作用。这些力包括施加至晶片以及作为集成电路制造处理的一部分通过形成在其上的薄膜施加至在晶片上的芯片的压力或张 应力。
将压力施加至较薄的晶片/芯片的大量薄膜的组合导致晶片/芯片和随后形成的集成电路的显著翘曲。(众所周知，晶片被切成独立的多个芯片，当被封装时，这些芯片形成完整的集成电路器件)。
翘曲具有一些有害的影响。一个负面影响是芯片或晶片的翘曲可能显著地影响形成在芯片/晶片中的器件的电性能。众所周知，其中形成有MOS晶体管的半导体层的张力可能显著地影响电荷载子迁移率。由芯片/晶片的翘曲所引起的张力可能不利地影响电荷载子迁移率。
通常，晶片/芯片的翘曲问题是通过在晶片的正面或背面上涂覆一层膜来解决的(其中，该膜具有固有应力)，这导致晶片向现有翘曲方向相反的方向弯曲，因此补偿了现有翘曲。因而，可以形成平坦的晶片。在切割处理之后，所得到的芯片也是平坦的。然而，并不是所有的晶片都可以使用这种方法来固定。例如，为了例如感测声波(在MEMS麦克风中)、或者允许液体流动(在微型喷墨头或生物流量泵(bio flow pump)的目的，微型电机系统(MEMS)器件需要暴露在所得到的芯片之外的外部环境中。这样的芯片就不能被涂覆有膜。
因此，需要用于克服现有技术中的上述缺点的方法和结构。
发明内容
根据本发明的一个方面，集成电路结构包括分立芯片(其包括背面)、从背面延伸到分立芯片中的开口、以及开口中的有机材料。有机材料部分地或全部地填充开口。有机材料可以包括光刻胶。
根据本发明的另一方面，集成电路结构包括芯片。该芯片包括正面以及在作为正面的芯片的相反侧上的背面。多个沟槽在该芯片中并从背面延伸到芯片中。光刻胶填充多个沟槽，其中，光刻胶基本上不在多个沟槽的外部，而是在芯片的背面上。
根据本发明的又一方面，一种形成集成电路结构的方法包括：提供具有正面和背面的晶片，其中，该晶片包括芯片；形成从背面延伸到该芯片中的开口；以及将有机材料填充在开口中。有机材料基本上 都不在开口的外部，而是在晶片的背面上。有机材料被烘培以使有机材料收缩。
根据本发明的又一方面，一种用于形成集成电路结构的方法包括：提供具有正面和背面的晶片。该晶片包括芯片。该方法还包括：形成从背面延伸到芯片中的多个沟槽；将第一光刻胶填充在多个沟槽中；去除第一光刻胶在多个沟槽外部的部分；以及烘培第一光刻胶。
这些实施例的有利特征包括用于减少并基本上消除半导体芯片的翘曲的能力、以及将本发明的实施例应用于不能被施加压涂覆(stressed coating)的结构的灵活性。
附图说明
为了更加彻底地理解本发明及其优点，现在结合附图进行下列描述以作出参考，其中：
图1和图2示出了将光刻胶填充到两个相邻的结构之间的空间中以及烘培光刻胶的效果；
图3示出了作为填充到晶片的沟槽中的光刻胶的量的函数的晶片翘曲；
图4A至图8B是在本发明实施例的制造中的中间阶段的顶视图和截面图，其中，图5C-F是图5A所示的芯片30的可能仰视图；以及
图9A和图9B是包括本发明的实施例的封装件。
具体实施方式
以下，将详细描述实施例的制造和使用。然而，应该理解，这些实施例提供了可以在各种特定情况下具体化的许多可应用的发明构思。所描述的具体实施例仅仅说明制造和使用本发明的具体方式，而不限制本发明的范围。
提出了具有应力补偿沟槽的新半导体芯片及其形成方法。说明了制造实施例的中间阶段。描述了该实施例的改变。在各个视图和示意性实施例中，类似的参考标号用于指定类似元件。在整个说明书中， 当晶片被以正面向上放置并且翘曲(warpage)使晶片的边缘高于晶片的中心时，翘曲被认为具有正值，并被称为正翘曲。相反，如果边缘低于晶片的中心，则晶片被认为具有负值，并被称为反翘曲。另外，如果翘曲的绝对值增大，则不管翘曲是正的还是反的，翘曲都被认为“增大”。
图1和图2示意性地示出了本发明的发明人在其上执行了实验的结构(structure)的截面图。参考图1，结构12形成在基板10上。结构12可以是基板10的一部分，并且可以通过蚀刻基板10来形成，使得结构12位于周围的基板材料之上。可选地，结构12可以是形成在基板10的表面上的部件(feature)。空间14存在于相邻的结构12之间。光刻胶16被填充到空间14中，然后被烘培。作为烘培的结果，光刻胶16收缩，因此，将压缩力施加至结构12。因此，在基板1中发生翘曲，如图2所示。出于说明的目的，翘曲被夸大。
在另一实验中，提供了基本平坦的晶片(未示出)，并且沟槽被形成在晶片的背面上，其中，在晶片中的每一个芯片中，沟槽形成同心环，并且每个环将芯片的中心作为其中心。然后，执行多次光刻胶填充和烘培处理，其中，将光刻胶填充到沟槽中并堆叠在先前光刻胶填充处理中填充的光刻胶上。因此，每次光刻胶填充处理都使光刻胶在沟槽中的厚度增加。在图3中示出了结果，其中，X轴表示光刻胶填充的次数，而Y轴表示晶片翘曲度(warpage)，其中，在图4B中晶片翘曲度的意思可以被称为翘曲度WAP1。图3中的点20表示具有形成30μm的深度但其中未填充光刻胶的沟槽的晶片的初始翘曲度。
在实验中，当光刻胶没有被填充到沟槽中(第0次填充)时，晶片具有约-5μm的翘曲。沟槽首先被填充有第一层光刻胶，其中，第一层光刻胶在沟槽中具有10μm的厚度T(参考图1)。然后，晶片被烘培。我们发现，在烘培之后，晶片的翘曲度增大至约-30μm，如由点22所示。接下来，将也具有10μm厚度的第二层光刻胶填充到沟槽中并且在第一层光刻胶之上。然后，执行了第二次烘培。作为第二次烘培的结果，晶片的翘曲度增大至约-65μm，如由点24所示。接下来， 也具有10μm厚度的第三层光刻胶填充到沟槽中并且在第二层光刻胶之上。然后，执行第三次烘培。再次，翘曲度增大至约-82μm，如由点26所示。
图3所示的结果揭示了，通过在晶片的背面形成沟槽、将光刻胶填充在沟槽中并对光刻胶进行烘培，可能产生反翘曲。另外，反翘曲度的大小随着光刻胶厚度的增大而增加。因此，如果晶片或芯片具有有正翘曲度，则通过使用如图1至图3所示的方法，可以补偿正翘曲。所得到的晶片的翘曲度至少可以被减小，在使用了适当量的光刻胶的情况下，翘曲可能基本上被消除。由于晶片基本上是平坦的，所得到的芯片在其被从晶片锯掉之后也是平坦的。
图4A至图8B示出了在实施例中的中间阶段的截面图和顶视图。参考图4A，形成了芯片30。芯片30是晶片100的一部分，其在图4B中被示意性地示出，其中，芯片30可以是晶片100中的任意芯片。另外，晶片100中的所有芯片均具有与芯片30相同的结构，并且将经过如图5A至图8A所示的相同处理。芯片30可以包括半导体基板32，其可以包括硅、锗、GaAs或其他通用的半导体材料。此外，半导体基板32还可以是大块基板，或者具有绝缘半导体结构。由框表示的器件34和36形成在基板32的正面(图4A中面朝上的表面)处。在一个实施例中，器件34包括互补金属氧化物半导体(CMOS)器件、双极结式晶体管、电容器、晶体管等。器件可以是MEMS器件，其可以包括MEMS麦克风、微型流泵、微型喷墨头等。芯片30还包括在正面上的互连结构38，其中，互连结构38可以包括金属线和通孔(未示出)。另外，焊盘40可以形成在芯片30的正面上。再次参考图4A，晶片100具有翘曲度WAP1，其是正翘曲度。此外，出于说明目的，在所有附图中，晶片100的翘曲可能被夸大。
如图5A所示，沟槽44形成在芯片30的背面上，并且均可以在基板32中或者形成在基板32的背面上的(多个)层中，该(多个)层包括但不限于半导体层、介电层、金属层、多晶硅层及其结合。应该注意，术语“沟槽”是指长度和宽度不同的开口，也指长度和宽度基 本相同的开口。沟槽44可以通过蚀刻或激光打孔、或者任何其他可应用方法来形成。图5B至图5F示出了如图5A所示的芯片30的可能仰视图。请注意，形成在芯片30的背面上的任何沟槽或开口在填充在其中的光刻胶被烘培之后均具有引起正翘曲度的效果。因此，沟槽44可以具有除了所示出和/或描述的图案外的任何其他图案，并且图5B至图5F中所示的图案仅是实例，而不应限制本发明的范围。
在图5B中，沟槽44形成同心环，其中，每一个环都是正方形。在一个实施例中，每个沟槽44被限制在相应芯片30的范围内，而不延伸到围绕芯片30的划线(scribe line)46中，尽管沟槽44可以延伸到划线46中。因而，晶片100中的每个芯片30均具有其自身的沟槽44。图5C示出了可选实施例，其中，沟槽44形成同心圆。
在可选实施例中，沟槽44不形成闭环图案。例如，在图5D中，沟槽44不彼此连接。在图5E中，沟槽44平行于X轴方向或平行于Y轴方向分配，其中，X轴方向和Y轴方向都平行于基板32的正面和背面(在图5E中未示出，请参照图5A)，并且被称为平面内方向。然而，在每个小区域中，沟槽44可以彼此平行，并且垂直于相邻区域中的沟槽44。在图5F中，沟槽44实际上是深孔的形式，这些深孔的长度和宽度基本上是相同的。深孔44可以排列形成矩阵、蜂窝的形状、或者任何其他形状。每个深孔可以具有矩形或圆形的形状。在本发明的这些实施例中，沟槽44可以具有对称图案，其或者对称于芯片30的中心45、或者对称于芯片的X轴和Y轴，其中，X轴平行于芯片30的一侧，而Y轴平行于芯片30的另一侧并垂直于X轴。更优选地，沟槽44对称于芯片30的中心45、芯片30的X轴和Y轴，使得由沟槽44所施加的合成应力也是对称的。
沟槽44的最佳密度、宽度W和深度D(参照图5A)、以及长度L(参照图5B和5E)取决于将补偿的翘曲度，并且可以通过实验得到。较大密度的沟槽44将导致在垂直于沟槽的长度方向的方向上的较大翘曲度补偿效应。在示例性实施例中，宽度W在约5μm与10μm之间。深度D小于约150μm，并且甚至可以小于50μm。然而，应认识 到，在整篇说明书中所列举的尺寸仅是实例，并且在使用不同形成技术或者在实验揭示不同尺寸是优选的情况下，可以改变。
图6A至图8B示出了重复的光刻胶填充和烘培处理。请注意，在实际的光刻胶应用处理中，当执行这些处理步骤时，沟槽44可以面朝上。参照图6A，沟槽44填充有光刻胶50。应注意，喷射或旋压(spinon)的光刻胶50可以具有直接在芯片30的背面之上的第一部分(使用虚线示出)、以及在沟槽44中的第二部分，并且期望光刻胶50的第二部分的厚度显著大于第一部分的厚度。因此，可以使用干蚀刻或湿蚀刻来各向异性地或各向同性地蚀刻光刻胶50的第一部分。尽管被蚀刻而变薄，但是光刻胶50的第二部分将仍具有剩余在沟槽44中的部分。可选地，光刻胶50的第一部分可以通过首先暴露于光中、然后显影来去除，使得仅去除暴露的第一部分。在又一个实施例中，可以使用诸如CMP的其他方法。然后，例如使用熔炉烘培来对晶片进行烘培。烘培导致晶片的翘曲度从翘曲度WAP1减小至WAP2，如图6B所示。
接下来，如图7A所示，光刻胶52被填充在沟槽44中并在光刻胶50之上。填充处理可以基本上与在前述章节中所描述的填充处理相同。执行第二次烘培。作为第二次烘培的结果，晶片的翘曲度从WAP2减小至WAP3，如图7B所示。接下来，将光刻胶54被填充在沟槽44中并进行烘培，如图8A所示。类似地，光刻胶54的填充和烘培导致翘曲度进一步减小。最后，如图8B所示，晶片100的翘曲被基本上消除，从而产生基本平坦的晶片100。
在将芯片30从晶片100分离(其可以使用锯子或激光器来进行)之后，光刻胶50、52和54可能仍留在沟槽44中，并且被封装成封装件，如图9A和9B所示。可选地，可以从沟槽44去除光刻胶50、52和54，并且在芯片30从晶片100分离开之后去除光刻胶。在整篇说明书中，已从相应晶片100分离的芯片30被称为分立芯片。图9A示出了示例性的引线键合封装件，其中，芯片30被通过导线64接合至封装基板60。未填充部分(underfill)62可以被填充在芯片30的背面与封装基板60之间。图9B示出了示例性的覆晶(flip-chip)封装，其 中，芯片30通过锡球66接合至封装基板60。压模化合物(或未填充部分)68可以用于保护芯片30和锡球66，其中，压模化合物68可以接触芯片30的背面，并且可以被填充到芯片30与封装基板60之间的空间中。
在上述实施例中，三次光刻胶填充和烘培处理被用作解释这些实施例的构思的实例。在可选的实施例中，根据翘曲度WAP1(图4A)的值和/或光刻胶的类型，多步骤填充处理可以仅包括两次光刻胶填充和烘培处理、或者多于三次的光刻胶填充和烘培处理。有利地，通过使用多步骤填充和烘培处理，光刻胶50、52和54中的每一个的厚度都不是过大的，因此，在光刻胶中不太可能产生气泡。在又一个实施例中，如果深度D(图4A)小，则仅使用一次光刻胶填充和烘培步骤。另外，在晶片100基本上是平坦时，以及/或者在光刻胶填充和烘培处理完成时，光刻胶可以基本上完全填充沟槽44(图5A)，或者仅部分地填充沟槽44。
本发明的实施例不限于光刻胶的填充。在可选实施例中，在硬化或退火/烘培时可以收缩的其他有机材料(诸如，聚酰亚胺、树脂等)也可以用于实现翘曲度补偿效应。
本发明的实施例具有一些有利的特征。由于沟槽形成在芯片的背面上，所以其可以在不适于在芯片的顶面上形成应力补偿涂层的情况下使用。另外，可以调节沟槽的图案，使得它们与现有图案以及/或者必须形成在芯片30的背面上的器件隔离，因此，本发明的实施例的使用不受关于芯片的背面的调节的影响。
尽管已详细描述了本发明及其优点，但是应该理解，在不背离由所附权利要求所限定的本发明的精神和范围的情况下，在本文中，可以进行各种变化、替换和变更。此外，本申请的范围并不旨在限于在本说明书中所描述处理、机器、产品以及物质、手段、方法和步骤的结合的特定实施例。本领域的普通技术人员从本发明的公开很容易想到，根据本发明，可以利用处理、机器、产品和现有或后来开发的物质、手段、方法或步骤(其执行基本上相同的功能或者实现基本上与 本文中所描述的对应实施例相同的结果)的结合。因此，所附的权利要求旨在包括在其范围内，诸如处理、机器、产品、以及物质、手段、方法或步骤的结合。另外，每项权利要求构成单独的实施例，并且各项权利要求和实施例的结合均在本发明的范围内。

Claims (15)

1.一种形成集成电路结构的方法，所述方法包括：
提供包括正面和背面的晶片，其中，所述晶片包括芯片；
形成从所述背面延伸到所述芯片的开口；
将有机材料填充到所述开口中，其中，所述有机材料基本上都不在所述开口的外部，而是在所述晶片的背面上；以及
对所述有机材料进行烘培，以使所述有机材料收缩。
2.根据权利要求1所述的方法，还包括将所述晶片分离成包括所述芯片的多个芯片，其中，在所述分离步骤之后，所述有机材料仍然在所述开口中。
3.根据权利要求2所述的方法，还包括将所述芯片封装在封装基板上。
4.根据权利要求1所述的方法，其中，所述有机材料包括光刻胶。
5.根据权利要求1所述的方法，其中，填充所述有机材料和烘培所述有机材料的步骤包括：
将第一层所述有机材料填充到所述开口中，其中，所述有机材料基本上都不在所述开口的外部；
对所述第一层的所述有机材料进行烘培；
将第二层所述有机材料填充到所述开口中并且在所述第一层所述有机材料之上，其中，所述第二层所述有机材料基本上都不在所述开口的外部；以及
对所述第二层所述有机材料进行烘培。
6.根据权利要求1所述的方法，还包括：
当执行形成所述开口的步骤时，同时形成多个开口；以及
当执行将所述有机材料填充到所述开口中的步骤时，同时将所述有机材料填充到所述多个开口中。
7.根据权利要求6所述的方法，其中，所述多个开口包括基本上对称于所述芯片的中心的分离沟槽。
8.根据权利要求1所述的方法，其中，所述开口具有大于约10μm的深度。
9.根据权利要求1所述的方法，其中，所述开口形成闭环环。
10.一种形成集成电路结构的方法，所述方法包括：
提供包括正面和背面的晶片，其中，所述晶片包括芯片；
形成从所述背面延伸到所述芯片的多个沟槽；
将第一光刻胶填充在所述多个沟槽中；
去除所述第一光刻胶在所述多个沟槽外部的部分；以及
对所述第一光刻胶进行烘培。
11.根据权利要求10所述的方法，还包括：
将第二光刻胶填充在所述多个沟槽中并且在所述第一光刻胶之上；
去除所述第二光刻胶在所述沟槽外部的部分；以及
对所述第二光刻胶进行烘培。
12.根据权利要求10所述的方法，还包括：重复从填充所述第一光刻胶的步骤到对所述第一光刻胶进行烘培的步骤的这些步骤，直到所述晶片的翘曲基本上完全被补偿并且所述晶片基本上是平坦的。
13.根据权利要求10所述的方法，其中，所述多个沟槽基本上对称于所述芯片的中心。
14.根据权利要求10所述的方法，其中，所述多个沟槽包括形成闭环沟槽环的沟槽。
15.根据权利要求10所述的方法，还包括：将所述芯片封装到封装基板上，其中，在所述封装步骤之后，所述第一光刻胶在所述多个沟槽中。
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