CN1019238B - Method for mode conversion of dual-port memory device - Google Patents
Method for mode conversion of dual-port memory deviceInfo
- Publication number
- CN1019238B CN1019238B CN90104906A CN90104906A CN1019238B CN 1019238 B CN1019238 B CN 1019238B CN 90104906 A CN90104906 A CN 90104906A CN 90104906 A CN90104906 A CN 90104906A CN 1019238 B CN1019238 B CN 1019238B
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- CN
- China
- Prior art keywords
- port
- mode
- transmission
- sam
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 5
- 238000012360 testing method Methods 0.000 claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims description 112
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
- 230000004304 visual acuity Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/32—Serial access; Scan testing
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Transceivers (AREA)
Abstract
A method for mode conversion of a dual-port memory device including a RAM(random access) port and a SAM (serial access) port. The SAM port can be converted from a serial write mode SW to a serial read mode SR by a pseudo read transfer mode PRT without data transfer between the ports, to enable testing of the SAM port by comparing original data with data read out from the SAM port. The RAM port and the SAM port can be tested easily as to whether or not they are normal in the wafer state in mass production of the dual-port memory device.
Description
The present invention relates to a kind of mode conversion method of not only including random access storage (RAM) port but also including the dual-port memory device of serial access storage (SAM) port of being used for, particularly a kind of being used for carries out data transmission and is used for reaching at random the mode switch of serial access test at the video random access memory (RAM) (VRAM) that includes ram port and sam port.
Previously the VRAM that is used for the image demonstration has the ram port of 64K * 1 and the sam port of 256K * 1.Afterwards, developed the 256KVRAM that includes 64K * 4 access ports again.From this time, the function by improvement 64K * 1VRAM is added on the VRAM writing every bit (Write-per-bit) and real-time Data Transmission function, thereby has formed the standard type of a kind of VRAM.With the integrated level of present 1M bit, VRAM has 256K * 4 and 128K * 8 two type.On the other hand, in the VRAM of routine, when data when processor reaches peripherals, these data at first will be transferred to memory, in memory these data are carried out access then.In this case, because access is by the peripherals execution, so processor just can not be given memory with this data transmission.But in this VRAM, when processor transferred data to memory by first port, this memory can carry out access by second port simultaneously.
This relation will 1 be described with reference to the accompanying drawings.
Fig. 1 shows a VRAM10 who contains ram port 1 and sam port 2.Ram port 1 is connected to sam port 2 by data transmission gating DTG.When the 1 second port P2 that is connected to screen display device was used to serial access, the first port P1 that is connected to the VRAM10 of processor then was used for random access.In addition, an end of ram port 1 is connected to the first port P1 by column decoder 4, and the other end of ram port 1 is connected to the row decoder (not shown in figure 1), label 5 expression control sections.Have a minimum access time owing to be used for the sam port 2 of serial access, thereby VRAM10 is widely used in high resolving power or the high speed display system.
In VRAM10, in reading transmission cycle, the data in the ram port 1 are written to sam port 2, and in sam port 2 the data readout mode are set.Similarly, in writing transmission cycle, the data in the sam port 2 are written to ram port 1, and write pattern PWT write-ining data mode is set by writing transmission cycle and puppet.In sam port 2, be switched to from write data mode in the cycle of reading pattern, read transmission cycle and must offer sam port 2, like this by bypass and with the data in the ram port 1, when after sam port 2 writes data, sam port 2 just can not directly be carried out read operation.Therefore, under the situation of producing VRAM in enormous quantities, owing to sam port is to rely on ram port to carry out the read and write operation, thereby the test of sam port itself also is impossible.
The objective of the invention is to provide a kind of mode converting method that is used for dual-port memory device.Utilize this method, make that under the situation of VRAM test, sam port can not rely on ram port and carry out the read and write operation independently.
Purpose of the present invention can be by under the situation of testing SA M, carries out a puppet when serial is write Mode S W and is converted to series read-out Mode S R and reads in transmission mode PRT, thereby forbid this data transmission is realized to ram port.
According to the present invention, a kind of mode converting method that is used to comprise the dual-port memory device of ram port and sam port is provided, this method comprises: carry out one and read transmission cycle, in this cycle, the data of ram port are transferred to sam port to read transmission mode or to read transmission mode in real time, and the data in the sam port are transmitted with the series read-out pattern; Carry out one and write transmission cycle, in this cycle, the data of an external unit are write pattern by this external unit with serial and directly store sam port, and the data in the sam port are transferred to ram port to write transmission mode; Carry out a puppet and write transmission mode, this pattern does not carry out data transmission between the transmission cycle and converts serial to writing pattern reading transmission cycle and write; With carry out a puppet and read transmission mode, this pattern is not carried out data transmission between the transmission cycle and the defeated series read-out pattern that changes into reading transmission cycle and write.
These and other purpose, characteristic and advantage of the present invention will become more obvious by described most preferred embodiment with reference to the accompanying drawings.
Fig. 1 shows the block scheme of conventional VRAM structure;
Fig. 2 shows the sequential chart of each mode of operation of sam port in this VRAM;
Fig. 3 shows the mode switch process flow diagram of SAM working condition in the dual-port memory device of routine;
Fig. 4 shows the mode switch process flow diagram according to the SAM of showing duty of the present invention.
Below, in conjunction with the accompanying drawings the present invention is made a more detailed description.
The course of work of VRAM10 is described referring to Fig. 1.The ram port 1 of VRAM10 is connected on the processor (not shown) by the first port P1, and the sam port 2 of VRAM10 is connected on the display device 3 by the second port P2.The data of from processor by column decoder 4 ' and the row decoder (not shown) be stored in randomly in the ram port 1.Being stored in data in the ram port 1 is transferred to by single file parts (one row unit) and is in the sam port 2 of reading transmission mode RT.At this moment, these data are transferred to sam port 2 by a data transmission gating DTG.Sam port 2 has and the corresponding serial register of ram port 1 single file parts, and like this, the single file parts just can receive or provide in turn these data.
In series read-out Mode S R, the data that are stored in sam port 2 are displayed on the display device 3 by the second port P2.In addition, utilize input media (for example a write device etc.) directly by sam port 2 with data under the situation of ram port 1 storage, sam port 2 at first is converted into puppet and writes transmission mode PWT and do not carry out data transmission and convert serial to and write Mode S W.Thereby these data are written into sam port P2 by the second port P2.And then in writing transmission mode WT, the data that are stored in sam port 2 are transferred to ram port 1, and at this moment, data are transmitted by data transmission gating DTG.
In this VRAM, the mode of operation of sam port is:
Read transmission mode RT
Read transmission mode RRT in real time
Series read-out Mode S R
Serial writes Mode S W
Write transmission mode WT
Puppet writes transmission mode PWT
Only, between ram port and sam port, just can carry out data communication in each transmission mode with when being provided with series read-out Mode S R or serial and writing Mode S W.In other series read-out Mode S R or serial when writing Mode S W, the work of sam port does not rely on ram port, particularly writing under the situation of transmission mode PWT in puppet, only is to become serial to write Mode S W this mode switch at ram port with not the carrying out data transmission of SAM end.The work of SAM is the correction by 6 kinds of patterns, carries out promptly that mode switch shown in Figure 3 realizes.In Fig. 3, mode switch only is to carry out according to the direction shown in the arrow.
Every kind of pattern has following function:
(1) reads transmission mode RT
This pattern is the serial register of giving sam port from the data transmission of ram port single file parts.At this moment, the last rising edge of serial clock signal SC (rising edge) must be ahead of effective edge (active edge) of rwo address strobe signals RAS.Carried out read transmission mode RT after, series read-out Mode S R is set to be used for sense data serially.Fig. 2 (a) has represented to be in the sequential chart when reading transmission mode RT.
In Fig. 2, RAS is the row address strobe signal, and CAS is the column address strobe signal, and A0-A8 is an address signal, and SIO1-SJO4 is an input/output signal.In addition, DT/OE is the clock signal of control data transmission and ram port output, and SC is the clock signal that is used for serial access (read/write), and SE is that serial enables clock signal.
(2) read transmission mode RRT in real time
This pattern is used for handling continuously its length flowing greater than the data of serial register length.The last clock that only is signal SC and signal DT/OE with the difference of reading transmission mode RT must be synchronized with each other.In addition, signal DT/OE must be synchronous with signal RAS and CAS.This pattern can be carried out real time access and data transmission simultaneously.Fig. 2 (b) shows the sequential chart of this pattern.
(3) series read-out Mode S R
This pattern be used to utilization read transmission mode RT or read transmission mode RRT in real time sam port is placed this pattern after, read these data according to signal SC fast from serial register.Fig. 2 (c) shows the sequential chart of this pattern.
(4) serial writes Mode S W
This pattern is used for writing continuous data apace to the serial register of sam port.Owing to be by external definition, this pattern and series read-out Mode S R are as broad as long.Since this pattern write transmission mode or pseudo-write transmission mode PWT after setting, carry out so the serial write operation is the timing identical with signal SC.The sequential chart of this pattern is shown in Fig. 2 (d).
(5) write transmission mode WT
This pattern is used for will utilizing serial to write Mode S W by the single file parts and is stored in the data transmission of serial register to ram port.In addition, after this pattern, SAM is placed in serial and writes Mode S W.The sequential chart of this pattern is shown in Fig. 2 (e).
(b) puppet writes transmission mode PWT
After data are write serial register, these data are transferred to ram port from sam port by writing transmission mode WT.Write Mode S W in order to carry out serial after series read-out Mode S R, then sam port must be placed in serial and write Mode S W.This is not write transmission mode WT because if place serial just to carry out before writing Mode S W as yet at sam port, and then Cuo Wu data will be transferred to ram port.Therefore, during writing Mode S W, serial do not allow these data are transferred to ram port from sam port being transformed into from series read-out Mode S R.Puppet writes transmission mode PWT and is used to not write Mode S W having under the situation of data transmission series read-out Mode S R to be converted to serial.The sequential chart of this pattern is shown in Fig. 2 (f).The work of sam port shown in Figure 3 is carried out in turn by above-mentioned six kinds of patterns.
Fig. 3 shows the model process figure of working condition of the sam port of conventional dual-port memory device.In Fig. 3, have and read transmission cycle 6, write transmission cycle 7 and write transmission cycle pattern PWT in the puppet of reading transmission cycle 6 and write between the transmission cycle 7.Have only when at first finishing and read transmission or read when operation transmission in real time, could carry out series read-out Mode S R.In this VRAM, read transmission mode RT or read a pattern among the transmission mode RRT in real time by the hardware configuration initial selected.Because, will utilize to be in the single file parts reading transmission mode RT or read transmission mode RRT in real time and to give the sam port serial register with the data transmission in the ram port for data are transferred to sam port from ram port.The data that are stored in the serial register are read fast with series read-out Mode S R, and are transferred to display device.
On the other hand, for data are directly stored sam port from external unit, serial at first must be set write Mode S W.That is to say, write Mode S W in order to be transformed into serial from series read-out Mode S R, just must carry out a puppet writes transmission mode PWT.Write among the transmission mode PWT in this puppet, do not carry out data transmission.Write among the Mode S W in serial, directly store sam port by the data that external unit applies.In addition, in order to read the data that are stored in sam port once more, this pattern must be converted into series read-out Mode S R, but as shown in Figure 3, this pattern can not directly write Mode S W from serial and convert series read-out Mode S R to.Therefore, when this pattern write from serial Mode S W convert to write transmission mode WT after, the data in the sam port serial register are transferred to and are in the ram port that writes transmission mode WT.For the data that are stored in the ram port are transferred to sam port once more, by read transmission mode RT data-storing after sam port, these data that are stored in sam port are read out with series read-out Mode S R.Therefore, under the SAM test case, just must carry out and read the above-mentioned SAM test of transmission mode RT(is by comparing to check whether this sam port is normal to raw data with from the data that sam port is read), between ram port and sam port, just always exist data communication like this, thereby only just do not needed at the test of SAM.
Fig. 4 is a mode switch process flow diagram, and it shows the working condition according to the SAM in the dual-port memory device of the present invention.In Fig. 4, read transmission cycle 6 and write transmission cycle 7 same as shown in Figure 3.In addition, puppet is read transmission mode PRT and puppet and is write transmission mode PWT and be inserted in and read transmission cycle 6 and write between the transmission cycle 7.Read transmission cycle 6 and write the groundwork situation of transmission cycle 7 same as shown in Figure 3, and be used for being transformed into the puppet that writes transmission cycle 7 to write transmission mode also same as shown in Figure 3 reading transmission cycle 6.
But, according to the present invention, as shown in Figure 4, when SAM tests, when raw data is compared with the data of reading from sam port, read transmission mode PRT by puppet and do not carry out data transmission and also can make sam port write Mode S W to convert series read-out Mode S R to from serial.That is to say that if from external unit data-storing is carried out puppet later on and read transmission mode PRT to being in sam port that serial writes Mode S W, then SAM just can not have to convert series read-out Mode S R under the situation of data transmission to.Afterwards, the data that are stored in the sam port are read out for comparing with raw data, so just can check whether sam port is normal.
Above-mentioned working condition is explained with reference to figure 1.After producing VRAM in a large number, when wafer state, just ram port among the VRAM and sam port are tested to check whether it is normal by semiconductor fabrication process.Its ram test is identical with conventional ram test.For the SAM on the manufacturing process of a large amount of production VRAM is tested, disposed several solder joints that only when wafer state, use, form one the 3rd port.In addition, being used for writing puppet that Mode S W converts series read-out Mode S R to from serial reads transmission mode PRT and is carried out by the control clock signal of control section 5.When VRAM is fabricated in when testing on this wafer and to sam port, at first carry out the serial that writes in the transmission cycle 7 and write Mode S W.At this moment, test data is stored sam port 2 by the second port P2, and read transmission mode PRT by providing a control clock signal to carry out puppet, thereby the data that are stored in sam port 2 are offered the second port P2 from the control section 5 that contains the 3rd port P3.After this, not carrying out data transmission between sam port and ram port just can make sam port convert series read-out Mode S R to.The data that are stored in sam port are read with the series read-out pattern, and compare to check whether sam port is normal with raw data.
So far described, according to the present invention, under a large amount of situations of producing the dual-port memory device with ram port and sam port, whether SAM end and sam port be normal during the testing wafer state easily.Particularly, according to the present invention, needn't carry out data transmission because sam port can only write transmission mode PWT by puppet and write Mode S W from serial and convert series read-out Mode S R to, thereby make under the situation of SAM test, can be very easy to whether test it simply normal.
The present invention is not limited to the foregoing description.On the basis of reference the present invention narration, for this professional those of ordinary skill, the various modifications of other embodiments of the invention and described embodiment all are clearly.Therefore, can give the phase, additional claims all will cover any this modification or the embodiment in the scope of the invention.
Claims (3)
1, a kind of mode conversion method of dual-port memory device of the control section that is used to include ram port, sam port and generation control signal, this method comprises:
Carry out one and read transmission cycle, in this cycle, the data in the ram port are transferred to sam port to read transmission mode and to read transmission mode in real time, and the data in the sam port are read with the series read-out pattern;
Carry out one and write transmission cycle, in this cycle, the data of external unit write pattern with serial and directly store sam port from external unit, and the data in the sam port are transferred to ram port to write transmission mode;
Carry out a puppet and write transmission mode, this pattern is not carried out data transmission and just is convertible into serial and writes pattern reading transmission cycle and write between the transmission cycle; With
Carry out a puppet and read transmission mode, this pattern is not carried out data transmission and just is convertible into the series read-out pattern reading transmission cycle and write between the transmission.
2, the method for claim 1, wherein, being used for not carrying out data transmission between ram port and sam port just can write puppet that mode switch becomes the serial readout mode to serial to read transmission mode be to be carried out by the fixed control signal of giving from the control part.
3, the method for claim 1, wherein be used for not carrying out data transmission and just can write puppet that mode switch becomes the serial readout mode to serial and read transmission mode and realize by increase some solder joints on wafer between ram port and sam port, described solder joint receives one and decides signal in order to giving of test VRAM device.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR6350/90 | 1990-05-04 | ||
| KR1019900006350A KR920003269B1 (en) | 1990-05-04 | 1990-05-04 | Mode transfer method in dual port memory system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1056361A CN1056361A (en) | 1991-11-20 |
| CN1019238B true CN1019238B (en) | 1992-11-25 |
Family
ID=19298718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN90104906A Expired CN1019238B (en) | 1990-05-04 | 1990-06-25 | Method for mode conversion of dual-port memory device |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPH073747B2 (en) |
| KR (1) | KR920003269B1 (en) |
| CN (1) | CN1019238B (en) |
| DE (1) | DE4021600C2 (en) |
| FR (1) | FR2661770B1 (en) |
| GB (1) | GB2243700B (en) |
| IT (1) | IT1248855B (en) |
| NL (1) | NL194899C (en) |
| RU (1) | RU2109330C1 (en) |
| SE (1) | SE512454C2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1067477C (en) * | 1996-04-16 | 2001-06-20 | 联华电子股份有限公司 | Signal transmitting device between chip assemblies by series codes |
| KR100773063B1 (en) * | 2006-09-12 | 2007-11-19 | 엠텍비젼 주식회사 | Dual port memory device, memory device and method of operating the dual port memory device |
| KR100773065B1 (en) * | 2006-09-12 | 2007-11-19 | 엠텍비젼 주식회사 | Dual port memory device, memory device and method of operating the dual port memory device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5589980A (en) * | 1978-11-27 | 1980-07-08 | Nec Corp | Semiconductor memory unit |
| US4703449A (en) * | 1983-02-28 | 1987-10-27 | Data Translation Inc. | Interrupt driven multi-buffer DMA circuit for enabling continuous sequential data transfers |
| SU1298754A1 (en) * | 1985-03-12 | 1987-03-23 | Войсковая часть 03080 | Device for controlling internal memory allocation |
| SU1348860A1 (en) * | 1986-06-25 | 1987-10-30 | Харьковский Институт Радиоэлектроники Им.Акад.М.К.Янгеля | Device for controlling video information memory |
| JPH073757B2 (en) * | 1987-02-25 | 1995-01-18 | 三菱電機株式会社 | Semiconductor memory device |
| US4817058A (en) * | 1987-05-21 | 1989-03-28 | Texas Instruments Incorporated | Multiple input/output read/write memory having a multiple-cycle write mask |
| JPH0760594B2 (en) * | 1987-06-25 | 1995-06-28 | 富士通株式会社 | Semiconductor memory device |
| JP2793184B2 (en) * | 1987-07-27 | 1998-09-03 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor storage device |
-
1990
- 1990-05-04 KR KR1019900006350A patent/KR920003269B1/en not_active IP Right Cessation
- 1990-06-15 SE SE9002149A patent/SE512454C2/en unknown
- 1990-06-15 IT IT02065090A patent/IT1248855B/en active IP Right Grant
- 1990-06-22 RU SU4830360A patent/RU2109330C1/en not_active IP Right Cessation
- 1990-06-25 CN CN90104906A patent/CN1019238B/en not_active Expired
- 1990-06-25 GB GB9014079A patent/GB2243700B/en not_active Expired - Fee Related
- 1990-07-06 DE DE4021600A patent/DE4021600C2/en not_active Expired - Fee Related
- 1990-07-16 NL NL9001613A patent/NL194899C/en not_active IP Right Cessation
- 1990-07-20 FR FR9009334A patent/FR2661770B1/en not_active Expired - Fee Related
- 1990-07-23 JP JP2194692A patent/JPH073747B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE4021600C2 (en) | 1994-04-07 |
| CN1056361A (en) | 1991-11-20 |
| JPH073747B2 (en) | 1995-01-18 |
| IT9020650A1 (en) | 1991-12-15 |
| NL194899B (en) | 2003-02-03 |
| SE512454C2 (en) | 2000-03-20 |
| SE9002149D0 (en) | 1990-06-15 |
| FR2661770B1 (en) | 1994-01-28 |
| KR920003269B1 (en) | 1992-04-27 |
| GB2243700B (en) | 1994-02-02 |
| GB9014079D0 (en) | 1990-08-15 |
| IT1248855B (en) | 1995-01-30 |
| KR910020557A (en) | 1991-12-20 |
| DE4021600A1 (en) | 1991-11-07 |
| GB2243700A (en) | 1991-11-06 |
| IT9020650A0 (en) | 1990-06-15 |
| NL9001613A (en) | 1991-12-02 |
| FR2661770A1 (en) | 1991-11-08 |
| SE9002149L (en) | 1991-11-05 |
| RU2109330C1 (en) | 1998-04-20 |
| NL194899C (en) | 2003-06-04 |
| JPH0414695A (en) | 1992-01-20 |
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| C15 | Extension of patent right duration from 15 to 20 years for appl. with date before 31.12.1992 and still valid on 11.12.2001 (patent law change 1993) | ||
| OR01 | Other related matters | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 19930901 |