KR100773065B1 - Dual port memory device, memory device and method of operating the dual port memory device - Google Patents

Abstract

A dual port memory device, a memory device and a method of operating the dual port memory device are provided to be used by being connected to a processor having an SRAM external interface and a processor having an SDRAM external interface without changing a logic circuit of the prior SDRAM interface, by adding a block converting an address and a control signal following an SRAM interface into an address and a control signal following an SDRAM interface to the logic circuit of the prior SDRAM interface. A dual port memory device includes a memory array(160), a signal converter(110), a first memory interface(150) and a second memory interface(170). The signal converter converts an address and a control signal following a first memory interface inputted through a first port into an address and a control signal following a second memory interface. The first memory interface performs a read or write operation of the memory array on the basis of the converted address and control signal following the second memory interface. The second memory interface performs the read or write operation of the memory array on the basis of the address and the control signal following the second memory interface inputted through a second port.

Description

DUAL PORT MEMORY DEVICE, MEMORY DEVICE AND METHOD OF OPERATING THE DUAL PORT MEMORY DEVICE}

1 is a conceptual diagram illustrating a dual port memory device used in a processor A having a conventional SDRAM External Bus Interface (EBI) and a processor B having an SDRAM External Bus Interface (EBI).

FIG. 2 is a conceptual diagram illustrating a dual port memory device used in processor A having a conventional SRAM external bus interface (EBI) and processor B having an SRAM external bus interface (EBI).

3 is a block diagram illustrating a state in which dual port SDRAM is connected to a processor having a PSRAM (or SRAM) external interface bus and a processor having an SDRAM external interface bus according to an embodiment of the present invention.

4 is a block diagram illustrating a signal converter of FIG. 3.

5 is a timing diagram illustrating read and write operations of a dual port SDRAM according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: dual port memory device 110: signal converter

150: first SDRAM interface 160: DRAM memory array

170: second SDRAM interface

The present invention relates to a dual port memory device, and more particularly, to a dual port memory device, a memory device and a method of operating a dual port memory device applicable to a portable terminal.

Various processors such as a baseband processor, a video processor, and a multimedia processor used in a portable terminal such as a mobile phone have an SRAM external interface (or PSRAM external interface) and an SDRAM external interface.

Dual port memory is widely used in processors having the SRAM external interface (or PSRAM external interface) and the SDRAM external interface.

The dual port memory has two input / output ports, in which the first processor accesses data through the first port and the second processor accesses data through the second port, thereby accessing data through the two ports. Is possible.

Dual-port memory is often used when two processors are connected to different memory, each of which sends and receives data through an external printed circuit board (PCB) line through a host-processor interface. Data transfer speeds are faster and overall system performance can be improved. In addition, the use of dual port memory can reduce one memory in terms of mounting area.

1 and 2 are conceptual views illustrating dual port memory used in two processors accessing a memory having a memory cell structure of the same type. Specifically, FIG. 1 is a conceptual diagram illustrating dual port memory used in Processor A having a conventional SDRAM External Bus Interface (EBI) and Processor B having an SDRAM External Bus Interface (EBI), and FIG. 2 is a conventional SRAM. A conceptual diagram showing dual port memory used in processor A with an external bus interface (EBI) and processor B with an SRAM external bus interface (EBI). Here, the external bus interface EBI serves as a kind of memory controller.

As illustrated in FIGS. 1 and 2, dual port memory having two ports may be used for two processors that access memory having the same type of memory cell structure. That is, in FIG. 1, a dual port memory having a memory cell array made of DRAM may be connected to two processors having an SDRAM external bus interface (EBI). In addition, in FIG. 2, a dual port memory including an SRAM memory cell array may be connected to two processors having an SRAM external bus interface (EBI).

However, it is difficult to use dual port memory because the unit memory cell structure is different between two processors having an external bus interface (EBI) for different types of memories.

Synchronous Dynamic RAM (SDRAM) is a volatile memory that performs periodic refreshes and periodically fills a capacitor to store data, and has a unit memory cell structure of one transistor and one capacitor of DRAM.

Static random access memory (SRAM) is a volatile memory whose data is lost when the power is turned off. The data stored in the memory cell is maintained while the power is present even if the power is not refreshed. A unit memory cell of an SRAM generally has a structure consisting of four transistors having a latch structure and two transistors having a transfer gate structure, for a total of six transistors. Since data is stored in a unit memory cell of a latch structure, a refresh operation for storing data is not required. Since the unit memory cell of the SRAM is implemented with six transistors, the unit memory cell of the SRAM has a disadvantage in terms of the layout area required compared to the unit memory cell of the DRAM having one transistor and one capacitor.

While PSRAM (Pseudo SRAM) uses the same interface as SRAM, the unit memory cell structure has a unit memory cell structure of DRAM, that is, a structure of one transistor and one capacitor, and includes a refresh circuit.

Due to many limitations in the semiconductor memory manufacturing process, it is difficult to form both SRAM memory cells and DRAM memory cells having different memory cell structures as described above in the memory cell array region on the dual port memory.

That is, when processor A has an SRAM external bus interface (EBI) and processor B has an SDRAM external bus interface (EBI), a dual port memory in which both an SRAM memory cell and a DRAM memory cell are formed in a memory cell array region may not be manufactured. It is difficult because of many limitations in the semiconductor memory manufacturing process.

In addition, when both the SRAM memory cell and the DRAM memory cell are formed in the memory cell array region on the dual port memory, the SRAM memory cell is composed of six transistors, resulting in a large die size, thereby increasing manufacturing costs.

Therefore, it is common to implement a memory array of a conventional dual port memory using only one type of memory cell structure of SRAM or DRAM. In this case, the use of DRAM is more efficient in terms of layout area than using SRAM as a memory array of dual port memory.

Increasingly, when more processors are used in one portable terminal, dual port memory is required that can be used between processors with different memory interfaces.

In particular, in a portable terminal such as a mobile phone, there is a need for a dual port memory having a DRAM memory cell structure for use in a processor having such an SRAM external interface (or a PSRAM external interface) and a processor having an SDRAM external interface.

Accordingly, a first object of the present invention is to provide a dual port memory device that can be used in a processor having different types of memory interfaces.

It is also a second object of the present invention to provide a memory device that can be used in a processor having different types of memory interfaces.

It is also a third object of the present invention to provide a dual port memory operating method that can be used in a processor having different types of memory interfaces.

A dual port memory device according to an aspect of the present invention for achieving the first object of the present invention is a memory array; A signal conversion unit converting an address and a control signal along the first type memory interface input through the first port into an address and a control signal along the second type memory interface; A first memory interface unit configured to perform a read or write operation on the memory array based on the converted address and a control signal along the second type memory interface; And a second memory interface unit configured to perform a read or write operation on the memory array based on an address and a control signal along the second type memory interface input through a second port. The first method memory interface may be a PSRAM interface, and the second method memory interface may be an SDRAM interface. The signal converter may separate an address along the first memory interface input through the first port into a row address, a column address, and a bank address along the second type memory interface. The signal converter may include: a row address extractor configured to extract a row address along the second method memory interface from an address along the first method memory interface input through the first port; A column address extracting unit configured to extract a column address along the second method memory interface from an address along the first method memory interface input through the first port; And a bank address extractor configured to extract a bank address along the second method memory interface from an address along the first method memory interface input through the first port. The signal converter may include a converter configured to receive a control signal input through the first port and to generate timing information for performing a read, write, and refresh operation along the second type memory interface; And a command controller configured to receive the timing information and generate a control signal for performing a read, write, and refresh operation along the second type memory interface. The memory array may have a DRAM cell structure.

Memory device according to an aspect of the present invention for achieving the second object of the present invention comprises a memory array; A signal conversion unit converting an address and a control signal along the first type memory interface input through the first port into an address and a control signal along the second type memory interface; And a memory interface unit configured to perform a read or write operation on the memory array based on the converted address and the control signal along the second type memory interface. The first method memory interface may be a PSRAM interface, and the second method memory interface may be an SDRAM interface. The signal converter may separate an address along the first type memory interface input through the first port into a row address, a column address, and a bank address along the second type memory interface.

According to an aspect of the present invention, there is provided a method of operating a dual port memory device, the method including: address and control signals following a first type memory interface input through a first port; Converting to an address and control signal; And performing a read or write operation on the memory array based on the converted address and the control signal along the second scheme memory interface.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

In describing the drawings, similar reference numerals are used for similar components.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

3 is a block diagram illustrating a state in which a dual port SDRAM is connected to a processor having a PSRAM (or SRAM) external interface bus and a processor having an SDRAM external interface bus according to an embodiment of the present invention. 4 is a block diagram illustrating a signal converter of FIG. 3. The dual port SDRAM 100 has a unit memory cell structure of DRAM.

The dual port SDRAM 100 is connected to the processor A 50 having the PSRAM (or SRAM) external interface bus (EBI) 52 through the A port to receive the address 51, the control signal 53 and the data 59. After converting the address 141, the control signal 143, the clock 145, and the data 147 according to the operation timing of the SDRAM, the SDRAM memory array 160 is accessed through the first SDRAM interface 150.

The control signal 53 is, for example, a chip select signal / CS (Chip Select) in accordance with the operation timing of the PSRAM (or SRAM), the write enable signal / WE (Write Enable) and the output enable signal / OE (Output Enable). ) May be included. The control signal 143 includes / CS, a low strobe signal / RAS (Row Address Strobe), a column strobe signal / CAS (Column Address Strobe) and / WE for performing operations such as reading, writing, and refreshing the SDRAM. can do.

The dual port SDRAM 100 exchanges data with the processor B 60 having the SDRAM external interface (EBI) 62 through the B port. Processor B 60 having an SDRAM external interface bus 62 is provided with an address 61 and a plurality of control signals via a plurality of address pins, a plurality of control signal pins and a plurality of data pins of the dual port SDRAM 100. 63), and the dual port SDRAM 100 inputs and outputs data 69 through the B port using the second SDRAM interface 170.

Referring to FIG. 3, the dual port SDRAM 100 according to an embodiment of the present invention may include a signal converter 110, a first SDRAM interface 150, a DRAM memory array 160, and a second SDRAM interface 170. It includes.

The signal converting unit 110 includes the address 51 and the plurality of addresses through the processor A 50 having the PSRAM (or SRAM) external interface bus 52 and the plurality of address pins, the plurality of control signal pins, and the plurality of data pins. The control signals 53 are input and input and output data 59.

The signal converter 110 converts the control signals 53 based on the PSRAM (or SRAM) interface into the control signal 143 based on the SDRAM interface. In detail, the signal converter 110 receives control signals 53 such as / CS, / WE, and / OE that follow the operation timing of the PSRAM (or SRAM), and performs operations such as reading, writing, and refreshing the SDRAM. Generate control signals 143 such as / CS, / RAS, / CAS, and / WE to perform. In addition, the signal converter 110 generates a clock signal 145 required for the SDRAM operation.

In addition, the signal converting unit 110 receives, for example, an N-bit address 51 from the processor A 50 having the PSRAM (or SRAM) external interface bus 52 and follows the address system of the SDRAM. And convert it to). For example, the address 141 may include a row address, a column address, and a bank address BA. The bank address may be, for example, one bit when the DRAM memory array 160 has two banks, or two bits when the DRAM memory array 160 has four banks. The SDRAM interface 150 of FIG. 3 may be provided for each bank indicated by each bank address.

In addition, the signal converter 110 reads, writes, and refreshes the SDRAM data input from the processor A 50 having the PSRAM (or SRAM) external interface bus 52 or data read from the DRAM memory array 160. The input / output timing of the data is adjusted so as to comply with the operation timing.

Hereinafter, the operation of the signal converter 110 will be described in detail with reference to FIG. 4.

Referring to FIG. 4, the signal converter 110 includes a row address extractor 111, a column address extractor 115, a refresh controller 113, a mux 116, a converter 117, and a command controller 119. And an input / output buffer 118. The signal converter 120 may further include a bank address extractor 114 when the DRAM memory array 160 includes a plurality of banks. Hereinafter, it will be assumed that the DRAM memory array 160 is composed of a plurality of banks.

The bank address extracting unit 114 extracts the bank address BA from the upper address among the addresses 51 input based on the bank address control signal S2.

The row address extracting unit 111 extracts a row address from an upper address among the addresses 51 input based on the row address control signal S3, and the column address extracting unit 115 transmits the column address control signal S4 to the column address control signal S4. The column address is extracted from the lower address among the addresses 51 input based on this. The mux 116 sequentially outputs the extracted row address and column address based on the mux control signal S5.

The refresh control unit 113 generates a clock timing signal and provides the clock timing signal to the command control unit 119, and the command control unit 119 may provide a clock (CLK, 145) to be provided to the first SDRAM interface 150 based on the clock timing signal. Create Alternatively, the refresh control unit 113 may generate a clock CLK 145 to be provided directly to the first SDRAM interface 150. The refresh control unit 113 may be implemented using an oscillator.

The converter 117 receives a control signal 53 -for example, / CS, / WE, and / OE- that conforms to the operation timing of the PSRAM (or SRAM), and timing information for reading, writing, and refreshing the SDRAM. (S1) is provided to the command control unit 119. In addition, the converter 117 uses the control signal 53 in accordance with the operation timing of the PSRAM (or SRAM) to extract the bank address 114, the row address extractor 111, the column address extractor 115, and the mux. 116, the bank address control signal S2, the row address control signal S3, the column address control signal S4, and the mux control signal for controlling the operation timing of the command control unit 119 and the input / output buffer 121 S5), the input / output buffer control signal S6 is generated.

The command control unit 119 receives the timing information S1 generated by the converter 117 and executes / CS, / RAS, / CAS, for performing row active, read, write, and refresh operations of the SDRAM. Generate control signals 143 such as / WE and clock enable (CKE).

The command controller 119 adjusts the operation timing so that the read / write operation and the refresh operation of the SDRAM do not collide with each other, thereby controlling control signals 143 such as / CS, / RAS, / CAS, / WE, and clock enable (CKE). Create

That is, / CS, / RAS, / CAS, and / WE are used to control the row active, read, write and write of SDRAM using control signals 53-/ CS, / WE, / OE- along the interface of PSRAM. The timing may be adjusted and generated to perform the refresh operation.

Specifically, / CS, / RAS, / CAS and / WE along the interface of the SDRAM is activated when / CS of the control signals 53 along the interface of the PSRAM is active and / WE is activated while the refresh operation is not performed. The signal levels (high and low) of / CS, / RAS, / CAS and / WE are adjusted to perform the write operation. That is, when / CS is activated and / WE is activated among the control signals 53 along the interface of PSRAM, in order to perform the write operation of the SDRAM, / CS along the interface of SDRAM is low and / WE is high. , / RAS generates a low and / CAS high state to activate the active command (row active) to activate a row line corresponding to a predetermined row address of the SDRAM occurs, Create a write command by activating a write command by creating a / CS low, / WE low, / RAS high and / CAS low along the SDRAM interface.

Specifically, / CS, / RAS, / CAS and / which follow the interface of SDRAM when / CS is activated and / OE is activated among control signals 53 that follow the interface of PSRAM while not performing the refresh operation. The signal levels (high and low) of / CS, / RAS, / CAS and / WE are adjusted to allow WE to perform read operations. That is, in order to perform a read operation of the SDRAM when / CS is activated and / OE is activated among the control signals 53 along the interface of the PSRAM, / CS along the interface of the SDRAM is low and / WE is high. , / RAS generates a low and / CAS high state to activate the active command (row active) to activate a row line corresponding to a predetermined row address of the SDRAM occurs In this case, read / write operations are performed by enabling / CS to be low, / WE to high, / RAS to high and / CAS to low along the SDRAM interface.

Although FIG. 6 illustrates an example in which the converter 117 and the command controller 119 are implemented as two separate blocks, the converter 117 and the command controller 119 may be implemented as one block, that is, a single finite state machine (FSM).

The input / output buffer 121 buffers the data 59 into an input buffer (not shown) under the control of the converter 117, and then outputs the data 59 to the first SDRAM interface 150 according to the timing of the SDRAM write operation. ) Is buffered in an output buffer (not shown) and then output according to the timing of the read operation of the SDRAM.

Referring back to FIG. 3, the first SDRAM interface 150 receives an address 141, a control signal 143, a clock 145, and data 147 from the signal conversion unit 110. To decode the row address and the column address to output the decoded address 151 to the DRAM memory array 160, and output the data 153 to the DRAM memory array 160 in accordance with an operation timing such as reading, writing, and refreshing the SDRAM. Input and output.

The first SDRAM interface 150 has a configuration of a general SDRAM interface, and includes a command decoder for receiving and decoding a control signal 143, a row decoder for decoding a row address, and a column address for decoding. A column decoder, a sense amplifier, and a refresh controller for controlling a refresh operation are included.

The second SDRAM interface 170 receives an address 61, control signals 63, and a clock 67 from the processor B 60 having the SDRAM external interface bus 62 through the port B, and receives the address 61. To decode the row address and the column address, output the decoded address 171 to the DRAM memory array 160, and output the data 173 to the DRAM memory array 160 according to an operation timing such as reading, writing, and refreshing the SDRAM. Input and output.

The second SDRAM interface 170 has a configuration of a general SDRAM interface, and includes a command decoder, a row decoder, a column decoder, a sense amplifier, and a refresh controller for receiving and decoding the control signal 63.

Therefore, the signal converter 110 is provided in front of the SDRAM interface 150 to generate an address and control signal along the SDRAM interface and provide the SDRAM interface 150 to the logic circuit of the SDRAM interface 150 of a general dual port memory. You can use as is without changing.

Although FIG. 3 illustrates a memory having dual ports, the present invention can also be applied to a memory device having a single port. Specifically, the present invention may be applied to a memory device including the signal converter 120, the memory interface 150, and the memory array 160 by removing the second memory interface 170 from the dual port memory device of FIG. 3. Can be.

5 is a timing diagram illustrating read and write operations of a dual port SDRAM according to an embodiment of the present invention. The clock signals CLK, / CS, / RAS, / CAS, and / WE of FIG. 5 are signals generated by the command controller 119 of FIG.

The dual port SDRAM 100 receives an address 51 and a control signal 53-for example, / CS, / WE and / OE-along the PSRAM (or SRAM) interface by the signal converter 110 of FIG. Address 141 and control signal 143 along the interface of the SDRAM are converted into, for example, / CS, / RAS, / CAS, CKE, / WE, etc., and then read according to the operation timing of the diary and write of the SDRAM. And write operation.

Referring to FIG. 5, data is read from or written to a dual port memory device in synchronization with a clock signal CLK. The clock enable signal CKE has a high state because it operates in synchronization with the clock signal. If / RAS, / CAS and / WE are all high, they are in NOP (no operation). When / CS is high, the command decoder is disabled so that / RAS, / CAS and / WE and address inputs are ignored. 5 illustrates read and write operations in a memory array corresponding to a bank indicated by a bank address.

First, the read operation is performed as follows. When / CS is low, / WE is high, and the low strobe signal (/ RAS) is low and the column strobe signal (/ CAS) is high, a row address is applied to the address pin to correspond to the row address of the memory array 160. If the low line is active (row active), / CS is low, / WE is high, low strobe signal (/ RAS) is high and column strobe signal (/ CAS) is low, then a read command is issued. The column address is applied to the address pin, and data is read through the column line corresponding to the column address of the memory array 160 after a predetermined delay time after the read command is issued. In FIG. 5, the case in which the delay time (CAS Latency) is 2 clocks is taken as an example.

Next, the write operation is performed as follows. When / CS is low, / WE is low, and the low strobe signal (/ RAS) is low and the column strobe signal (/ CAS) is high, a row address is applied to the address pin to correspond to the row address of the memory array 160. If a low line is active (row active), / CS is low, / WE is low, low strobe signal (/ RAS) is high, and column strobe signal (/ CAS) is low, a write command is issued. The column address is applied to the address pin, and data is written through the column line corresponding to the column address of the memory array 160.

According to the dual port memory device and the dual port memory device operating method as described above, there is provided a dual port memory device and a memory device that can be used by connecting to processors having different memory interfaces. Therefore, the dual port memory device of the present invention can be used when one portable terminal includes processors having a plurality of different memory interfaces.

In particular, in a portable terminal such as a mobile phone, the dual port memory device of the present invention converts an address and control signal following an SRAM interface (or a PSRAM interface) into a logic circuit of an existing SDRAM interface into an address and control signal along an SDRAM interface. By adding a block that can be used, it can be connected to a processor having an SRAM external interface (or a PSRAM external interface) and a processor having an SDRAM external interface without changing the logic circuit of the existing SDRAM interface.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (15)

Memory arrays; A signal conversion unit converting an address and a control signal along the first type memory interface input through the first port into an address and a control signal along the second type memory interface; A first memory interface unit configured to perform a read or write operation on the memory array based on the converted address and a control signal along the second type memory interface; And And a second memory interface unit configured to perform a read or write operation on the memory array based on an address and a control signal along the second type memory interface input through a second port. Claim 2 was abandoned when the setup registration fee was paid. The dual port memory device of claim 1, wherein the first type memory interface is a PSRAM interface and the second type memory interface is an SDRAM interface. The method of claim 2, wherein the signal conversion unit And dividing an address along the first method memory interface input through the first port into a row address, a column address, and a bank address along the second method memory interface. The method of claim 2, wherein the signal conversion unit A row address extracting unit configured to extract a row address along the second method memory interface from an address along the first method memory interface input through the first port; A column address extracting unit configured to extract a column address along the second method memory interface from an address along the first method memory interface input through the first port; And And a bank address extracting unit configured to extract a bank address along the second method memory interface from an address along the first method memory interface input through the first port. The method of claim 4, wherein the signal conversion unit A converter configured to receive a control signal input through the first port through the first port and generate timing information for performing a read, write, and refresh operation along the second type memory interface; And And a command controller configured to receive the timing information and generate a control signal for performing a read, write, and refresh operation along the second type memory interface. Claim 6 was abandoned when the registration fee was paid. The dual port memory device of claim 2, wherein the memory array has a DRAM cell structure. Memory arrays; A signal conversion unit converting an address and a control signal along the first type memory interface input through the first port into an address and a control signal along the second type memory interface; And And a memory interface unit configured to perform a read or write operation on the memory array based on the converted address and the control signal along the second type memory interface. Claim 8 was abandoned when the registration fee was paid. 8. The memory device of claim 7, wherein the first type memory interface is a PSRAM interface and the second type memory interface is an SDRAM interface. The method of claim 8, wherein the signal conversion unit And dividing an address along the first method memory interface input through the first port into a row address, a column address, and a bank address along the second method memory interface. Converting an address and control signal along the first way memory interface input through the first port into an address and control signal along the second way memory interface; And And performing a read or write operation on the memory array based on the converted address and control signals along the second type memory interface. The dual port memory device operation of claim 10, further comprising performing a read or write operation on the memory array based on an address and a control signal along the second type memory interface input through a second port. Way. Claim 12 was abandoned upon payment of a registration fee. The method of claim 10, wherein the first type memory interface is a PSRAM interface and the second type memory interface is an SDRAM interface. The method of claim 12, wherein the converting the address and control signals along the first method memory interface input through the first port into the address and control signals along the second method memory interface is performed. And dividing an address along the first method memory interface input through the first port into a row address, a column address, and a bank address along the second method memory interface. The method of claim 13, wherein the converting the address and control signals along the first method memory interface input through the first port into the address and control signals along the second method memory interface comprises: Extracting a row address along the second manner memory interface from an address along the first manner memory interface input through the first port; Extracting a column address along the second manner memory interface from an address along the first manner memory interface input through the first port; And Extracting a bank address along the second way memory interface from an address along the first way memory interface input through the first port. 15. The method of claim 14, wherein converting the address and control signals along the first method memory interface input through the first port into the address and control signals along the second method memory interface. Generating timing information for performing a read, write, and refresh operation according to the second method memory interface by receiving a control signal that is input through the first port; And And receiving the timing information to generate a control signal according to the second type memory interface.

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