CN1052094C

CN1052094C - Serial access storage

Info

Publication number: CN1052094C
Application number: CN94106176A
Authority: CN
Inventors: 林京元
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 1994-05-21
Filing date: 1994-05-21
Publication date: 2000-05-03
Anticipated expiration: 2014-05-21
Also published as: CN1112717A

Abstract

The present invention provides a serial access memory which is provided with a first data terminal and a memory cell array, wherein the memory cell array is provided with a plurality of addresses. The serial access memory comprises a shift register and an address demoding circuit and responds to one address clock pulse signal. The shift register stores a first address value of the serial access operation of the memory. The address demoding circuit responds to an access control signal, the first address value, the address clock pulse signal and a clock pulse signal, and values in a plurality of addresses are accessed in a serial mode.

Description

The memory device of serial access

The present invention relates to a kind of memory device, refer to a kind of integrated circuit memory devices of serial access especially.

In order to satisfy the demand of nearest multimedia computer system, the integrated circuit storing apparatus has been used to store mass data, for example voice or image data recently.Voice or image data have the continuous characteristic of data, in other words, these class data, under most of situations, with the time sequential mode (sequentially) or the access of serial (serially) mode.

Traditional relevant technologies has dual mode to handle digital speech and stores.First kind of mode adopts chip that voice controller and speech memory are incorporated in the integrated circuit.The design of this mode lacks system compatibility.Such as, the minimum memory span that 12 inches speech recording and reproducing systems are required and 6 inches required and inequality.In this case, though the part of the controller in the chip still can satisfy user's demand,, and must change entire chip because of storer self-capacity deficiency.

The second way adopts the scheme of two chips, as shown in Figure 1.First chip 13 is responsible for voice control function, and second chip 11 is responsible for the speech-sound storage function.This mode obviously has compatibility than first kind of mode.But this mode still has many shortcomings.First shortcoming is to need too many output/go into pin (pins).Static storage (SRAM) with 256K is an example, must the interface pin comprise A0～A14 address wire at least, D0～D7 data line, memory read (RD) and write (WR) control line, chip is selected (CS) line, Vdd and Vss line.Second shortcoming is the feasibility of memory expansion.When needs when 256K extends to 1M, chip 11 needs to increase by two address wire A15 and A16.The input that the 3rd shortcoming is first chip 13/the go into demand of pin.When controller 13 notice roads arrive the terminal point of this memory during by access because of memory chip 11, thereby controller 13 needs at least one to select signal wire M1, M2, know institute's employing storer capacity of 11 this moment according to the input value controller 13 of M1, M2.

In order to overcome the shortcoming of above-mentioned prior art, first purpose of the present invention provides a serial access memory, its must output/going into pin lacks than the number of pins of prior art.

Second purpose of the present invention provides a serial access memory, and it need only a data line, an address clock taps, a time clock line and an access control line just can carry out the string type access.

The 3rd purpose of the present invention provides a serial access memory, and its number of exporting/going into pin is irrelevant with its memory span.

The 4th purpose of the present invention provides a serial access memory, when this memory is carried out the string type access, need only be obtained first address value of memory access by controller.

To achieve the object of the present invention, the string type access storage unit device among the present invention has one first data terminal and a memory cell array, and this memory cell array has most addresses, and this storing apparatus comprises:

One shift register, it responds an address clock pulse signal, and first address value of memory device one serial access action is stored, and this shift LD utensil one first input end and described first data terminal link;

One address decoding circuitry, it responds an access control signal, described first address value, described address clock pulse signal and a time clock signal, and the serial access action is carried out in most addresses in the described memory cell array.

Illustrated explanatory memorandum:

Fig. 1 is the synoptic diagram of the speech recording and reproducing system of prior art.

Fig. 2 is the synoptic diagram of the speech recording and reproducing system among the present invention.

Fig. 3 is the displacement sequential chart of first address value during the memory access among the present invention.

Fig. 4 is the detailed functional block diagram of serial access memory among the present invention.

Fig. 5 is that the present invention carries out the coherent signal sequential chart that memory writes.

Fig. 6 is the detailed electrograph figure of edge detector among Fig. 4.

Fig. 7 is the generation circuit diagram of write signal and read output signal.

Fig. 8 is the detailed functions calcspar of the second embodiment of the present invention.

Fig. 9 is the detailed circuit diagram of reset circuit among Fig. 8.

Figure 10 is the sequential chart of signal among Fig. 9.

Figure 11 is another circuit diagram that has reset function and edge detection feature simultaneously.

As shown in Figure 2, serial access storing apparatus 21 of the present invention is to put controller 23 with a quotation to link.Interface therebetween comprises a time clock line (CLK) 230, an address clock pulse (ADD CLK) 210, one two-way data line (DATA) 220, memory read-write (WR/RD) line 240, chip selection (CS) line 250 and memory terminal point (EOM) line 260.Memory read/write line 240 is to be used for the memory access control.

Storage arrangement 21 has most addresses, and the value in it can be via data line 220 by serial access.The data input pin of storage arrangement 21 (DATA) was imported first address value of the serial access action of memory device with serial mode in one first period, and made a data shift in a residue period with serial mode.First address value in the sequential of data line 220 superior displacements as shown in Figure 3 during the memory access.

As shown in Figure 4, memory device 21 has a shift register 42, and it responds an address clock pulse signal 210, and first address value of storage arrangement one serial access action is stored.This shift LD utensil one first input end and first data terminal (DATA) link.Memory device 21 has an address decoding circuitry 44, its response is read (READ) signal 242, is write (WRITE) signal 241, the first address value signal 421 and address clock pulse signal 210, and the serial access action is carried out in most addresses in the memory unit array 46.Both are relevant with clock pulse signal 230 and memory read 240 for read signal 242, write signal 241, and its detailed relation has a detailed description in the back, as shown in Figure 7.

Shift register 42 has N data register 420, and they are this shift register 42 of serial connection formation mutually.In N data register each has a data output end (Q), a time clock input end (CLK) and a data input pin (D), and the data input pin of first data register is the first input end of shift register 42 and links with data input pin (DATA).The clock pulse terminal Input Address clock pulse signal 210 of each data register 420.

Address decoding circuitry 44 has one address latch/counter 442, it has N input end, the data output end (Q) of the corresponding data register 420 with of each input end links, so that respond (Load) signal 448 of packing into, first address value is latched, and respond an increment (increment) signal 446 the access address value is increased one by one.Address decoding circuitry 44 has EOM end, and it during by access, exports a memory terminal point (End of Memory) signal 260 in last address of this memory cell array 46.

Address decoding circuitry 44 further comprises an edge detecting device 444, and it responds access control signal 240, clock pulse signal 230 and address clock pulse signal 210, so that produce pack into signal 448 and increment signal 446.

String type access storage unit device 21 has a data buffer 48 and links with data input pin (DATA) and memory cell array 46 respectively, and response access control signal 240 and time clock signal 230, makes described data shift with serial mode.

The present invention is shown in Fig. 5 with the signal sequence that storer writes when action, and as can be known when the value in last memory address during by access, memory terminal point (End of Memory) signal 260 moves (asserted) by wherein.In the signal of Fig. 5, when access control signal 240 became high level under controller 23 effect, for storer writes action, and access signal 240 was when becoming low level under controller 23 effects, and memory read goes out action.

In Fig. 6, show an embodiment of edge detector 444.It has a Sheffer stroke gate 60, one first rejection gate 62, one second rejection gate 64, a not gate 66, a delay circuit 67 and one and door 68.Sheffer stroke gate 60 has two input ends to divide input one read signal 242 and a write signal 241, and has an output terminal to produce increment signal 446.First rejection gate 62 has a first input end, one second input end and one first output terminal.First input end input increment signal 446.Second rejection gate 64 has one the 3rd input end, a four-input terminal and one second output terminal.First output terminal of the 3rd input end Input Address clock pulse signal 210, the four-input terminals and first rejection gate 62 links, and second input end of second output terminal and first rejection gate 62 links and produce one second output signal 641.Not gate 66 has one the 5th input end and one the 3rd output terminal, and second output terminal of the 5th input end and second rejection gate 64 links, and the 3rd output terminal produces one the 3rd output signal 661.With door 68, respond second output signal 641 and the 3rd output signal 661, produce the signal 448 of packing into.

As shown in Figure 7, write signal 241 is to be done to be produced with non-(NAND) operation by clock pulse signal 230 and memory access control signal 240.And read output signal 242 is to be made NOT-AND operation and produced by the non-value of clock pulse signal 230 and memory access control signal 240.

By the explanation of foregoing invention first embodiment as can be known, this case has following advantage:

The first, one single data (DATA) line 220 and an address clock taps 210 enough are used for memory cell array 46 is carried out the string type access, and speed can be too not slow.

The second, the interface signal line that controller 23 and storing apparatus are 21 all must not changed, no matter the amount of capacity of storing apparatus 21, as 256K or 1M or the like.

The 3rd, the address latch/counter 442 in storing apparatus 21 can be exported a signal 260 to controller 23 when storer all deposits data in.Thereby just must not select the memory-aided capacity that makes of signal M1, M2 announcement.

The 4th, the memory storage 21 of multi-form or capacity all can cooperate with identical controller 23, and must not do any correction to storer 21 itself or controller 23.

It is its unique shortcoming that the storage arrangement 21 of first embodiment of the invention can not be handled the variable word length address.

Because after in a single day storage arrangement 21 was made and finished, number of data register 420 was just fixing in it.For example, 20 data registers 420 are arranged to the SRAM (Static Random Access Memory) (SRAM) of 1M.Address clock pulse signal 210 must have 20 time clock correctly to carry out access to memory cell array 46.Surpass 20 time clock if controller 23 is sent on address clock taps 210, then shift register 420 just can only keep 20 last values.Thereby its access action is subject to the capacity of memory 21 itself.Otherwise, send as controller 23 and to be less than 20 time clock, then because of the influence of the left value of some higher bits (higher bits) in the shift register 42, first address value of access will produce mistake.Therefore for overcoming this little minor defect, the present invention provides second embodiment as shown in Figure 8 again.

Second embodiment as shown in Figure 8, has identical shift register 42, address latch/counter 442, memory cell array 46, edge detector 444, data buffer 48 with first embodiment.The function of these elements and manner of execution are all described identical with first embodiment, can not repeat them here with reference to narration relevant among first embodiment.

Reset circuit 450 response address clock pulse signals 210, read signal 242 or write signal 241 in Fig. 8 produce a reset signal 452 and make shift register 42 resets.The preferred embodiment of reset circuit 450 is shown among Fig. 9.

As shown in Figure 9, reset circuit 450 has a Sheffer stroke gate 90, one first rejection gate 92, one second rejection gate 94, a not gate 96, a delay circuit 97 and a rejection gate 98.Sheffer stroke gate 90 has two input ends and imports a read signal 242 and a write signal 241 respectively, and tool one output terminal.First rejection gate, 92 tools, one first input end, one second input end and one first output terminal.The output terminal of first input end Sheffer stroke gate 90 links.Second rejection gate 94 has one the 3rd input end, four-input terminal and one second output terminal.The 3rd input end Input Address clock pulse signal 210, and first output terminal of the four-input terminal and first rejection gate 92 links, second input end binding of second output terminal and first rejection gate 92 also produces one second output signal 941.Not gate 96, tool 1 the 5th input end and one the 3rd output terminal, second output terminal of the 5th input end and second rejection gate 94 links, and the 3rd output terminal produces one the 3rd output signal 961.Rejection gate 98 responds second output signal 941 and the 3rd output signal 961, produces reset signal 452.

The sequential relationship of signal is shown in Figure 10 among Fig. 9.Similarly, write signal 241, read signal 242 are produced by the circuit of Fig. 7.

Because of first address clock pulse signal 210 places after last once read signal 242 or write signal 241 are cancelled (deasserted) produce an action reset signal 452, so shift register 42 is by reset, so that correctly store first address value that is next read in (clocking) by data line 220 under the time clock effect.If the number of this address value is less than the number of data register 420, can wrongly not take place yet.

Claims

1, a kind of memory device of serial access has one first data terminal and a memory cell array, and this memory cell array has most addresses; With a shift register, its response is stored first address value of a memory device one serial access action from an address clock pulse signal of control device, and this shift LD utensil one first input end and described first data terminal link, it is characterized in that, also comprise:

One address decoding circuitry, its response is carried out the serial access action from an access control signal of control device, described first address value, described address clock pulse signal and a clock pulse signal from control device to most addresses in the described memory cell array.

2, memory device as claimed in claim 1 wherein also comprises:

One data input pin was imported first address value of memory device one serial access action with serial mode in one first period, and transmitted data in a residue period in a tandem mode;

One data buffer, it links with data input pin and memory cell array respectively, and responds a described access control signal and a described clock pulse signal, transmits described data with serial mode.

3, a kind of serial access memory device with variable address word length ability has one first data terminal and a memory cell array, and this memory cell array has most addresses;

With a shift register, it responds an address clock pulse signal from control device, and first address value of a memory device one serial access action is stored, and this shift LD utensil one first input end and described first data terminal link, it is characterized in that, also comprise:

One address decoding circuitry, its response one access control signal from control device, described first address value, described address clock pulse signal and a time clock signal carry out the serial access action to most addresses in the described memory cell array; And

One reset circuit, it responds described access control signal, described clock pulse signal and described address clock pulse signal, produces a reset signal so that described shift register reset.

4, memory device as claimed in claim 2 further comprises:

One shift register, it responds a described address clock pulse signal, and first address value of memory device one serial access action is stored, and this shift LD utensil one first input end and described first data terminal link;

One address decoding circuitry, it responds a described access control signal, described first address value, described address clock pulse signal and a described clock pulse signal, and the serial access action is carried out in most addresses in the described memory cell array.

5, as claim 1 or 3 or 4 described memory devices, wherein this shift register has the mutual serial connection of N data register to constitute described shift register, each data register in N data register has an output terminal (Q), a time clock input end (CLK) and a data input pin (D), the data input pin (D) of first data register in N data register is the first input end of shift register, and the clock pulse input terminal of each data register is imported described address clock pulse signal.

6, memory device as claimed in claim 5, wherein this address decoding circuitry comprises one address latch/counter, it has N input end, each input end links with the data input pin (Q) of a corresponding data register, its response one signal of packing into latchs described first address value, and its response one increment signal is with the increase one by one of access address value.

7, memory device as claimed in claim 1, wherein this address decoding circuitry has EOM end, and its value in a FA final address of this memory cell array is exported a memory terminal point (End of Memory) signal during by access.

8, memory device as claimed in claim 6, wherein this address decoding circuitry further comprises:

One edge detecting device, its input end are imported described access control signal, described address clock pulse signal and described clock pulse signal respectively, export described signal and the increment signal of packing into.

9, memory device as claimed in claim 8, wherein edge detector comprises:

One Sheffer stroke gate, its tool two input ends are imported one respectively and are read (read) signal and and write (write) signal, and tool one output terminal is exported described increment signal;

One first rejection gate, its tool one first input end, one second input end and one first output terminal, first input end is imported described increment signal;

One second rejection gate, its tool 1 the 3rd input end, a four-input terminal and one second output terminal, the 3rd input end is imported described address clock pulse signal, first output terminal of the four-input terminal and first rejection gate links, and second input end binding of second output terminal and first rejection gate is also exported one second output signal;

One not gate, its tool 1 the 5th input end and one the 3rd output terminal, second output terminal of the 5th input end and second rejection gate links, and the 3rd output terminal is exported one the 3rd output signal;

One with the door, its input end is imported described second, third output signal respectively, exports the described signal of packing into.

10, memory device as claimed in claim 3, wherein the reset circuit comprises:

One Sheffer stroke gate, its tool two input ends are imported one respectively and are read (read) signal and and write (write) signal, and tool one output terminal;

One first rejection gate, its tool one first input end, one second input end and one first output terminal, the output terminal of first input end and Sheffer stroke gate is connected;

One rejection gate, its two input end is imported described second, third output signal respectively, exports described reset signal.