NL194899C - Method for mode conversion of a two-port memory device. - Google Patents

Description

1 194899

Method for mode conversion of a two-port memory device

The invention relates to a method for mode conversion of a two-port memory device, which is provided with a RAM port, a SAM port and a control component for generating control signals, wherein a readout transfer cycle is performed in which data in the SAM port is transferred to the SAM port in a readout transfer mode and the data in the SAM port is transferred into a serial readout mode, a record transfer cycle being performed in which data is stored directly from an external device in a serial record mode into the SAM port and data in the SAM port is transferred to the RAM port in a record transfer mode and a pseudo-record transfer mode is performed, which is converted to the serial record mode without data transfer between the read transfer cycle and the record transfer cycle.

Such a method is known from U.S. Pat. No. 4,866,678. A pseudo-transfer cycle is hereby applied when switching from a read-out transfer cycle to a registration transfer cycle. This makes it possible to refresh the memory element.

The invention relates more particularly to the mode conversion for data transfer into a freely accessible video memory (VRAM), which comprises a freely accessible memory (RAM) port and a serially accessible (SAM) port and for testing the freely accessible and serial access.

At present, with an integration capacity of 1-Mbit, VRAMs exist in two types: 256K x 4 and 128 K 20 x 8. With VRAMs, when the processor transfers the data via the first port to the memory, access can be made simultaneously via the second port until the memory is obtained.

This relationship will be described with reference to Figure 1.

Figure 1 shows a VRAM 10 with a RAM port 1 and a SAM port 2. The RAM port 1 is connected to the SAM port 2 via an information transfer port DTG. A first port P1 of the VRAM 10, connected to the processor, is used for free access, while a second port P2, connected to a screen display device, is used for the serial access. Furthermore, one side of the RAM port 1 is connected to the first port P1 via a column decoder 4 and the other side thereof is connected to the row decoder, but the row decoder is not shown, and 5 is a control part. Since the SAM port 2 for the serial access has a short access time 30, the VRAM 10 is used on a large scale in display systems with large resolution or high speed.

During the readout transfer cycle, the data in the SAM port 1 is registered in the SAM port 2 and the mode for reading the data in the SAM 2 is set. Similarly, the data in the SAM port 2 is recorded in the RAM port 1 during a record transfer cycle and the data record mode is set by the record transfer cycle and a pseudo-record mode PWT. During the recording mode, the data is converted to the data reading mode in the SAM port 2, the readout transfer cycle must be handled and the data in the RAM port 1 is supplied to the SAM port 2 so that the SAM port 2 cannot perform the readout operation directly after recording the data from SAM port 2. Therefore, in mass production of 40 the VRAM, testing of the SAM port itself is impossible since the SAM port does not read out and can perform registration operations independently of the RAM port.

It is an object of the invention to provide a method for mode conversion of a two-port memory device in which a SAM port can perform the same read and record operations independently of the RAM port when testing a RAM.

45 In the method known from the aforementioned U.S. patent specification, the SAM port cannot yet perform read and record operations completely independently of the RAM port, as is apparent from the following.

This object is achieved with the method of the above-mentioned type, characterized in that a pseudo readout transfer mode is performed, which is converted to the series readout mode without data transfer between the record transfer cycle and the readout transfer cycle.

The invention will be explained in more detail below with reference to the drawing. In addition: Figure 1 shows a block diagram of a conventional VRAM structure; Figure 2 is a time diagram of each operating mode of a SAM port in the VRAM; Fig. 3 shows a mode conversion flow chart showing the operation of the SAM in a conventional two-port memory device; and FIG. 4 is a mode conversion flow chart indicating the operating state of the SAM according to the invention.

194899 2

With reference to Figure 1, the operation of a VRAM 10 will be described. A RAM port 1 in the VRAM 10 is connected via a first port P1 to a processor (not shown), while a SAM port 2 in the VRAM 10 is connected via a second port P2 to a display device 3. The data which is transferred from the processor, is freely stored in the RAM port 1 via the column decoder 5 and a row decoder (not shown). The data stored in the RAM port 1 is transmitted across a row to the SAM port 2 in a readout transfer mode RT. At this time, the data is transmitted via a data transfer port DTG to the SAM port 2. The SAM port 2 has serial registers corresponding to a row of the RAM port 1 so that the data is received or supplied in series by the row.

In a serial read-out mode SR, the data stored in the SAM port 2 is displayed via the second port 2 in the display device 3. Further, in the case that the data is stored directly in the RAM port 1 through an input device such as a pen writer or the like via the SAM port 2, the SAM port 2 is first converted into a pseudo-registration transfer mode PWT and then converted to a serial registration mode SW and therefore the data is registered via the second port P2 in the SAM port 2. In a registration transfer mode WT, the data stored in the SAM port 2 is then transferred to the RAM port 1, with the data currently being transferred via the data transfer port DTG.

In this VRAM, the operating modes of the SAM port can be summarized as follows:

- readout transfer mode RT

20 - real-time readout transfer mode RRT

- SR series readout mode

- serial registration mode SW

- registration transfer mode WT

- pseudo-registration transfer mode PWT

The data communication between the RAM port and the SAM port even takes place in the transfer mode and the serial readout mode SR or the serial recording mode SW is set. In the other serial readout mode SR or serial registration mode SW, the SAM port operates independently of the RAM port. More specifically, in the pseudo-registration transfer mode PW 10, the data transfer between the RAM port and the SAM port does not occur, but only the mode conversion to the serial registration mode SW occurs. The operation of the SAM is achieved by the correlation of 6 modes, the mode conversion being performed as indicated in FIG. 3. In FIG. 3, the mode conversion proceeds only in the direction of the arrow.

Each of the modes has the following functions:

(1) readout transfer mode RT

This mode is for transferring the data from a row unit from the RAM port to the series of registers of the SAM port. At this time, the last rising edge of a series clock signal SC must precede the active edge of a row address "strobe" signal RAS. After performing the readout transfer mode RT, the series readout mode SR is set to read the data internally in series. Figure 2 (a) shows a time diagram for the readout transfer mode R.

40 In Figure 2, RAS is the row address "strobe" signal and CAS a column address "strobe *" signal and its A0-A8 address signals and its SI01-SI04 input / output signals. Furthermore, DT / OE is a clock signal which controls the data transfer and the output signal of the RAM port, SC is a clock signal for serial access (read out / recording) and SE is a serial release clock signal.

(2) Time-to-read readout transfer mode RRT.

45 This mode is used to sequentially process the stream of information that is larger than the size of the serial register size. The only difference with the readout transfer mode RT is that the last clock signal of the signal SC and the signal DT / OE must be synchronized with each other. Furthermore, the DT / OE signal must be synchronized with the RAS and CAS signals. This mode can perform time-based access and data transfer simultaneously. A 50 time diagram for this mode is shown in Figure 2 (b).

(3) SR series readout mode

This mode is used to quickly read out the data in the serial registers in accordance with the signal SC after the SAM port has been set by the readout transfer mode RT or the time-true readout transfer mode RRT in this mode. A time diagram of this mode is shown in Figure 2 (c).

55 (4) serial registration mode SW

This mode is for quickly registering the successive data in the serial ports of the SAM port. This mode does not differ from the serial read mode SR with respect to the external 194899 tempering. The serial registration operation takes place with the same tempering as the signal SC since the mode is set internally after the registration transfer mode or the pseudo-registration transfer mode PW 10. A time diagram of this mode is shown in Figure 2 (d).

(5) WT registration transfer mode

This mode serves for transferring the data stored in the serial register in the serial registration mode SW to the RAM port with a row unit. Furthermore, after this mode, the SAM is internally set to the serial registration mode SW. A time diagram of this mode is shown in Figure 2 (e).

(6) pseudo-registration transfer mode PWT

The data transfer from the SAM port to the RAM port takes place through the registration transfer mode WT after the data has been registered in the serial registers. In order to run the serial registration mode SW after the serial readout mode ST, the SAM port must be set to the serial registration mode SW. This is because the incorrect data is transferred to the RAM port if the registration transfer mode WT is performed before the SAM port has not yet been set to the serial registration mode SW. Therefore, the data should not be transferred from the SAM port to the RAM port during the conversion from the serial read mode SR to the serial recording mode SW. The pseudo-registration transfer mode PWT serves to convert the serial read mode SR to the serial registration mode SW without data transfer.

A time diagram of this mode is found in Figure 2 (f). The SAM port is operated with the above six modes in the order of Figure 3.

Fig. 3 is a mode flow diagram showing the operation of the SAM port of a conventional two-port memory device. Figure 3 shows the readout transfer cycle 6, the record transfer cycle 7 and the pseudo-record transfer mode PWT between the readout transfer cycle 6 and the record transfer cycle 7. The serial readout mode SR is only executed when the readout transfer or time-true readout transfer operation is first completed. In the VRA, either the readout transfer mode RT or the time-true readout transfer mode PRT is initially selected by a "hardware" structure. Therefore, for data transfer from the RAM port to the SAM port, the data in the RAM port is transferred over a row unit in the read transfer mode RT or the time-to-time read transfer mode RRT to the serial registers of the SAM port. The data stored in the serial registers is quickly read out in the serial read mode SR and also transferred to the display device.

On the other hand, to store the data directly from an external device in the SAM port, the serial registration mode SW must first be set. That is, for the conversion from the serial read mode SR to the serial record mode SW, the pseudo record transfer mode PWT must be performed. In the pseudo registration transfer mode PWT, no data transfer takes place. In the serial registration mode SW, the data supplied from the internal device is stored directly in the SAM port. In addition, to re-read the data stored in the SAM port, the mode must be converted to the serial read mode SR, but the mode cannot be converted directly from the serial record mode SW to the serial read mode SR, as shown in FIG. 3 Therefore, after the mode has been converted from the serial registration mode SW to the registration transfer mode 40 WT, the data in the serial registers of the SAM port in the registration transfer mode WT is transferred to the RAM port. To retransmit the data stored in the RAM port to the SAM port, after the data transfer mode RT is stored in the SAM port, the data stored in the SAM port is read out in the serial read mode SR . Therefore, in the SAM test, where the SAM port is checked whether it is normal or incorrect by comparing the original data with the 45 data read out from the SAM port, the readout transfer mode RT must be performed so that the data communication between the RAM port and the SAM port always takes place, making testing of SAM impossible.

Figure 4 is a mode conversion flow chart showing the operation of the SAM in a two-port memory device according to the invention. In Figure 1, the readout transfer cycle 6 and the record 50 transfer cycle 7 are the same as in Figure 3. In addition, the pseudo readout transfer mode PRT and the pseudo-register transfer mode PWT occur between the readout transfer cycle 6 and the record transfer cycle 7. The basic operations of the read transfer cycle 6 and the record transfer cycle 7 are the same as in FIG. 3, and the pseudo-record transfer mode for converting the read transfer cycle 6 to the record transfer cycle 7 is also identical to that of FIG. 55 3.

However, as shown in Figure 4, the SAM port can be converted from the serial registration mode SW to the serial read mode SR by the pseudo read transfer mode PRT without a

Claims (3)

194899 4 data transfer in the event that the original data is compared with the data read from the SAM port in the SAM test. That is, if the pseudo read transfer mode PRT is executed after the data from the external device is stored in the SAM port at the serial registration mode SW, the SAM is converted to the serial read mode SR without data transfer. Therefore, the data stored in the SAM port is read out for comparison with the original data, so that the SAM port is checked regardless of whether it is normal or incorrect. The above operation will be explained with reference to Figure I. After the mass production of the VRAM by semiconductor manufacturing processes, the RAM port and the SAM port in the VRAM are tested in the condition on the plate to check whether it is normal or incorrect . The RAM test is the same as the conventional RAM test. In order to test the SAM in the manufacturing processes for mass production of the VRAM, bodies which are used only in the platelet state are established to form a third port P3. Moreover, the pseudo read transfer mode PRT for the mode conversion from the serial recording mode SW to the serial read mode SR takes place by the control clock signals of the control part 5. When the VRAM on the plate is manufactured and the SAM port is tested, the serial recording mode SW performed the first in the registration transfer cycle 7. At this time, the test data is stored in the SAM port 2 via the second port P2 and the pseudo read transfer mode PRT is performed by applying the control clock signals from the control part 5 to the third port P3 in order to receive the data stored in the SAM port 2 to transfer data to the second port P2. Thereafter, the SAM port is converted to the serial read-out mode SR without the data transfer between the SAM port and the RAM port. The data stored in the SAM port is read out in the serial read mode SR, so that the data is compared with the original data to check whether the SAM port is either normal or incorrect. As mentioned above, the RAM port and the SAM port can be tested in a simple manner as to whether they are normal or incorrect and in the location condition of a mass production of the two-port memory device provided with the RAM port and the SAM port. More specifically, the SAM port can be tested in a simple manner to determine whether it is normal or incorrect in the SAM test since the SAM port from the serial recording mode SW to the serial read mode SR by the pseudo-record transfer mode PWT can be converted without transferring data. 30 1. Method for mode conversion of a two-port memory device, which is provided with a RAM port, a SAM port and a control component for generating control signals, wherein a read-out transfer cycle is carried out in which data in the SAM port is stored in a readout transfer mode is transferred to the SAM port and the data in the SAM port is transmitted in a serial readout mode, a record transfer cycle is performed in which data is stored directly from an external device in a serial registration mode in the SAM port and 40 data in the SAM port is transferred to the RAM port in a record transfer mode and wherein a pseudo-record transfer mode is performed, which is converted to the serial record mode without data transfer between the read transfer cycle and the record transfer cycle, characterized in that a pseudo read transfer cycle mode is carried out, which in the series exc A read mode is converted without data transfer between the record transfer cycle and the read transfer cycle. Method according to claim 1, characterized in that the pseudo read transfer mode for converting the serial registration mode to the serial read mode without data transfer between the RAM port and the SAM port is performed by a predetermined control signal from the control part. 3. A method as claimed in claim 1, characterized in that the pseudo read transfer mode for converting the serial registration mode to the serial read mode is performed without data transfer between the RAM port and the SAM port by providing connection points on a semiconductor plate, to which connection points a predetermined signal is applied to test a VRAM device. Hereby 5 sheets of drawing