JPH0414695A - Mode conversion of dual port memory element - Google Patents

Abstract

PURPOSE: To make it possible to perform a test on SAM port itself by adding further a virtual reading transmission mode to be converted into a serial reading mode without transmitting data between a record transmission cycle and a read transmission cycle. CONSTITUTION: When a SAM port is tested, serial recording mode SW of a record transmission cycle is executed. Then, data for the test are stored in a SAM port 2 through the second port P2. To output the data stored in SAM port 2 to a second port P2, a control clock signal is impressed on a third port P3 from a control part 5, and a virtual transmission mode PRT is executed. Thus, the SAM port makes a RAM display equipment 3 display. Further, when data are stored directly in RAM port 1 by an input device through the SAM port 2, the SAM port 2 is converted into the virtual transmission mode.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a RAM port (Random Access
Memory Port) and SAM Port (Seria
A dual-port memory device (Dual-port He[
Regarding the mode switching method of 1ory Device), for more details, refer to 161:
' -F RAM (Video RAM; VRA
The present invention relates to a mode switching method for a dual-port memory device that changes the mode during data transmission in M) or changes the mode for testing serial access and random access.

[Prior art] VRAM for graphic displays was initially
It had 4KX1 RAM ports and 256KX1 SAM ports. Later, 256 VRAMs with 64 x 4 access ports were developed.

From this time on, by improving the functions of 64Kxl VRAM, we were able to improve the recording function (Write-per-bit) and real-time data transmission from memory to serial register (
A standardized form of VRAM has been created by adding a function for real-time transfer (Real-time Transfer). Currently, VR at the 1Mbit density stage
A M Ha256 K X 4 or Ha128 K X
It is classified into two types: 8.

On the other hand, in the case of a boat-loading RAM, when transmitting information from a processor to a peripheral device, the information is first transmitted to the memory and then the information in the memory is accessed.

In this case, the processor cannot communicate information to the memory while the access is being performed by the peripheral device.

However, VRAM is configured so that while the processor is transmitting information to the memory through the first port, the peripheral device can simultaneously access the memory through the second port, and this relationship is maintained. The explanation will be as follows with reference to FIG.

FIG. 1 shows a VRAM10 formed by RAM port 1 and SAM port 2. These RAM ports 1
and SAM port 2 are connected through a data transfer 1 gate DTG formed of a MOS transistor. The first port P1 of the VRAM 10 is connected to the processor and used for random access, and the second port P2 is connected to the image display device 3 and used for serial access. And RAM
One side of the port 1 is connected to the first port P1 through the column decoder 4, and the other side is connected to a row decoder (not shown).

Reference numeral 5 indicates a control section. Therefore, a serially accessed SAM port has a fast access time, which is why VRAM10 is widely used in high resolution or high speed image display systems.

[Problem to be solved by the invention]

Thus, during the read transmission cycle, data written to RAM port 1 is written to SAM port 2, and a mode in which SAM port 2 can be read is set. During the write transmission cycle, S
The data written to M port 2 is written to RAM port 1, and the mode for recording data is set by the write transmission cycle and virtual recording mode PWT.

When SAM port 2 is switching from write mode to read mode, it must go through a read transmission cycle, and the data in RAM port 1 must be transferred to SAM port 1.
Since the SAM port 2 is provided to the AM port 2, the SAM port 2 cannot perform a read operation immediately after recording data.

Therefore, VRA, which is a type of dual-port memory device,
During mass production of M, the SAM port itself could not be tested because the SAM port could not perform read and write operations independently of the RAM port.

The present invention solves these problems, and
When testing dual port memory devices such as RAM,
It is an object of the present invention to provide a mode switching method for a dual-port memory device that allows a SAM port itself to perform read and write operations independently of a RAM port.

[Means to solve the problem]

To achieve the above object, the mode switching method of a dual port memory device according to the present invention as set forth in claim 1 provides a read transmission method that is selected on initial hardware and transmits data stored in a RAM port to a SAM port. a read transmission cycle consisting of a real-time read transmission mode, a serial read mode for outputting data stored in the SAM port, and a serial recording mode operated for storing data directly from the outside to the SAM port; SAM
A recording transmission cycle consisting of a recording transmission mode in which data stored in a port is transmitted to a RAM port, and a virtual recording transmission in which the mode is changed to a serial recording mode without transmitting data between the read transmission cycle and the recording transmission cycle. The mode switching method for a dual-port memory device having a dual-port memory device is characterized in that a virtual read transmission mode is further added between the record transmission cycle and the read transmission cycle, in which the mode is changed to a serial read mode without transmitting data. shall be.

Further, the mode conversion method for a dual port memory device according to claim 2 provides a virtual read transmission mode for converting serial recording to serial reading without transmitting data between a RAM port and a SAM port. , is characterized in that it is executed by a control signal set by the control section.

Further, in the mode conversion method for a dual port memory device according to claim 3, the virtual read transmission mode for converting from serial recording to serial reading without transmitting data between a RAM port and a SAM port is a mode conversion method for a VRAM device. It is characterized in that it is carried out by adding a pad to which a constant signal can be applied so that the Weber state can be tested.

[For production]

According to the mode switching method for a dual port memory device of the present invention as set forth in claim 1, data is prevented from being transmitted to the RAM port when switching from serial recording mode to serial reading mode during testing of the SAM port. A virtual read transmission mode is implemented in which only the SAM port can perform read and write operations.

Further, according to claim 2, the RAM port and the SAM
A virtual read transmission mode in which serial recording is converted to serial reading without transmitting data to the port is executed by a control signal set by the control section.

According to claim 3, the virtual read transmission mode converts serial allocation to serial read without transmitting data between the RAM port and the SAM port.
This is done by adding a pad to the VRAM device to which a constant signal can be applied so that it can be tested to Weber state.

〔Example〕

Hereinafter, embodiments of a mode switching method for a dual port memory device according to the present invention will be described in detail.

First, the operation of the VRAM will be explained with reference to FIG.

The RAM port 1 of the VRAM10 is connected to the processor through the first port P1, and the SAM port 2 is connected to the display device 3 through the second port P2. Data transmitted through the processor is randomly stored in the RAM port 1 through a column decoder 4 and a row decoder (not shown).

Data stored in RAM port 1 is transmitted to SAM port 2 in units of 10 rows of RAM port 1 in a read transmission mode. At this time, data is transmitted through the data transfer gate DTG. The SAM port 2 has serial registers in units of 10 units of the RAM port 1, and inputs or outputs data in units of rows in serial.

In the serial read mode, data stored in the SAM port 2 is displayed on the display device 3 through the second port P2. In addition, when data is directly stored in RAM port 1 through SAM port 2 by an input device such as a penlight, SAM port 2 is first converted to virtual record transmission mode, and then serial data is stored without transmitting data. When the recording mode is changed, data is stored in the SAM port 2 through the second baud 1-P2. Next, in the recording transmission mode, the data stored in the SAM port 2 is transmitted to the RAM port 1, and at this time, the data is also transmitted through the data transformer 77 gate DTG.

The operating modes of the SAM port as a serial mode in the VRAM operated in this manner are as follows.

・Read transfer mode (RT
)・Real-time read transfer mode (Real-Time Read Transfer
r; RRT)・Serial read mode (Serial R
ea(1;SR)・Si'J Full recording mode (Seri
AL WRITE; SW)・Record transmission mode (Write
eTransfcrJR)・Virtual record transmission mode (Pseudo Write Transfer; PW
T) Therefore, the RAM port and the SAM port are in the transfer mode (Transfer Node). In serial read mode and serial record mode, the SAM port operates independently of the RAM port.

In particular, during the virtual recording transmission mode, no transmission occurs between the two ports, only a mode change to the serial recording mode occurs. The SAM operation has the same mode conversion as shown in FIG. 3 because the six modes described above are combined in a mutually correlated manner.

Here, each mode is changed only in the direction of the arrow. The functions of each of these modes are as follows.

(1) Read transmission mode This is a mode for moving data in units of 10 from the RAM port to the serial register of the SAM port.

At this time, the rising edge of the last serial clock signal SC in the previous serial read or serial allocation must be before the active edge of the D-address strobe signal RAS. After the read transmission mode, a serial read mode is set in which data can be internally read out serially.

FIG. 2(a) shows a timing chart of this read transmission mode. Here, the control clock RAS of the control unit 5 is a row address strobe (Ro
w Address 5rtobe) signal, CA
S is column address strobe (ColumnAddr
ess 5trobe) signal 10AO-A8 is an address signal, and 5IOI-8104 is an input/output signal. Then, "/σ is the clock signal that controls data transmission and RAM port output. WB/W completed"
is a clock signal for controlling recording (Write) and reading (Read), SC is a clock signal used for serial access (read/record), and SE is a serial switchable clock signal.

(2) Real-time read transmission mode This mode is used to handle continuous streams much larger than the size of the serial register.

The only difference from the read transmission mode RT is that the serial clock signal SC provides the data at the end of the serial register.
and the data transmission signal (DTloE) may have to be spaced from each other.

At this time, the data transmission signal (DTloE) must also be synchronized with RAS and CAS.

In this mode, data transmission can be performed by real-time access, and a timing chart thereof is shown in FIG. 2(b).

(3) Serial read mode This mode uses the serial clock to read the data in the serial register when the mode of the SAM port is set so that the data can be read serially by read transmission mode RT or real-time read transmission mode RRT. It can be read out at high speed according to signal SC.

A timing chart of this relationship is shown in FIG. 2(C).

(4) Serial recording mode This mode is for sequential recording at high speed in the serial register, and there is no difference from the serial read mode in terms of external timing. Recording transmission mode W
Since this mode is internally set after T or virtual recording transmission mode PWT, serial recording is performed at the same timing as the serial clock signal SC.

A timing chart at this time is shown in FIG. 2(d).

(5) Recording Transmission Mode In this mode, the data stored in the serial register is transmitted to ten RAM ports by the serial recording mode SW. Also, when this mode ends, the SA
M is internally set to serial recording mode SW.

A timing chart at this time is shown in FIG. 2(e).

(6) Virtual recording transmission mode Data transmission from the SAM port to the RAM port is performed in the allocating transmission mode WT after first going through the process of recording data in the serial register. In order to execute the serial distribution mode SW after the serial read mode FSR, the SAM port must be set in the serial recording mode SW, which must be set in the recording transmission mode WT. If the recording transmission mode WT is executed with the serial recording mode SW not set, unintended data (Wron
g Date) will be transmitted. Therefore, when only mode conversion is performed from serial read mode SR to serial write mode SW, data transmission from the SAM port to the RAM port must not actually be performed. In the virtual recording transmission mode PWT, only the mode is converted from the serial read mode to the serial recording mode without transmitting data, and the timing chart at this time is shown in FIG. 2(f).

The SAM port operates in the same order as shown in FIG. 4 in the six modes described above.

FIG. 4 shows a mode sequence indicating the operating state of the SAM port of a conventional dual port memory device. This conventional dual-port memory device has a read transfer cycle 6 and a record transfer cycle 7, and the read transfer cycle 6
It includes a virtual record transfer mode PWT that is executed when the mode is transferred from record transfer cycle 7 to record transfer cycle 7. It can be seen here that the serial read mode SR is enabled only when the read transmission mode RT or the real-time read transmission mode RRT is terminated. In VRAM, read transmission mode R
The selection of T or real-time read transmission mode RRT is selected depending on the hardware structure.

Therefore, when transmitting data from a RAM port to a SAM port, data in units of 10 from the RAM port is transmitted to the serial register in the SAM port in read transmission mode RT or real-time read transmission mode RRT. There is. Then, in serial read mode SR,
Data stored in the serial register is read out at high speed in accordance with the serial clock signal SC. On this occasion,
The data stored in the serial register of the SAM port is also transmitted to the display device.

In order to directly store data from the outside into the SAM port in such a display state, the serial distribution mode SW must be executed first.

That is, in order to convert from the serial read mode SR to the serial distribution mode SW, the virtual record transmission mode PWT must first be performed.

In this virtual record transmission mode PWT, only the mode is changed without transmitting data. In the serial recording mode SW, externally applied data is directly stored in the SAM port. In order to read the data stored in the SAM port again, the mode must be changed to serial read mode SR, but as shown in FIG.
It is not directly converted to R. Therefore, it is necessary to convert the serial recording mode SW to the recording transmission mode WT, and in the recording transmission mode WT, the data stored in the serial register in the SAM port is transmitted to the RAM port.

In order to transmit the data stored in the RAM port to the SAM port again, the SA
After the data is stored in the M port, the data stored in the SAM port is outputted in the serial read mode SR.

Therefore, when testing a SAM port, after storing data in the SAM port, the data stored in the SAM port is output and compared with the original data to determine whether the SAM port is normal or abnormal. Since the read transmission mode RT must be executed when
Data exchange between the port and the S to M port was always performed, so it was not possible to test only the SAM port.

FIG. 3 shows SA in the dual port memory device according to the present invention.
Fig. 5 shows the order of conversion modes indicating the operating status of the M port;

This embodiment has a read transmission cycle 6 having a read transmission mode RT, a real-time read transmission mode RRT, and a serial read mode SR, and a recording transmission cycle 7 having a serial recording mode SW and a recording transmission mode WT. . A virtual recording transmission mode PWT is interposed between the read transmission cycle 6 and the recording transmission cycle 7, and a virtual read transmission mode PRT is intervened between the recording transmission cycle 7 and the read transmission cycle 6. is formed. The basic operations of the read transmission cycle 6 and the recording transmission cycle 7 are the same as those shown in FIG. It is.

However, in order to test the SAM port, the present invention
When data is stored in the M port and the data stored in the SAM port is read and compared with the originally stored data, the virtual read transmission mode PRT is performed and the serial read mode SR is performed without data conversion. It can be converted.

In other words, by using the serial recording mode SW,
After storing data in the AM port, if the virtual read transmission mode PRT is performed, the SAM
The port is converted to serial read mode SR. At this time, since the data stored in the SAM port is output, it can be compared with the original data to determine whether the SAM port is normal or abnormal.

The operation in the VRAM will be explained with reference to FIG.

After VRAM is mass-produced through the semiconductor manufacturing process,
In the 7 p (II lafer) state, a test is performed to determine whether the RAM port and SAM port of the VRAM are normal or abnormal.

RAM testing is performed similar to conventional SAM testing methods. Said VRAMIF! : During mass production, in the semiconductor manufacturing process, in order to test the SAM, it is necessary to add a third pad that can only be used in the wafer state.
Forms port P3. And serial recording mode S
The virtual read transmission mode PRT for converting from W to the serial read mode SR is executed by a control clock signal set by the control unit 5. When the VRAM10 is mass-produced on the wafer and the SAM port is tested, the serial recording mode SW of recording transmission cycle 7 is first performed. At this time, the test data is
It is stored in SAM port 2 through port P2. Then, in order to output the data stored in the M port 2 to the second port P2, the control clock signal is applied from the control unit 5 to the third port P3, and the virtual read transmission mode PRT is performed. It has become so. This allows the SAM port to enter the next serial read mode S without performing data transmission with the RAM port.
Converted to R. The data stored in the SAM port 2 is output from the serial read mode SR and compared with the original data to check whether the SAM port 2 is normal or abnormal.

The present invention is not limited to the embodiments described above, and can be modified as necessary.

[Effects of the Invention] As explained above, the present invention can easily determine whether the RAM port is normal or abnormal and the SAM port is normal or abnormal in the wafer state during mass production of dual-port memory devices having a RAM port and a SAM port. can be judged, especially SAM
When testing the port, it has a virtual recording transmission mode PWT, so the serial recording state can be immediately changed to the serial reading state without data transmission between the RAM port and the SAM port, which is convenient during the semiconductor manufacturing process. Accordingly, it is possible to easily test for a defective state of a dual port memory element.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the structure of a general VRAM, Figures 2 (a) to (f) are timing charts for each operating mode of the RAM ports built into the VRAM, and Figure 3 is a dual port in the present invention. FIG. 4 is a conversion mode sequence diagram showing the operation status of a serial access port in a general dual-port memory device. 1...RAM port, 2...SAM port, 3...
- Display device, 4... Column decoder, 5... Control section, 6... Read transmission cycle, 7... Record transmission cycle, 10... VRAMXPl... First port, P2... 2nd port, P3... 3rd port, D
TG...Data transfer gate, RT...Read transmission mode, RRT...Real time read transmission mode, SR
... Serial read mode, SW... Serial recording mode, WT... Record transmission mode, PWT... Virtual record transmission mode, PRT... Virtual read transmission mode. 5IOI-5ICX FIG, 2(a) F IG, 2(e) FIG, 2(C) at night 0 tiger 14. Yonge FIG, 2(d) FIG, 3 FIG, 4

Claims (1)

[Claims] 1) A read transmission mode and a real-time read transmission mode selected on initial hardware to transmit data stored in a RAM port to a SAM port, and output data stored in a SAM port. A read transmission cycle consisting of a serial read mode to store data directly from the outside to the SAM port, a serial record mode operated to store data directly from the outside to the SAM port, and a record transmission mode to transmit data stored in the SAM port to the RAM port. between the read transmission cycle and the record transmission cycle,
In a mode switching method for a dual port memory device having a virtual recording transmission mode in which the mode is changed to a serial recording mode without transmitting data, the mode is changed to a serial read mode without transmitting data between the recording transmission cycle and the read transmission cycle. 1. A mode switching method for a dual port memory device, further comprising a virtual read transmission mode to be changed. 2) A virtual read transmission mode in which serial recording is converted to serial reading without data transmission between the RAM port and the SAM port is executed by a control signal set by the control unit. The mode switching method of a dual port memory device according to claim 1. 3) Virtual read transmission mode, which converts serial recording to serial reading without transmitting data between the RAM port and the SAM port, applies a constant signal to the VRAM device so that it can be tested in the wafer state. 2. The method of mode switching of a dual port memory device as claimed in claim 1, characterized in that the method is carried out by adding a pad capable of changing the mode of a dual port memory device.