JP4313456B2 - Memory control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is a circuit for controlling an SRAM (Synchronous Dynamic RAM) for transferring data in synchronization with a clock, and in particular, a synchronous DRAM while minimizing the number of signal lines between the control circuit and the SDRAM. The present invention relates to a memory control device that improves the actual bus bandwidth.
[0002]
[Prior art]
Conventionally, an SDRAM used as one of memory devices for storing data is capable of continuous data transfer in synchronization with a clock. When burst transfer is instructed, data transfer for a specified number of bytes is 1 It can be performed continuously in units of clocks.
[0003]
Note that as references described regarding the specifications of the SDRAM, there are, for example, “NEC μPD4516421 data sheet (1995, NEC), Japanese Patent Laid-Open No. 6-76567“ Semiconductor memory device and synchronous semiconductor memory device ”, and the like. .
[0004]
As one method for improving the data transfer capability in such a system using SDRAM, there is a method in which a plurality of SDRAMs are used to divide and store data into a plurality of SDRAMs and operate the plurality of SDRAMs simultaneously. .
[0005]
However, this method has no problem when applied to transfer to a continuous area where the burst length can be sufficiently long. However, in the case of random access with a short burst length, the performance of the SDRAM cannot be exhibited sufficiently, In particular, there is a problem that the data transfer capability is not improved.
[0006]
Therefore, as another method for improving the data transfer capability, there is a method of separately storing different types of data in a plurality of SDRAMs and independently controlling them.
[0007]
A memory control apparatus using such a method will be described below.
[0008]
In FIG. 5, the transfer request unit 501A to the transfer request unit 501C are inputted with data requiring processing from the outside or from the SDRAM described below. After the processing, the data is transferred to the SDRAM 510a and the SDRAM 510b or sent to an external device. Is output.
[0009]
When the transfer request units 501A to 501C try to perform a predetermined process or when the predetermined process is completed, an access request (start address, transfer size, transfer direction, read from the SDRAM 510a, SDRAM 510b, or write to the SDRAM). (Execution priority) is input to the memory control device 500.
[0010]
In the memory control device 500, the arbitration unit 505 that has received the access request requests access to a different memory device having a higher priority from the transfer requests from the three transfer request units 101A to 101C. Two requests are selected, and an access start request (start address, transfer size, transfer direction) corresponding to the two transfer requests is output to the command generation unit 506a and the command generation unit 506b.
[0011]
The command generation unit 506a outputs a chip selection signal CSa for controlling the SDRAM 510a and the command a in response to the access start request a output from the arbitration unit 505.
[0012]
The command generation unit 506b outputs a chip selection signal CSb and a command b for controlling the SDRAM 510b in response to the access start request b output from the arbitration unit 505.
[0013]
The SDRAM 510a and SDRAM 510b are synchronous dynamic random access memories that operate by inputting a command and an SDRAM selection signal (CSa or CSb) from the memory control device 504. As described above, the chip selection signals CSa and CSb and the commands a and b are input to the SDRAM 510a and the SDRAM 510b, and the data is transferred to the transfer request units 501A to 501C via the data transfer means 508a and 508b described below. The transfer will be executed.
[0014]
The data transfer means 508a inputs write data from one of the transfer request units 501A to 501C via the data bus and writes it to the SDRAM 510a via the memory data bus a when writing to the SDRAM 510a. At the time of reading, read data is input from the SDRAM 510a via the memory data bus a and transferred to one of the transfer request units 501A to 501C via the data bus.
[0015]
The data transfer unit 508b operates in the same manner as the data transfer unit 508a. However, the access target is the SDRAM 510b and the memory data bus b is used.
[0016]
With the configuration as described above, in the conventional memory control device, the arbitration means 505 has two priority requests from among the transfer requests from the three transfer request units 501A to 501C and requests access to different memory devices. By selecting a transfer request and controlling the above two accesses completely independently by the two command generation means 506a and 506b, it becomes possible to operate the two SDRAMs independently and simultaneously from a plurality of transfer request units. The memory bus band is improved when there is an access request to a different SDRAM.
[0017]
The transfer request units 501A to 501C, the memory control device 500, and the SDRAMs 510a and 510b configured as described above are applied to the following uses, for example.
[0018]
That is, for example, the transfer request unit 510A is connected to, for example, a DVD drive, and issues a write request to the DRAM 510a when compressed image data is input from the DVD drive. Based on this request, the memory control device 500 executes a write process to the DRAM 510a. The compressed image data written in this way is then transferred based on a read request from the transfer request unit 501B, for example, and is decoded into original image data by the transfer request unit 501B. When the decoding is completed, the transfer request unit 501B issues a write request to the DRAM 510b, and the original image data is transferred to the DRAM 510b based on this request. Next, the original image data stored in the DRAM 510b is transferred based on a read request from the transfer request unit 501C, and is output from the transfer request unit 501C to a television monitor or the like. Each of the above write request and read request is processed by the memory control device 500.
[0019]
[Problems to be solved by the invention]
However, the conventional memory control device requires a number of signal transmission signal lines as many as the number of SDRAMs, so that the number of signal lines between the memory control device and the SDRAM increases.
[0020]
Therefore, an object of the present invention is to reduce the number of signal lines between the memory control device and the memory device in a memory subsystem using a synchronous memory device such as an SDRAM even when the burst length is short. To provide a memory control device capable of improving the effective bus bandwidth of a memory.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, the present invention employs the following means. In other words, the arbitration means selects a plurality of transfer requests requesting access to different memory devices from a plurality of data transfer requests from a plurality of data transfer request units, and notifies the command generation means, as in the prior art. . The command generation means simultaneously generates memory device control commands corresponding to the selected data transfer requests. In addition, a rule determination unit is provided to determine whether or not the next command can be issued to each memory device based on the specifications of the memory device.
[0022]
The command selection means selects one of the memory control commands for the memory device that can issue the next command based on the determination of the rule determination means and the priority, and outputs the selected memory control command to a plurality of memory devices simultaneously. The chip selection signal for the memory device corresponding to the selected command is validated.
[0023]
As a result, command pins for a plurality of memory devices are shared, and the number of LSI pins can be reduced.
[0024]
In the above, each memory device operates individually based on a command obtained from a common command pin, but the command generation means issues one command corresponding to a plurality of memory devices, The plurality of memory devices can be operated simultaneously corresponding to common transfer data. As a result, large data can be divided and written in a plurality of memory devices, and the original data can be restored by simultaneously reading the divided and written data.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0026]
(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the memory control apparatus according to the first embodiment of the present invention.
[0027]
In FIG. 1, a predetermined number (three in this example) of transfer request units 101A to 101C are access requests (start address, transfer size, transfer direction) related to reading from or writing to SDRAM as in the conventional example. , Execution priority) is generated and input to the memory control device 100 described below.
[0028]
Arbitration means 103 of the memory control device 100 requests access to different SDRAMs having higher priority from the transfer requests from the predetermined number of transfer request units 101A to 101C, as in the conventional memory control device 500. The two transfer requests are selected, and an access start request (start address, transfer size, transfer direction) corresponding to the two transfer requests is output to the command generation means 105.
[0029]
Based on the two requests selected by the arbitration unit 103, the command generation unit 105 generates a command a and a command b corresponding to the two transfer requests and inputs them to the command selection unit 106.
[0030]
The command selection means 106 determines the command based on the information from the command issue rule determination means 109 described below (whether or not the command a and the command b can be issued) and the execution priority of the commands a and b. Two commands obtained from the generation means are selected one by one in a time-division manner and output to SDRAMs 110a and 110b from a set of command pins, and a chip selection signal CSa or CSb corresponding to the selected command is time-divisionally divided. Is enabled (Low in the example of FIG. 2).
[0031]
Note that the chip selection signal CSa is a selection signal for the SDRAM 110a, and the selection signal CSb is a selection signal for the SDRAM 110b, and is output from a set of pins corresponding to the SDRAMs 110a and 110b, respectively, as in the prior art. The
[0032]
This is because the operations of the data transfer means 107a and the data transfer means 107b are the same as in the prior art. The description is omitted here.
[0033]
The command issuance rule determination unit 109 generates information on whether or not the next command can be issued to the two SDRAMs according to the specifications of the SDRAM to be used, and outputs the information to the command selection unit 106.
[0034]
For example, when an SDRAM having CAS latency = 3 is used and an active command is issued to the SDRAM 110a (or 110b), command issuance to the SDRAM 110a (or 110b) is prohibited during the subsequent two cycles. Become. Accordingly, the command issuance rule determination unit 109 instructs the command selection unit 106 to prohibit access to the SDRAM 110a (or 110b) during the two cycles.
[0035]
FIG. 2 is a timing chart showing an example of operation timing of the memory control device according to the first embodiment.
[0036]
Hereinafter, further description will be given with reference to FIGS. 1 and 2.
[0037]
First, the transfer request unit 101A issues a 4-byte data read request from the memory device 110a, the transfer request unit 101B outputs a 4-byte data write request to the memory device 110b, and the execution priority is the transfer request. Assume that the access request of the unit 101A is higher. Under this situation, the arbitration unit 103 outputs an access start request for the SDRAM 110a and an access start request corresponding to the SDRAM 110b to the command generation unit 105 unless there is another transfer request with a higher execution priority.
[0038]
Further, the data bus width of the SDRAM 110a and the SDRAM 110b is 8 bits, CAS latency = 3, and burst length = 4.
[0039]
The command generation means 105 that has received the access start request generates an active command Aa to the SDRAM 110a and a read command Ra to the SDRAM 110a in this order as the command a, outputs them to the command selection means 106, and also as a command b The active command Ab to the SDRAM 110 b and the write command Wb to the SDRAM 110 b are generated in this order and output to the command selection means 106. Further, it is assumed that the command a is added with information that the command is executed with priority over the command b.
[0040]
The command selection means 106 first selects the command a in cycle 2 (see FIG. 2 (a)), and outputs the active command Aa to the SDRAMs 110a and 110b as shown in FIG. 2 (e). b) Activate the chip selection signal CSa as shown in FIG. As a result, the command a is accepted by the SDRAM 110a, but not accepted by the SDRAM 110b, and the activation of the SDRAM 110a is executed.
[0041]
As described above, when an active command is issued, command issuance to the SDRAM 110a (or 110b) is prohibited during the subsequent two cycles. Accordingly, in cycle 3, information indicating that command issuance to the SDRAM 110a is in a prohibited state is output from the command issuance rule determination unit 109, whereby the command selection unit 106 selects the command b corresponding to the SRAM 106. As shown in FIG. 2 (e), the active command Ab is output to the SDRAM 110b, and the chip selection signal CSb is activated as shown in FIG. 2 (d). Thereby, activation of the SDRAM 110b is executed.
[0042]
In cycle 4, information indicating that command issue is prohibited in both SDRAMs is output from the command issue rule determination means 109, and the command selection means 106 receives the chip selection signals CSa and CSb. Activate.
[0043]
Next, in response to the active command Aa issued in the cycle 2, the command issuance to the SDRAM 110a is enabled in the cycle 5, so the command selection means 106 selects the command a and sends the read command Ra to the SDRAM 110a. As a result, the SDRAM 110a outputs the read data r1, r2, r3, r4 having the burst length 4 to the memory data bus a from the cycle 8, and this data is transferred to the transfer request unit A by the data transfer means 107a. Is done. When a read command is input to the SDRAM 110a, the data to be read is once dropped in a buffer in the SDRAM 110a and then read. Accordingly, as shown in FIGS. 2E and 2F, data is read after a predetermined cycle (three cycles in this case) after the read command Ra is issued.
[0044]
Subsequently, in response to the active command Ab issued in the cycle 3, the command issuance to the SDRAM 110b is permitted in the cycle 6. Here, since the command a does not exist, the command selection means 106 selects the command b, and outputs the write command Wb to the SDRAM 110b. As a result, as shown in FIGS. The transfer means 107b outputs the write data w1, w2, w3, w4 input from the transfer request unit B from the cycle 6 to the memory data bus b.
[0045]
As described above, in the memory control device according to the first embodiment of the present invention, the command selection unit 106 inputs information on whether or not a command is issued from the command issuance rule determination unit 109, and the information and the execution priority One of the command a to the SDRAM 110a and the command b to the SDRAM 110b is selected and output as a command to the two SDRAMs 110a and 110b, and the SDRAM selection signal CSa or By making CSb active, two SDRAMs are independently controlled by a common command signal.
[0046]
As a result, since the command signals to the two SDRAMs 110a and 110b can be shared, the number of signal lines between the memory control device and the SDRAM can be reduced.
[0047]
In the first embodiment, the number of transfer request units is three. However, the number of transfer request units may be two or four or more. Although there are two SDRAMs, three or more configurations may be used.
[0048]
(Embodiment 2)
FIG. 3 is a block diagram showing the configuration of the memory control device according to the second embodiment of the present invention.
[0049]
In FIG. 3, when there is a transfer request from the transfer request unit 101C, for example, via the arbitration unit 103, the command generation unit 301 selects only the transfer request and generates a command a. At this time, attribute information indicating that the two SDRAMs 110a and 110b are simultaneously accessed is added to the command a. For example, when there is a transfer request from the transfer request units 101A and 101B, two transfer requests are selected together, and commands a and b corresponding to the two transfer requests are generated. At this time, attribute information for individually accessing a specific SDRAM is added to the commands a and b.
[0050]
When the command generation unit 301 outputs a command having attribute information indicating that individual SDRAMs 110a and 110b are individually accessed from the command generation unit 301 (the command b in this example), the command issue rule determination unit Based on the information from 109 (whether command a and command b can be issued) and the execution priority of command a and command b, one of the two commands input from command generation means 301 is selected. Are output to the SDRAM 110a or 110b, and the SDRAM selection signal (CSa or CSb) corresponding to the selected command is validated. The subsequent operation procedure is the same as that described in the above embodiment with reference to FIG.
[0051]
On the other hand, when a command having attribute information indicating that two SDRAMs are simultaneously accessed (command a in this case) is output from the command generation unit 301, information (command a, command b) from the command issuance rule determination unit 109 is output. The command a input from the command generation means is output to the SDRAMs 110a and 110b as it is, and the two chip selection signals CSa and CSb are simultaneously enabled.
[0052]
Since the operation of the data transfer means 303a when transferring data between the transfer request unit 101A or the transfer request unit 101B and the SDRAMs 110a and 110b is the same as that in the first embodiment, description thereof is omitted here.
[0053]
When data is transferred from the transfer request unit 101C to the SDRAMs 110a and 110b, the data transfer unit 303a receives the notification from the command selection unit 302 and divides the data into both the memory data bus a and the memory data bus b. Are simultaneously transferred to the SDRAMs 110a and 110b. In this division, for example, data of 1 byte is alternately distributed to the SDRAMs 110a and 110b, and each is written to the same address of the SDRAMs 110a and 110b. However, since this method is already known, detailed description is omitted here. To do.
[0054]
Further, when data is transferred from the SDRAMs 110a and 110b to the transfer request unit 101C, the data transfer means 303a is notified from the command selection means 302 and obtained from both the memory data bus a and the memory data bus b. The divided data is restored and transferred to the transfer request unit C. Since the restoration method here is already known, the description is omitted here.
[0055]
The data transfer means 303b operates in the same manner as in the first embodiment described above when transferring data between the transfer request unit 101A or the transfer request unit 101B and the SDRAMs 110a and 110b. Further, it is not used when transferring data between the transfer request unit 101C and the SDRAMs 110a and 110b.
[0056]
The function of the command issuance rule determination unit 109 is the same as that in the first embodiment.
[0057]
FIG. 4 is a timing chart illustrating an example of operation timing of the memory control device according to the second embodiment.
[0058]
Hereinafter, a description will be given with reference to FIGS. 3 and 4.
[0059]
First, the transfer request unit 101A outputs a read of 4-byte data from the SDRAM 110a as an access request, the transfer request unit 101B outputs a read of 4-byte data from the SDRAM 110b as an access request, and the transfer request unit 103C is output from the SDRAM 110a. 16-byte data write to both the SDRAM 110b and the SDRAM 110b as an access request, and the execution priority is an access request output from the transfer request unit C, an access request output from the transfer request unit A, and an output from the transfer request unit B. Assume that the access requests are in descending order.
[0060]
The memory data bus width of the SDRAM 110a and SDRAM 110b is 8 bits, CAS latency = 3, and burst length = 4. In this case, as shown in FIG. 4, first, data of the transfer request unit C having the highest execution priority is transferred to the SDRAMs 110a and 110b.
[0061]
At this time, as shown in FIG. 4 (e), first in two cycles, the active command Aab to both the SDRAM 110a and the SDRAM 110b is output from the command selection means 302 and shown in FIGS. 4 (c) and 4 (d). As described above, the chip selection signal CSa and the chip selection signal CSb are simultaneously activated. In five cycles after the third cycle, a 16-byte data write access request Wab is output from the command selection means 302, and at this time, the chip selection signal CSa and the chip selection signal CSb are simultaneously activated.
[0062]
When the command Aab is received, the two SDRAMs 110a and 110b are simultaneously activated, and the command Aab is also input to the data transfer means 303a, and as shown in FIGS. 4 (f) and 4 (g). SDRAM 110a and SDRAM 110b operate simultaneously, and data transfer means 303a divides the data from transfer request unit C into memory data bus a and memory data bus b and transfers them to SDRAM 110a and SDRAM 110b (cycles 5 to 5). Cycle 12). In FIG. 4, the data W1, W2,.
[0063]
Since the 16 bytes are written to the SDRAM 110a and 110b buffers, it is necessary to write from the buffer to the SDRAM body, and precharge is activated for both SDRAMs 110a and 110b in cycle 13. (See cycle 15).
[0064]
Next, in cycle 16 and later, the transfer from the SDRAM 110a to the transfer request unit 101A and the transfer from the SDRAM 110b to the transfer request unit B are executed in parallel with a shift of one cycle (cycle 16 to cycle 28). As described above, in the memory control device according to the second embodiment of the present invention, when the data transfer size is large according to the data transfer size per time for the SDRAM, the data is parallel to the plurality of SDRAMs. When a plurality of SDRAMs are operated simultaneously to perform one data transfer and the data transfer size is small, the data is stored only in one SDRAM and the plurality of SDRAMs are independently controlled to control the plurality of SDRAMs. Data transfer at the same time.
[0065]
This embodiment is effective for transferring large data, and the burst length is also increased to minimize the overhead. In addition, the command output from the command generation means includes information on whether to use a plurality of (two) SDRAMs simultaneously or individually, so that the SDRAM can minimize overhead according to the length of the burst length. Can be selected, and the execution bus bandwidth of the memory can be improved.
[0066]
Further, in this embodiment, two SDRAMs are accessed based on a transfer request from a specific transfer request unit. However, the present embodiment is not limited to this, and for example, a specific Data indicating that two DRAMs are used simultaneously can be written in the data, and the two DRAMs can be used simultaneously regardless of which transfer request unit is used for the data. Although two DRAMs are used at the same time, it is needless to say that more DRAMs may be used at the same time.
[0067]
【The invention's effect】
As described above, the present invention can reduce the number of pins of the memory control device and the number of signal lines between the memory control device and the SDRAM by sharing the command pin to the SDRAM.
[0068]
In addition, storage in an SDRAM that minimizes overhead is made possible by selecting whether to use a plurality of memory devices individually or in common according to the size of the data and the length of the burst length. The method can be selected, which can improve the execution bus bandwidth of the memory.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a memory control device according to a first embodiment.
FIG. 2 is a timing chart showing an operation procedure of the memory control device according to the first embodiment.
FIG. 3 is a block diagram showing a configuration of a memory control device according to a second embodiment.
FIG. 4 is a timing chart showing an operation procedure of the memory control device according to the second embodiment.
FIG. 5 is a block diagram showing an example of a configuration of a conventional memory control device.
[Explanation of symbols]
101A, 101B, 101C... Transfer request unit
105: Command generation means
106: Command selection means
107a, 107b ... Data transfer means
109: Command issuance rule determination means
301: Command generation means
302: Command selection means
303a, 303b ... Data transfer means

Claims (3)

In a memory control device that controls data transfer between a plurality of data transfer request units and a plurality of dynamic memory devices in synchronization with a clock,
Arbitration means for selecting a plurality of transfer requests requesting access to different memory devices from a plurality of data transfer requests from the plurality of data transfer request units;
Command generation means for simultaneously generating memory device control commands corresponding to a plurality of data transfer requests selected by the arbitration means;
Rule determining means for determining whether or not the next command can be issued to each memory device based on the specifications of the memory device;
Based on the determination and priority of the rule determination means, one of the memory control commands for the memory device that can issue the next command is selected and simultaneously output to a plurality of memory devices, and the selected command And a command selection means for enabling a chip selection signal for the memory device corresponding to the memory control device. The command includes a request for simultaneous access to a plurality of memory devices, the command selection means for simultaneously enabling the chip selection signals corresponding to the plurality of memory devices, and data of a predetermined length as described above The memory control device according to claim 1, wherein the memory control device is divided into the number of memory devices selected at the same time and written to the plurality of memory devices, and the divided data is simultaneously read from the plurality of memory devices and restored. The memory control device according to claim 2, wherein a plurality of memory devices are operated simultaneously in response to a data transfer request from a specific data transfer request unit.

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