JPH0628246A - Storage device - Google Patents

Abstract

PURPOSE:To increase the use efficiency of the high-speed storage part and perform high-speed access at relatively a low cost without making the storage capacity of the device small by placing data which are high in use frequency in the high-speed storage part by a storage control part. CONSTITUTION:When the storage control part 10 inputs a request command, an address, and data from a processor through input terminals 1, 3, and 4, a request accepting circuit 11 outputs control signals to a timing control circuit 12, an address control circuit 16, and a data control circuit 17 to perform writing/reading operation at the high-speed storage part 30 or storage part 40 corresponding to the command. When an address area which is high in use frequency is already known, address avocation information is inputted to an avocation setting circuit 13 so as to store the data which are high in use frequency in the high-speed storage part 30. An address converting circuit 15 holds the setting from the allocation setting part 13 and converts the address area which is high in use frequency into addresses of the high-speed storage part 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device.

[0002]

2. Description of the Related Art Heretofore, a storage device of this type has no high-speed storage part at all or has a high-speed storage part.

[0003]

The above-mentioned conventional storage device, if it does not have a high-speed storage unit, has no means for high-speed access even for frequently used data, which is a bottleneck in the overall processing speed. If the storage unit is configured with a high-speed storage unit, there is a drawback that the storage capacity cannot be large and the cost is high.

[0004]

A storage device of the present invention has a high-speed storage portion and a storage control portion in addition to an ordinary storage portion,
Further, in the storage control unit, allocation setting means for address allocation of the high-speed storage portion, address conversion means, data transfer means for transferring data between the normal storage portion and the high-speed storage portion, and the number of accesses to each data are counted. It has a counting means, an access number setting means, a count value and a set access number comparing means, and a refresh control means for executing the data transfer instead of or in parallel with the refresh operation.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
When the storage controller 10 fetches requests / commands, addresses, and data from the processor from the input terminals 1, 3, and 4, the request acceptance circuit 11 controls the timing control circuit 12, the address control circuit 16, and the data control circuit 17. A signal is output, and the write / read operation according to the command is executed on the high-speed storage unit 30 or the storage unit 40. Since the processing speed is improved by storing the data frequently accessed by the processor in the high-speed storage unit 30, when the frequently used address area is known in advance, the address allocation information is allocated from the input terminal 2. Input to the setting circuit 13. The address conversion circuit 16 holds the setting from the allocation setting circuit 13 and converts the frequently used address area into the address of the high speed storage unit 30.

When the frequency of use for each data is known at the time of writing from the processor, allocation information sent from the processor side in synchronization with the data is fetched from the input terminal 2 to the allocation setting circuit 13. Allocation setting circuit 13
Outputs control signals to the address conversion circuit 15 and the request acceptance circuit 11, respectively. The address conversion circuit 16 converts the address into the address of the high speed storage unit 30 by the output from the allocation setting circuit 15, and the request reception circuit 11 controls the timing control circuit 12, the address control circuit 16 and the data control circuit 17. Writing to the high speed storage unit 30 is executed.

At this time, the address conversion circuit 16 holds the converted address information until the allocation setting circuit 13 releases it. Further, when it is known that the frequency of use of the data decreases after the reading, the allocation cancellation information is input from the processor side to the allocation setting circuit 13 via the input terminal 2 in synchronization with the request at the time of reading. The allocation setting circuit 13 releases the corresponding address of the address conversion circuit 15 from the conversion target, and the request reception circuit 11
Via the timing control circuit 12, the address control 16,
The data control circuit 17 is controlled to transfer read data from the high speed storage unit 30 to the processor via the input / output terminal 5 and move the data read from the high speed storage unit 30 to the storage unit 40.

When setting / releasing each data to / from the high-speed storage unit 30 asynchronously with the access from the processor, the allocation release information for each data is fetched into the allocation setting circuit 13 via the input terminal 2. The allocation setting circuit 13 sends the request receiving circuit 11 to the high-speed storage unit 30 and the storage unit 40.
Start data movement with.

The request accepting circuit 11 controls the timing control circuit 12, the address control circuit 16 and the data control circuit 17 to read out data from the storage unit 40 and transfer data to the high-speed storage unit 30 when set. Writing is performed, and when the setting is released, data is read from the high speed storage unit 30 and data is written to the storage unit 40. The allocation setting circuit 13 also clears the conversion information of the corresponding address in the address conversion circuit 15.

In order to use the high speed storage section 30 efficiently,
It is necessary to store data according to the actual frequency of use, and to dynamically move data between the high-speed storage unit 30 and the storage unit 40 in this device in order to release the processor from the burden of the setting. . Therefore, the count circuit 18 monitors the access frequency of each data or address area within a certain period. When the reference access count set in the access count setting circuit 20 from the input terminal 5 and each count value of the count circuit 18 are compared by the comparison circuit 19, and the count count in the fixed period exceeds the reference access count, the comparison circuit An output signal is output from 19 to the allocation setting circuit 13.

The corresponding data or address area is the storage unit 4.
If it is above 0, the allocation setting circuit 13 activates the request acceptance circuit 11 to move the data or the address area to the high-speed storage unit 30, and sets the address allocation to the address conversion circuit. To do.
Further, when the access to each data or address area allocated on the high-speed storage unit 30 is less than or equal to the reference access frequency, the comparison circuit 19 outputs to the allocation setting circuit 13,
The allocation setting circuit 13 releases the setting to the address conversion circuit 15 and the high-speed storage unit 30 to the request receiving circuit 11.
To activate storage of data from the storage unit 40 to the storage unit 40. As a result, a state in which frequently used data or address areas are allocated to the high speed storage unit is maintained.

It is necessary to perform the above-mentioned data movement during the unused period of each storage unit in order to avoid conflict with access by the processor. If the storage element used in the storage unit is a dynamic random access memory (DRAM), it is necessary to perform a refresh operation at regular intervals, and when the above data movement occurs, the allocation control circuit 13 performs refresh control. By outputting the control signal to the circuit 14 and performing the data transfer instead of the refresh operation or in parallel with the refresh operation at the refresh execution time, access conflict with the processor can be avoided.

[0013]

As described above, the present invention has a normal large-capacity storage unit and a relatively small-capacity high-speed storage unit, and the storage control unit places frequently used data in the high-speed storage unit. As a result, there is an effect that it is possible to realize a storage device that performs high-speed access at a relatively low cost without increasing the use efficiency of the high-speed storage unit and reducing the storage capacity of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 to 6 input / output terminals 10 storage control unit 11 request reception circuit 12 timing control circuit 13 priority setting circuit 14 refresh control circuit 15 allocation setting circuit 16 address conversion circuit 17 address control circuit 18 data control circuit 19 count circuit 20 access count setting Circuit 21 Comparison circuit 30 High-speed storage unit 40 Storage unit

Claims (7)

[Claims] 1. A storage device comprising an ordinary storage unit, a small-capacity high-speed storage unit that can be accessed at high speed, and a storage control unit that controls the storage unit and the high-speed storage unit. 2. The storage device according to claim 1, wherein the storage control unit has address conversion means for allocating the high-speed storage part to an arbitrary address in the storage device, and allocation setting means for making settings for address conversion. . 3. The data transfer means for allocating / setting / releasing individual stored data to / from the high-speed storage unit, and the data transfer unit for transferring data between the normal storage unit and the high-speed storage unit. The storage device according to claim 2, further comprising: 4. The storage device according to claim 3, wherein the allocation setting means performs allocation setting / cancellation in synchronization with a write or read operation. 5. The storage device according to claim 3, wherein the allocation setting means performs allocation setting / cancellation asynchronously with writing and reading operations. 6. The storage control unit compares a counter that counts the number of times of access to each data stored in each storage unit within a certain period, and a comparison that compares the count value of the counter with the set number of accesses. 6. An access number setting means for setting an access number for comparing with the count value by the comparing means, wherein the allocation setting means sets and cancels the allocation based on a comparison result of the comparing means. The storage device described. 7. The storage control unit includes refresh control means for executing data transfer from the high-speed storage unit to the normal storage unit at the time of setting and releasing allocation, instead of or in parallel with the refresh operation during the refresh operation. 7. The storage device according to claim 4, wherein the storage device has contention to avoid contention between the data transfer and an access from a processor.