JP3230489B2 - Memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (R) requiring data retention by a periodic refresh operation.
The present invention relates to an AM memory control circuit.

[0002]

2. Description of the Related Art In testing a semiconductor memory such as a dynamic RAM, the test time generally increases in proportion to the memory capacity. In recent years, with a significant increase in memory capacity,
The test time has also increased, and it has been required to reduce the test time. In order to respond to this request, for example, as disclosed in Japanese Patent Application Laid-Open No. 5-107314, data is read out for testing at a cycle shorter than a cycle of a periodic refresh operation for each memory element. A method has been proposed in which this data is temporarily stored outside to avoid conflict with the refresh operation.

[0003]

However, this prior art has the following problems. That is, there is a disadvantage that a special circuit for temporarily storing data read from the memory element for the test is required to avoid a refresh operation that is periodically performed. Also,
During the execution of the refresh operation that is periodically performed, the operation for the test needs to be interrupted, and the test time cannot always be shortened.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and provides a memory control circuit which does not require a special circuit for temporarily storing data and which can shorten a memory test time.

[0005]

Means for Solving the Problems The invention described in claim 1, in the memory control circuit for holding the data periodically to refresh dynamic RAM, the refresh timing generator for generating timings for signal of the refresh operation Circuit, a refresh operation stop circuit for stopping a refresh operation executed in accordance with the timing signal from the refresh timing generation circuit by a refresh operation stop instruction, and a refresh operation forcibly executing the refresh operation in response to a refresh operation execution instruction Circuit and execution of the refresh operation
A refresh address that generates a refresh address
A memory control circuit including a memory address generation circuit .

[0006]

According to a second aspect of the present invention, there is provided the memory control circuit according to the first aspect, further comprising a contention arbitration circuit for controlling a memory read or write instruction and the timing of the refresh operation. is there.

[0008] According to a third aspect of the invention, the conflict arbitration circuit is a memory control circuit according to claim 2, characterized in that priority is given to the the refresh operation than the read or write command.

[0009] According to a fourth aspect of the invention, the refresh operation execution circuit to any one of 3 claims 1, characterized in that sequentially executing a plurality of times the refresh operation by the refresh operation execution instruction It is a memory control circuit described. The invention according to claim 5 provides a
Data is retained by periodically refreshing the RAM
Memory control circuit that performs the refresh operation.
Refresh timing generation that generates timing signals
Circuit and before the refresh timing generation circuit
Refresh operation performed according to the timing signal
To be stopped by a refresh operation stop instruction
By the refresh operation stop circuit and the refresh operation execution instruction.
Refresh operation to force the refresh operation
And a refresh operation execution circuit.
Is refreshed by the refresh operation execution instruction.
Mesh operation is performed a plurality of times consecutively.
It is a memory control circuit.

[0010]

FIG. 1 is a block diagram of a memory control circuit according to an embodiment of the present invention. The memory control circuit 1 is connected to a dynamic RAM 2 that needs to hold data by a periodic refresh operation, and refreshes the dynamic RAM 2 periodically. When testing the dynamic RAM 2, a memory tester 3 is connected to the dynamic RAM 2 and the memory control circuit 1.

In the memory control circuit 1, a refresh timing generation circuit 4 for generating a timing signal for a periodic refresh operation of the dynamic RAM 2 is provided.
And a refresh operation execution circuit 5 for executing a refresh operation. A refresh operation stop circuit 5 is provided between the refresh timing generation circuit 4 and the refresh operation execution circuit 5, and the refresh operation stop circuit 5 is used when the dynamic RAM 2 is tested. The periodic refresh operation is stopped by the refresh operation stop instruction signal from the control unit 3. When testing the dynamic RAM 2, the refresh operation execution circuit 5 is also connected to the memory tester 3 and controlled by a refresh operation execution instruction signal.

A refresh address generation circuit 7 is provided downstream of the refresh operation execution circuit 5. This refresh address generation circuit 7 further includes
The contention arbitration circuit 8 is connected to an address line and a control line. Upon receiving the refresh timing signal from the refresh operation execution circuit 5, the refresh address generation circuit 7 outputs a refresh address signal and a control signal to the subsequent competition arbitration circuit 8. The contention arbitration circuit 8 is connected to the dynamic RAM 2 by an address line and a control line, and outputs an address signal and a control signal to the dynamic RAM 2. The competition arbitration circuit 8 is connected to the memory tester 3 by an address line and a control line when the dynamic RAM 2 is tested.

Next, the operation of the present embodiment will be described. During normal operation of the dynamic RAM 2, the memory control circuit 1
The internal refresh timing generation circuit 4 generates
A periodic refresh operation is performed by the periodic refresh timing signal. At this time, FIG.
Is not connected to the memory control circuit 1 and the dynamic RAM 2.

The periodic refresh timing signal generated by refresh timing generation circuit 4 is transmitted to refresh address generation circuit 7 via refresh operation stop circuit 6 and refresh operation execution circuit 5. At this time, the refresh operation stop circuit 6 and the refresh operation execution circuit 5 simply pass the refresh timing signal.

Upon receiving the refresh timing signal, the refresh address generating circuit 7 outputs the refresh address from the address line while counting up the refresh address in order to sequentially refresh each address of the dynamic RAM 2, and synchronizes the refresh signal with the refresh address. Is output from the control line.

The contention arbitration circuit 8 arbitrates the contention between the read / write operation and the refresh operation when a read / write operation of the dynamic RAM 2 is requested from the outside via an address line and a control line. That is, when only a read / write operation request is made, this request is sent to the dynamic RA via the address line and the control line.
Transmit to M2. Even in the case of only a refresh operation request, this request is transmitted to the dynamic RAM 2. However, when the read / write operation is requested at the same time as the refresh operation, the read / write operation is put on standby, and the refresh operation is prioritized.

Next, when testing the dynamic RAM 2, the refresh operation stop circuit 6 is operated by the refresh operation stop circuit 6 in accordance with the refresh operation stop instruction signal input from the externally connected memory tester 3. And the refresh operation execution circuit 5 outputs the refresh timing signal at a timing determined by the refresh operation execution instruction signal input from the memory tester 3.

The refresh address generation circuit 7 outputs the refresh address from the address line while counting up the refresh address in order to sequentially refresh each address of the dynamic RAM 2 in accordance with the refresh timing signal output from the refresh operation execution circuit 5,
A refresh signal is output from the control line in synchronization with this.

When a request for a test operation as a read / write operation of the dynamic RAM 2 is input from the externally connected memory tester 3, the contention arbitration circuit 8 transmits the request to the dynamic RAM 2. When the refresh operation is requested, the request is transmitted to the dynamic RAM 2.

At the time of testing the dynamic RAM 2, the timing of the refresh operation is controlled by the memory tester 3, so that the memory tester 3 can be set so that the refresh operation does not conflict with the test operation. However, if there is a conflict, the test operation is put on standby.

Next, the operation timing of this embodiment will be described. During a normal operation, as shown in FIG. 2, a refresh operation is periodically performed by a refresh timing signal generated by a refresh timing generation circuit 4 in the memory control circuit 1, so that this refresh operation and an external device or the like are performed. There is a possibility that the read / write operation that is input from the memory device may compete with the read / write operation. If there is a conflict, the read / write operation is suspended, so that a waiting time occurs in the read / write operation.

On the other hand, when testing the dynamic RAM 2, as shown in FIG. 3, the timing of the refresh operation can be freely determined by the memory tester 3 connected externally, so that the refresh operation and the test operation conflict. Can be set so that no test time is lost.

Also, the refresh operation of many different addresses is continuously performed, during which the dynamic RAM 2
Performing processing that does not require memory access, such as confirmation of data read from the memory, can further reduce the test time.

[0024]

According to the present invention, the memory control circuit for holding the data periodically to refresh dynamic RAM, a refresh timing generator for generating a timings for signal of the refresh operation, the refresh timing generator A refresh operation stop circuit for stopping a refresh operation executed in accordance with the timing signal according to a refresh operation stop instruction;
A refresh operation execution circuit for forcibly executing the refresh operation according to a refresh operation execution instruction ;
The refresh address is specified by the refresh operation execution instruction.
A refresh address generation circuit for generating a refresh operation, the refresh operation can be executed at an arbitrary timing under the control of an external device such as a memory tester, thereby avoiding a conflict between the refresh operation and the test operation. Thus, the memory test time can be reduced. In addition, there is no need to temporarily store data read from the memory element by avoiding the refresh operation, and a special circuit for this is not required.

Further, if the refresh operation execution circuit executes the refresh operation a plurality of times in response to the refresh operation execution instruction, memory access such as confirmation of data read from the memory in parallel with the operation is performed during the refresh operation. Since you can perform unnecessary processing,
Further, the test time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing timing during normal operation.

FIG. 3 is a diagram showing timing at the time of a memory test.

[Explanation of symbols]

1 Memory control circuit 2 Dynamic RA
M 3 memory tester 4 refresh timing generation circuit 5 refresh operation execution circuit 6 refresh operation stop circuit 7 refresh address generation circuit 8 competition arbitration circuit

Claims (5)

(57) [Claims] 1. A memory control circuit for holding the data periodically to refresh dynamic RAM, a refresh timing generator for generating a timings for signal of the refresh operation, the timing signal from the refresh timing generator A refresh operation stop circuit for stopping the refresh operation executed in accordance with the refresh operation stop instruction, a refresh operation execution circuit for forcibly executing the refresh operation in accordance with the refresh operation execution instruction , and a refresh operation in response to the refresh operation execution instruction.
And a refresh address generation circuit for generating a dress . 2. A memory read or write instruction,
2. The memory control circuit according to claim 1, further comprising a contention arbitration circuit for controlling a timing of the refresh operation. 3. The memory control circuit according to claim 2 , wherein said contention arbitration circuit prioritizes said refresh operation over said read or write instruction. Wherein said refresh operation execution circuit according to claim 1 of <br/> stone 3, characterized by continuously executed a plurality of times the refresh operation by the refresh operation execution instruction Memory control circuit. 5. A method for periodically refreshing a dynamic RAM.
In a memory control circuit for holding data by performing a refresh operation, a reset signal for generating a timing signal for the refresh operation is generated.
A fresh timing generation circuit and the timing from the refresh timing generation circuit;
Refresh operation performed according to the
Refresh operation stopped by the flash operation stop instruction
The refresh operation by the stop circuit and the refresh operation execution instruction.
Refresh operation execution circuit
The refresh operation execution circuit is configured to perform the refresh operation.
The refresh operation is repeated several times
A memory control circuit characterized in that the memory control circuit executes the program.