JP4593220B2 - Memory access control method and method, and shared memory access control method and method - Google Patents

Description

  The present invention relates to a memory access control method and method, and a shared memory access control method and method, and in particular, a memory access control method and method for controlling a plurality of banks divided into several groups. And a shared memory access control method and method.

In a shared main memory in a shared memory multiprocessor system, a storage element used for the shared memory is a large capacity and inexpensive SDRAM (Synchronous).
Dynamic RAM) is the mainstream.

  However, the speed difference between the shared memory access instruction issue rate of the processor and the storage element is large.

  In particular, as the number of processors increases, the difference increases and becomes a bottleneck in system performance.

  Therefore, the memory request is buffered on the memory system side, the busy of the bank accessed by the selected request is checked, and if it is busy, the request by the exclusive memory access instruction is overtaken and accessed. There is a memory access control system (see Patent Document 1).

  On the other hand, in recent years, there is a type of RAM element having a configuration in which a plurality of bank groups can be accessed simultaneously within a single RAM element.

Japanese Patent Laid-Open No. 10-333979

  In a computer system including a plurality of CPUs and a shared main memory (hereinafter referred to as a shared MMU), when the memory access method including the bank check and the overtaking control described above is combined with a memory module composed of the RAM element of the type, the access The above difference is somewhat improved.

  However, there is room to further improve the shared MMU throughput.

  That is, the memory access method using the bank check and exclusive instruction overtaking has only one request output line to the memory control unit.

  As shown in FIG. 8, in the case of a bank configuration in which a control LSI and a RAM are physically connected by a plurality of signal lines (hereinafter, this physical unit is referred to as a channel) in the memory control unit, a plurality of bank access waits are placed in the request buffer. The request stays.

  In other words, in the case where there are a plurality of requests that can be output in parallel to each of a plurality of channels, there is a problem that access to different memory channels cannot be performed in parallel.

  That is, it can be said that there is room for improving the memory access efficiency by increasing the access frequency to the memory.

  Here, as means for realizing simultaneous access to different channels, the bank check and exclusive instruction overtaking control circuits are provided for each channel by simply dividing the memory control port, and data is transferred from the CPU to the MMU. A configuration in which the configuration of the crossbar switch to be transferred is the number of CPUs * the number of memory ports is conceivable.

  However, such a configuration leads to an increase in cost due to an increase in the amount of hardware.

  Further, not only the shared main storage device but also a main storage device that receives a high-frequency access request has the same problem.

  A first memory access control system according to the present invention is a memory access control system in which a memory module has a plurality of banks, and the plurality of banks are divided into several groups for control, and the memory control means for each bank group And a request buffer that stores a memory request in which the access destination bank is busy, and a bank to be accessed is busy for each bank group with respect to a memory request stored in the request buffer and a newly received memory request. And a means for selecting a memory request that is no longer in a state and issuing it to the corresponding memory control means.

  A second memory access control system according to the present invention is a memory access control system in which a memory module has a plurality of banks, and the plurality of banks are divided into several groups for control, and the memory control means for each bank group A bank busy counter for each bank that manages the busy state of each bank, a request buffer that stores a memory request that does not meet a predetermined selection condition, or whether the access destination bank is busy, or the request Bank check means for checking the busy status of the access destination bank by referring to the bank busy counter for the memory request stored in the buffer and the newly received memory request, and the access destination checked by the bank check means Bank is busy One memory request that is no longer in condition to select for each of the bank group, characterized by comprising a means for issuing to the corresponding memory control unit.

  According to a third memory access control method of the present invention, in the second memory access control method, the bank busy counter counts when a memory request for accessing a corresponding bank is issued to each memory control means. A busy state is started, and when the predetermined value corresponding to the type of request is reached, the busy state of the counter is released.

  According to a fourth memory access control method of the present invention, in the second memory access control method, the selection condition is to access the memory request stored in the request buffer means and a newly received memory request. The memory request is divided into the groups in the previous bank, the memory requests are given priority in each group, and the memory request having the highest priority is selected.

  According to a fifth memory access control method of the present invention, in the second memory access control method, each of the request buffers stores one piece of request information, and the number is a priority on request issuance. A plurality of word storage units, and a means for storing newly received memory requests that are not to be issued at that time in the youngest word storage unit among the word storages that are free or are expected to be free in the next cycle And, when issuing a request during storage, for each word storage unit storing request information, the number of request information issued included in the word storage unit and the word storage unit on the lower number side is one or more. If so, specify the number of request information sequences stored in the word storage unit that is older than the word storage unit and not to be issued. Characterized in that it comprises a means for transferring the request information at the position in the word storage unit to be.

  The sixth memory access control system of the present invention is characterized in that, in any of the first to fifth memory access control systems, the bank group is divided into two groups, an odd bank group and an even bank group. And

  A first memory access control method according to the present invention is a memory access control method in which a memory module has a plurality of banks, and the plurality of banks are divided into several groups for control, and the memory control procedure for each bank group And a procedure for temporarily storing a memory request in which an access destination bank is busy, and a bank to be accessed is busy for each bank group with respect to the temporarily stored memory request and a newly received memory request. And a procedure for selecting a memory request that has disappeared and passing it to a corresponding memory control procedure.

  A second memory access control method of the present invention is a memory access control method in which a memory module has a plurality of banks and the plurality of banks are divided into several groups for control, and the memory control procedure for each bank group And a procedure for counting the elapsed cycles from the start of access to each bank to the period according to the access type and managing the busy state of each bank, and whether the bank to be accessed is busy or predetermined Check the busy status of the access destination bank by referring to the result of the managing procedure for the temporary storage of the memory request that does not match the selection condition and the temporarily stored memory request and the newly received memory request. Bank check procedure and the bank check procedure One memory request access destination bank is no longer busy, select for each of the bank group, and having a procedure to be passed to the corresponding memory control procedure.

  A third memory access control method according to the present invention is characterized in that, in the first or second memory access control method, the bank groups are two groups of an odd bank and an even bank. .

  A first shared memory access control system according to the present invention is a shared memory access control system in which a memory module is configured in a plurality of banks with a shared memory accessed by a plurality of processors, and the plurality of banks are divided into several groups and controlled. A memory control unit for each bank group, a request buffer for storing a memory request in which an access destination bank is busy, a memory request stored in the request buffer, and a newly received memory request And a means for selecting, for each bank group, a memory request in which a bank to be accessed is no longer busy, and issuing the selected memory request to a corresponding memory control means.

  A second shared memory access control system according to the present invention is a shared memory access control system in which a memory module is configured in a plurality of banks with a shared memory accessed by a plurality of processors, and the plurality of banks are divided into several groups and controlled. The memory control unit for each bank group, the bank busy counter for each bank that manages the busy state of each bank, and the access destination bank is busy or meets a predetermined selection condition. A request buffer for storing a memory request not to be executed, and a bank check means for checking a busy state of an access destination bank by referring to the bank busy counter for a memory request stored in the request buffer and a newly received memory request And the bank check One memory request checked accessed bank is no longer busy by means selects for each of the bank group, characterized by comprising a means for issuing to the corresponding memory control unit.

  According to a third shared memory access control method of the present invention, in the second shared memory access control method, the bank busy counter issues a memory request for accessing a corresponding bank to each memory control means. Counting is started to be in a busy state, and the busy state of the counter is canceled when a predetermined value corresponding to the type of request is reached.

  According to a fourth shared memory access control method of the present invention, in the second shared memory access control method, the selection condition includes the memory request stored in the request buffer and a newly received memory request. The access request bank is divided into the groups, the priority is given to the memory requests in each group, and the memory request having the highest priority is selected.

  According to a fifth shared memory access control system of the present invention, in the second shared memory access control system, each of the request buffers can store one request information, and the number is a priority in issuing a request. Means for storing a plurality of word storages in order and a memory request that is newly received and not issued at that time in the youngest word storage among the word storages that are free or are expected to be free in the next cycle And, when issuing a request during storage, for each word storage unit storing request information, the number of request information issued included in the word storage unit and the word storage unit on the lower number side is one or more. If so, the number of request information sequences stored in the word storage unit on the older side than the word storage unit and not to be issued Characterized in that it comprises a means for transferring the request information in the location specified in the word storage unit.

  According to a sixth shared memory access control system of the present invention, in any of the first to fifth shared memory access control systems, the bank group is divided into an odd bank group and an even bank group. It is characterized by.

  A first shared memory access control method according to the present invention is a shared memory accessed by a plurality of processors, and a memory module has a plurality of banks, and the plurality of banks are divided into several groups and controlled. A memory control procedure for each bank group, a procedure for temporarily storing a memory request in which an access destination bank is busy, and the temporarily stored memory request and a newly received memory request. For each bank group, there is a procedure for selecting a memory request in which a bank to be accessed is no longer busy and passing it to a corresponding memory control procedure.

  A second shared memory access control method according to the present invention is a shared memory accessed by a plurality of processors, wherein the memory module has a plurality of banks, and the plurality of banks are divided into several groups and controlled. A memory control procedure for each bank group, a procedure for counting elapsed cycles from the start of access to each bank to a period according to the access type, and managing the busy state of each bank, The procedure for temporarily storing a memory request that is in a busy state or not satisfying a predetermined selection condition, and the busy state of the access destination bank with respect to the temporarily stored memory request and the newly received memory request Check the bank check by referring to the result of the managing procedure And a procedure for selecting, for each bank group, one of the memory requests whose access destination bank checked by the bank check procedure is no longer busy and passing it to the corresponding memory control procedure. Features.

  A third shared memory access control method according to the present invention is characterized in that, in the first or second shared memory access control method, the bank group is divided into an odd bank group and an even bank group. And

  According to the present invention, requests that can access a plurality of channels staying in the request buffer are simultaneously accessed to the memory module (storage element), so that the bank overtaking circuit is not completely multiplexed, that is, the amount of hardware is increased. While suppressing this, it is possible to increase the access efficiency to the memory module and improve the system performance.

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram of a main storage device including a memory access control system according to the present invention.

  The main storage device includes a memory module 3 having a plurality of memory bank configurations.

  The memory module 3 has a plurality of memory channels, and each memory channel is constituted by a memory element such as an SDRAM having a plurality of banks.

  In FIG. 1, (i + 1) banks of bank 00 to bank i are divided into even-numbered bank groups and odd-numbered bank groups, which are referred to as a memory module (CH0) 3-1 and a memory module (CH1) 3-2, respectively.

  The bank overtaking circuit 1 in FIG. 1 is a bank overtaking control circuit for performing bank busy control of each memory bank and realizing exclusive memory access instruction overtaking control between banks.

  The bank overtaking circuit 1 can simultaneously output a plurality (two in the figure) of requests to the memory control units 2-1 and 2-2.

  The memory control units 2-1 and 2-2 are connected as CH0 and CH1 to memory modules each composed of a plurality of banks, and generate command signals and address signals for controlling the memory elements.

  On the other hand, the write data and the read data are connected to the storage element via the data control units 4-1 and 4-2.

  FIG. 2 shows a detailed block diagram of the bank overtaking circuit 1.

  A memory access request is input as a reception request from the host device. When a memory access is performed by a certain memory access request, a bank busy time (access prohibited time) for each access instruction such as a write or read is set in the bank busy counter 142 corresponding to the accessed memory bank.

  When a request to the memory bank is received during the bank busy period, the request is stored in the request buffer 11 that can hold (m + 1) requests.

  The request is stored in the order of words (word storage) 00, 01,..., M, and the access waiting request stored in the request buffer 11 can be accessed by the bank check circuit 15 for each word of the buffer. It stays in the request buffer until this timing.

  In the request storage control method of the request buffer 11, in the case where the requests are stored in all the words, for example, when the memory request of the word 03 is canceled and output, the requests of the word 00 to 02 are held, and the word 04 ~ Word m requests are stored shifted to word 03 to word m-1, respectively.

  Here, when two requests are simultaneously output to each memory channel by releasing the bank busy, the requests are similarly shifted to a buffer that is vacant by the request output.

  For example, when the memory request for word 03 and the memory request for word 04 are simultaneously released and output, the requests for word 00 to 02 are put in the hold state, and the requests for word 05 to word m are respectively transferred to word 03 to word m-2. Is stored in a shifted state.

  That is, in each word 00-m, if the number of requests issued in the word and the younger word is 1 or more, it is stored in the older word and is issued The request information at the position specified by the number in the non-request sequence is moved to the word.

  The access busy time to the memory module is set between different busy times determined in advance by the system side between banks in the memory module or by read, write, and refresh access. , The timing at which access to CH0 and CH1 becomes possible occurs.

  By providing two request selectors for outputting requests staying in the request buffer 11 to the CH0 memory control unit 2-1 and CH1 memory control unit 2-2 in FIG. 1, the bank busy of CH0 and CH1 can be reduced. A RAM access request can be issued at the same time when the cancellation occurs at the same time.

  The bank busy circuit 14 simultaneously decodes (i + 1) counters indicating that each bank is busy and the bank address signals 12-3 and 12-4 in parallel, and the corresponding bits of the decoding result are ORed. The decoder 141 is included.

  The bank address signal 12-3 is a bank address portion of the output of the request selector 12-1. For example, if i = 15, it is 4 bits.

  Similarly, the bank address signal 12-4 is a bank address portion of the output of the request selector 12-2 and is a 4-bit signal.

  The bank address signal is decoded, and a timer value corresponding to the access type (read, write, refresh, etc.) is set in the corresponding bank busy counter.

  The bank busy counter is a counter of several bits, and if the value is not 0, it represents busy.

  The bank check circuit 15 is a circuit for determining whether or not the access bank of each word of the reception request and the buffer retention request is busy.

  A detailed block diagram of the bank check circuit 15 is shown in FIG.

  The bank check circuit 15 is supplied with each word of the buffer of the request buffer 11 and bank address signals 11-0 (B) to 11-m (B) and 11-r (B) of the access destination of the received request. At −0 to 151-m and 151-r, the value of the designated bank busy circuit 14 is referred to and it is determined whether or not each request can be output to the memory module.

  If it is not bank busy and there is a request (validity bit of each word or reception request request signal), the bank pass signal is activated and sent to the request selection circuit 16.

  A detailed block diagram of the request selection circuit 16 is shown in FIG.

  The request selection circuit 16 is a selection circuit for determining an access priority order based on the exclusive access control in the case where there are a plurality of accessible requests based on the output result of the bank check circuit 15.

  Each circuit of the CH number decoder 161 determines a destination channel of the reception request and the request of each word of the request buffer. For example, if the least significant bit of the bank address in the reception request and each word is “0”, it is determined as CH0, and if it is “1”, it is determined as CH1.

  The CH select circuit 162 develops the bank pass signal of each word indicating that each request is accessible for CH0 and CH1, activates the signal corresponding to the determined channel, and supplies it to the word select circuit 163. .

  The word select circuit 163 separates the requests that can be output for each CH by the CH select circuit 162, and prioritizes the requests for actual memory access.

  That is, this is a circuit for realizing exclusive control for the same memory address (bank).

  The specific prioritization is performed in the order of the words 00, 01, 02,..., M, and the received requests, thereby overtaking requests between different banks while guaranteeing the access order to the same bank.

  The CH0 word select signal 16-1 generated by the word select circuit 163 is a request selector 12-1 for selecting an access request to CH0, and the CH1 word select signal 16-2 is a request for selecting an access request to CH1. This is a selection instruction in the selector 12-2.

  An access request is issued as a request output CH0 and a request output CH1 from each word and reception request shown in the request buffer 11, and a request is issued to the CH0 memory control unit 2-1 and the CH1 memory control unit 2-2 shown in FIG.

  Next, the operation of the best mode for carrying out the present invention will be described with reference to the drawings.

  The operation of the memory access control system of the present invention will be described based on the time charts of FIGS. 5 and 6 and with reference to FIGS.

  It is assumed that the reception request is input to the bank overtaking circuit 1 every machine cycle (hereinafter referred to as T).

  For the sake of brevity, it is assumed that the same bank busy time at the time of write access to each memory bank is 5T, and the same bank busy time at the time of read access is 4T, assuming that access is concentrated in the bank 00 and bank 01. .

  Also, the time required for output after inputting a request (reception request) to the bank overtaking circuit 1 is 1T.

  At time T1 in FIG. 5, write access to request R00-0 (bank 00 write), at T2, request R01-0 (bank 01 read), at T3 request R00-1 (bank 00 write), at T4 R01- Assume that requests are received in the order of 1 (bank 01 read), request R00-2 (bank 00 write) at T5, and R01-2 (bank 01 read) at T6.

  First, the requests R00-0 and R01-0 are permitted to be output by the bank check circuit 15 and the request selection circuit 16 in FIG. 2, and are output from the request output CH0 and the request output CH1 to the corresponding memory control unit.

  On the other hand, bank 00 busy information and bank 01 busy information are set in the bank busy circuit 14 of FIG.

  Subsequent memory access requests are stored in the request buffer 11 in the bank overtaking circuit 1 because the bank is busy.

  At T6 of the time chart, busy of the bank 0 and bank 1 is canceled, and the bank check circuit 15 can access all requests R00-1, R01-1, R00-2, and R01-2. A word bank pass signal indicating the presence is enabled.

  Since the request selection circuit 16 performs control to preferentially pass the request stored in the young word, the request R00-1 stored in the word 00 and the request R01-1 stored in the word 01 are registered in the register. The request output CH0 and the request output CH1 are output at T7.

  With the request R00-1 and the request R01-1 output at T7, both the bank 00 busy information and the bank 01 busy information are set again in the bank busy circuit 14 of FIG.

  Turning to FIG. 6, at T10, the busy state of the bank 01 is canceled, and the request R01-2 stored in the word 01 can be output by overtaking the request R00-2 stored in the word 00. At T11, the request R01-2 is output, and thereafter the memory access operation is repeated in the same manner.

  The time charts of FIGS. 5 and 6 also show the operation by the conventional bank access control method for reference.

  In the conventional method, the request R01-1 is output at T8 and the request R01-2 is output at T13, whereas in the present invention, the request R01-1 is output at T7 and the request R01-2 is output at T11. It can be seen that the access efficiency to the storage element is improved.

  In another embodiment of the memory access control system according to the present invention, for example, when the memory request for word 03 and the memory request for word 04 in the request buffer 11 are simultaneously released and output, the requests for word 00 to 02 are held. In the first cycle, word 3 becomes an empty (missing) word, and requests for word 05 to word m are shifted and stored in word 04 to word m−1, respectively.

  In the next cycle, each request from word 04 to word m-1 is shifted to word 03 to word m-2 and stored.

  In such an embodiment, the input of the words 00 and 01 in the request buffer 11 of FIG. 2 may be a maximum of two inputs, such as a reception request and a word 01 request, and a reception request and a word 02 request.

  Next, the shared memory access control system of the present invention will be described in detail with reference to the drawings.

  FIG. 7 is a block diagram of a shared memory multiprocessor system including the shared memory access control system of the present invention.

  The shared memory multiprocessor system includes a plurality of processors 10-1 to 10-n, a shared storage device 8 shared by them, and a connection device 9 for connecting them.

  The connection device 9 includes an upstream bus 91 for the processor to transfer memory request information (request command, address) and write data to the shared storage device 8, and a downstream direction for the shared storage device 8 to return read data to the processor. A bus 92 and a controller 93 are included.

  The shared storage device 8 includes a shared memory control unit 7 and a memory module 3.

  The shared memory control unit 7 includes a bank overtaking circuit 1, a CH0 memory control unit 2-1, a CH1 memory control unit 2-2, a CH0 data control unit 4-1, a CH1 data control unit 4-2, a selection circuit 5, and a connection device. An I / F unit (connection device interface unit) 6 is included.

  The connection device I / F unit 6 includes a register 61 for receiving memory request information and the like from the connection device 9, a register 62 for holding return data such as read data to the connection device 9, and a memory request request A control data buffer 63 for temporarily storing the original identification is included.

  Other control units and circuits and the memory module 3 are the same as in the memory access control method.

  Next, the operation of the shared memory multiprocessor system will be described with reference to the drawings.

  The processor receives permission to use the upstream bus and sends memory request information (request command, address) and write data to the upstream bus 91.

  When one processor sends the next request without waiting for the reply of the memory request, the identification information within the processor is also sent.

  The connection device I / F unit 6 writes the requesting processor number or this and the in-processor identification information in one entry of the control data buffer, and receives the memory request information in the register 61.

  Memory request information is transmitted to the bank overtaking circuit 1. At this time, the address (entry number) at which the writing is performed in the control data buffer is also sent in the request information.

  Thereafter, bank busy check of memory request, overtaking control and memory access are performed in the same manner as described above.

  The read data from the CH0 data control unit 4-1 and the CH1 data control unit 4-2 are selected by the selection circuit 5 in the order in which the data is determined, the read data is held in the register 62, and the entry that has been carried around The requesting processor number or this and the identification information in the processor are read out from the control data buffer 63 by the number.

  The requesting processor number is a control signal to the connection device 9, and the in-processor identification information is added to the read data and placed on the downstream bus.

1 is a block diagram of a main storage device including a memory access control system of the present invention. FIG. 2 is a detailed block diagram of the bank overtaking circuit 1 of FIG. 1. FIG. 3 is a detailed block diagram of the request selection circuit 16 in FIG. 2. 3 is a detailed block diagram of the bank check circuit 15 of FIG. The time chart for demonstrating operation | movement of the memory access control system of this invention. The time chart for demonstrating operation | movement of the memory access control system of this invention. 1 is a block diagram of a shared memory multiprocessor system including a shared memory access control system of the present invention. The figure which shows the main memory unit which combined the memory access system containing the conventional bank check and exclusive instruction overtaking control with the type of RAM element which has the structure which can access a several bank group simultaneously.

Explanation of symbols

1 bank overtaking circuit 10-1 to 10-n processor 11 request buffer 11-0 (B) to 11-m (B) access bank address signal 12-1, 12-2 request selector 12-3, 12-4 bank address Signal 14 Bank busy circuit 141 Decoder 142 Bank busy counter 15 Bank check circuit 151-0 to 151-m, 151-r Selector 16 Request selection circuit 16-1 CH0 word select signal 16-2 CH1 word select signal 161 CH number decoder 162 CH select circuit 163 Word select circuit 2-1 CH0 memory control unit 2-2 CH1 memory control unit 3 Memory module 3-1 Memory module (CH0)
3-2 Memory module (CH1)
4-1 CH0 Data Control Unit 4-2 CH1 Data Control Unit 5 Selection Circuit 6 Connection Device I / F Unit 61 Register 62 Register 63 Control Data Buffer 7 Shared Memory Control Unit 8 Shared Storage Device 9 Connection Device 91 Uplink Bus 92 Downlink Direction bus 93 control unit

Claims (18)

A memory access control method in which a memory module is configured as a plurality of banks, and the plurality of banks are divided into several groups and controlled.
Memory control means for each bank group;
A request buffer for storing memory requests in which the bank being accessed is busy;
For the memory request stored in the request buffer and the newly received memory request, for each bank group, a memory request in which the bank to be accessed is no longer busy is selected and issued to the corresponding memory control unit; A memory access control system comprising: A memory access control method in which a memory module is configured as a plurality of banks, and the plurality of banks are divided into several groups and controlled.
Memory control means for each bank group;
A bank busy counter for each bank that manages the busy status of each bank;
A request buffer for storing a memory request that is not busy or the access destination bank is busy, or
Bank check means for checking the busy state of the access destination bank by referring to the bank busy counter for the memory request stored in the request buffer and the newly received memory request;
Selecting one of the memory requests whose access destination bank checked by the bank check unit is no longer busy for each bank group, and issuing the selected memory request to the corresponding memory control unit. Memory access control method. The bank busy counter starts counting when a memory request to access the corresponding bank is issued to each memory control means, and sets the busy state when the memory request reaches a predetermined value corresponding to the type of request. 3. The memory access control system according to claim 2, wherein the memory access control system is released. The selection condition is that the memory request stored in the request buffer means and a newly received memory request are divided into the groups of the banks to be accessed, and the priority is given to the memory requests in each group, and the highest priority is given. 3. The memory access control method according to claim 2, wherein the memory request having a high degree is selected. The request buffer is
A plurality of word storage units each storing one piece of request information, the number of which is a priority in issuing requests,
Means for storing a newly received memory request that is not to be issued at that time in the youngest word storage section of the word storage that is free or is expected to be free in the next cycle;
When issuing a request being stored, for each word storage unit storing the request information, the number of request information issued included in the word storage unit and the word storage unit on the lower number side is one or more. A request information sequence stored in the word storage unit older than the word storage unit and not to be issued, and means for transferring the request information at the position specified by the number to the word storage unit. The memory access control system according to claim 2, wherein: 6. The memory access control system according to claim 1, wherein the bank group is divided into an odd bank group and an even bank group. A memory access control method for controlling a memory module in a plurality of banks and dividing the plurality of banks into several groups,
A memory control procedure for each bank group;
A procedure to temporarily store a memory request when the bank to be accessed is busy;
For the temporarily stored memory request and the newly received memory request, for each bank group, there is a procedure for selecting a memory request in which the bank to be accessed is not busy and passing it to the corresponding memory control procedure. A memory access control method. A memory access control method for controlling a memory module in a plurality of banks and dividing the plurality of banks into several groups,
A memory control procedure for each bank group;
A procedure for counting the elapsed cycles from the start of access to each bank to the period according to the access type and managing the busy state of each bank;
A procedure for temporarily storing a memory request that does not meet a predetermined selection condition, or whether the bank to be accessed is busy;
A bank check procedure for checking the busy state of the access destination bank by referring to the result of the managing procedure for the temporarily stored memory request and the newly received memory request;
And selecting one of the memory requests whose access destination bank checked by the bank check procedure is no longer busy for each bank group, and passing the selected memory request to a corresponding memory control procedure. Access control method. 9. The memory access control method according to claim 7, wherein the bank group includes two groups, an odd bank group and an even bank group. A shared memory access control method in which a memory module is configured in a plurality of banks with a shared memory accessed by a plurality of processors, and the plurality of banks are divided into several groups and controlled.
Memory control means for each bank group;
A request buffer for storing memory requests in which the bank being accessed is busy;
For the memory request stored in the request buffer and the newly received memory request, for each bank group, a memory request in which the bank to be accessed is no longer busy is selected and issued to the corresponding memory control unit; A shared memory access control system comprising: A shared memory access control method in which a memory module is configured in a plurality of banks with a shared memory accessed by a plurality of processors, and the plurality of banks are divided into several groups and controlled.
Memory control means for each bank group;
A bank busy counter for each bank that manages the busy status of each bank;
A request buffer for storing a memory request that is not busy or the access destination bank is busy, or
Bank check means for checking the busy state of the access destination bank by referring to the bank busy counter for the memory request stored in the request buffer and the newly received memory request;
Selecting one of the memory requests whose access destination bank checked by the bank check unit is no longer busy for each bank group, and issuing the selected memory request to the corresponding memory control unit. Shared memory access control method. The bank busy counter starts counting when a memory request to access the corresponding bank is issued to each memory control means, and sets the busy state when the memory request reaches a predetermined value corresponding to the type of request. 12. The shared memory access control method according to claim 11, wherein the shared memory access control method is canceled. The selection condition is that the memory request stored in the request buffer and a newly received memory request are divided into the groups of the bank to be accessed, and the priority is given to the memory requests in each group, and the highest priority 12. The shared memory access control method according to claim 11, wherein the memory request having a higher value is selected. The request buffer is
Each of them can store one request information, a plurality of word storage whose number is a priority in issuing requests,
Means for storing a newly received memory request that is not to be issued at that time in the youngest word memory among the word memories that are free or are expected to be free in the next cycle;
When issuing a request being stored, for each word storage unit storing the request information, the number of request information issued included in the word storage unit and the word storage unit on the lower number side is one or more. A request information sequence stored in the word storage unit older than the word storage unit and not to be issued, and means for transferring the request information at the position specified by the number to the word storage unit. 12. The shared memory access control method according to claim 11, wherein: 15. The shared memory access control system according to claim 10, wherein the bank groups are two groups, an odd bank group and an even bank group. In a shared memory accessed by a plurality of processors, a memory module is configured in a plurality of banks, and the plurality of banks are divided into several groups and controlled.
A memory control procedure for each bank group;
A procedure to temporarily store a memory request when the bank to be accessed is busy;
For the temporarily stored memory request and the newly received memory request, for each bank group, there is a procedure for selecting a memory request in which the bank to be accessed is not busy and passing it to the corresponding memory control procedure. A shared memory access control method. In a shared memory accessed by a plurality of processors, a memory module is configured in a plurality of banks, and the plurality of banks are divided into several groups and controlled.
A memory control procedure for each bank group;
A procedure for counting the elapsed cycles from the start of access to each bank to the period according to the access type and managing the busy state of each bank;
A procedure for temporarily storing a memory request that does not meet a predetermined selection condition, or whether the bank to be accessed is busy;
A bank check procedure for checking the busy state of the access destination bank by referring to the result of the managing procedure for the temporarily stored memory request and the newly received memory request;
And a procedure for selecting, for each bank group, one of the memory requests whose access destination bank checked by the bank check procedure is no longer busy and passing the selected memory request to the corresponding memory control procedure. Memory access control method. 18. The shared memory access control method according to claim 16, wherein the bank group includes two groups of an odd bank and an even bank.

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