JPH11110289A - Buffer control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To store data in a buffer without suppressing data transfer even when a plurality of data are transferred to the same bank of the buffer in the same cycle. SOLUTION: A plurality of data transferred from a storage device are stored in a register 1C by way of a selector 1B, a circuit 1G inputs a valid bit and an identifier of the data of the register 1C, detects a bank competition of the data and selects one datum out of data causing the bank competition, a circuit 1I inputs an output of the circuit 1G and selects data to be stored when the plurality of data stored in the register 1C can simultaneously be stored in a buffer 1Q, a selector 1N selects data to be transferred to the buffer 1Q from the register 1C in accordance with an output of the circuit 1I, the circuit 1L inputs an output of the circuit 1I and an empty bit of each register 1C and generates a control signal for a selector 1B for selecting transfer data to be stored in the register 1C, and a selector 1P stores data outputted from the selector 1N in each bank of the buffer 1Q.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for controlling access to a storage device in a computer system, and more particularly to a buffer for improving the efficiency of a buffer for rearranging data randomly read from the storage device. Related to the control method.

[0002]

2. Description of the Related Art In a computer system which realizes concealment of access latency to a storage device by continuously issuing a data read request to the storage device, a data read request issued to the storage device can be performed. By adding an identifier to the read data from the storage device and by adding the identifier to the data read from the storage device, an access method to the storage device using an identifier addition method for identifying transfer data from the storage device corresponding to each data read request is used. (Japanese Patent Application Laid-Open No. 60-136849). The main memory of current supercomputers generally adopts a multi-bank system in which independently operable storage devices are arranged in parallel in order to secure throughput, and thus the main memory corresponding to a read request is used. Data transferred from the storage is not always transferred in the order in which the read requests were issued to the main storage. Therefore, the device in the system that has issued the data read request to the main memory temporarily stores the data in the buffer so that the data transferred from the main memory in a random order can be used in the order in which the read request was issued. The data must be rearranged by storing.

In the above-described access method to a storage device, a plurality of transfer data from the storage device in response to a data read request from a device in the system is transferred in one cycle, and the data is random with respect to the identifier. Conventionally, one register is assigned to each identifier of a data read request so that those data can be stored in a buffer without inhibiting data transfer from a subsequent storage device. ,
By configuring a buffer with these registers, the data is rearranged so that data transferred from the storage device in a random order can be used in the order in which the read requests were issued. At this time, for the data transferred from the storage device in response to the data read request, the register to be stored is determined by decoding the added identifier.

[0004]

In recent years, with the speeding up of computer systems, the access latency to main storage has increased. In such a situation, in the access method to the storage device by the identifier addition method, more read requests must be continuously issued to the storage device in order to conceal access latency to the storage device. That is, more identifiers must be prepared, and a large-capacity buffer for rearranging read data must be secured. However, in the buffer control method described above, since the buffer is configured by a large number of registers, a very large number of gates are consumed, and it is difficult to configure a large-capacity buffer in implementation. There was a point.

Therefore, it is conceivable to reduce the number of gates by configuring the buffer in a multi-bank system using a register file array, a RAM, and the like. Problems arise. When a buffer is configured in a multi-bank system using a register file array, RAM, or the like, generally, the contents of an identifier correspond to the number of a bank for storing data and an address in the bank, so that a storage device can be used. Determine the storage location of the data transferred from. At this time, when a plurality of data stored in different banks are transferred from the storage device in the same cycle, those data are stored in the bank determined by the added identifier, but are stored in the same bank. When multiple data are transferred in the same cycle, the number of data that can be stored in one bank during one cycle is limited. And store it there. Then, after there is no other data stored in the same bank as the bank in which the data is stored, the data must be stored in the corresponding bank. At this time, if the number of registers for temporarily storing data is insufficient, when bank contention frequently occurs, even if data transferred from a subsequent storage device is data stored in a different bank, storage Transfer of data from the storage device must be suppressed, and the performance of reading data from the storage device may be degraded.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problem, so that even if a plurality of data stored in the same bank of the data rearrangement buffer is transferred from the storage device in the same cycle, the storage device can store the data in the same cycle. Data can be stored in a buffer without suppressing data transfer, and a buffer for rearranging read data from the storage device can be stored in a register file array or the like.
An object of the present invention is to propose an efficient buffer control method configured by a multi-bank method using a RAM or the like.

Furthermore, in the above-mentioned method, in order to guarantee the number of cycles until data in which a bank conflict has occurred is stored in a rearranging buffer, a plurality of data stored in an arbitration circuit or a register for bank conflict are stored. When the arbitration circuit for the case where data of the same type can be stored in the buffer at the same time employs an arbitration method such as a round robin method, the number of states is determined by the number of registers for temporarily storing transfer data from the storage device. When the number increases, the number of states increases and control becomes complicated. Therefore, a second object of the present invention is to guarantee the number of cycles until data stored in a bank conflict is stored in a buffer for sorting by a simple arbitration method,
Another object of the present invention is to propose a buffer control method in which data transferred from a storage device is stored in the same bank in the order in which the data is transferred from the storage device.

[0008]

According to the present invention, there is provided a buffer control method for rearranging data read from a storage device and storing the data in a buffer. A plurality of registers for temporarily storing a plurality of transferred data, a first selector for selecting and storing transfer data to be stored in the registers in accordance with a control signal, and data stored in each of the registers A valid bit and an identifier, and a bank conflict detection and arbitration circuit for detecting bank conflict of data and selecting one data from the data causing the bank conflict, and inputting the output of the circuit and storing the data in a register. A storage request arbitration circuit for selecting data to be stored when a plurality of data items can be stored in the buffer at the same time; A second selector for selecting data to be transferred to the buffer from the register in accordance with the output,
An input data storage register selection circuit for receiving the output of the circuit and the Empty bit of each register, generating a control signal for selecting transfer data to be stored in the register, and outputting the control signal to the first selector; A third selector for storing data output from the selector of each buffer in each bank of the buffer. Even if a plurality of data read at random from the storage device in the same cycle causes a bank conflict, the data is read from the storage device. Read data is stored in a buffer without suppressing data transfer, and a buffer for rearranging read data from a storage device is configured by a multi-bank method using a register file array or RAM. I have.

Further, a counter is provided which is updated every cycle of a data transfer cycle from the storage device. Each of the registers stores a counter value of the counter at the time of transfer of the data transferred to the register, and the bank conflict is generated. The detection and arbitration circuit further receives the counter value, detects a bank conflict of data, selects one data from the data in which the bank conflict occurs, includes the counter value in the data selection output, and stores the stored data. The request arbitration circuit inputs a data selection output including the counter value, selects data to be stored when a plurality of data stored in the register can be simultaneously stored in the buffer, and outputs data transferred from the storage device. Are stored in the same bank in the order in which they are transferred from the storage device. Storing, data transferred from the storage device is to ensure the maximum number of cycles stored in the register until is stored in the buffer.

Further, a plurality of data transfer paths read from the storage device are connected to the register, and are directly connected to the bank conflict detection / arbitration circuit and the second selector.
When the arbitration circuit and the storage request arbitration circuit detect that the data transferred from the storage device does not cause a bank conflict, the data bypasses the register and bypasses the register. And store it in a buffer.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 Hereinafter, an embodiment of a buffer control system according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a buffer to which the present invention is applied.

In FIG. 1, 1A is a path for transferring data from a storage device, 1B is a selector for storing data transferred from the storage device in a register, and 1C is a selector for temporarily storing data transferred from the storage device. 1D is a path for transferring the Valid bit and identifier of the data stored in the register 1C to the bank conflict detection & arbitration circuit, and 1E is for selecting the Empty bit (inversion of the Valid bit) as the input data storage register 1F is a path for transferring data and an identifier stored in a register, 1G is a bank conflict detection and arbitration circuit for data stored in a register, and 1H is a buffer for data stored in a register. 1I is the arbiter for the data issuing the storage request to the buffer. Shon circuit, 1 J is a control signal for selecting the data to be stored in the buffer,
1K is a path for transferring information about registers which become empty in the next cycle by outputting data, 1L is a circuit for selecting a register for storing data transferred from the storage device, and 1M is a circuit for selecting a register for storing data transferred from the storage device. Control signal for storing the data stored in the register, 1N is a selector for selecting data to be transferred from the data stored in the register to the buffer, 10O is a path for transferring the data stored in the register to the buffer, 1P is a selector for storing data transferred from the register in a corresponding bank, and 1Q is a register file array or a RAM constituting a buffer by a multi-bank system.

In the first embodiment of the present invention configured as described above, when data is transferred from the storage device via the data transfer path 1A, the selector 1B empties out of the plurality of registers 1C prepared by the selector 1B. The data is stored in either the current register or the register that becomes empty in the next cycle. At this time, in which register the data transferred from the storage device is stored is determined by the storage register selection circuit 1L for the input data (described later).
The number of registers that must be prepared at this time depends on the bandwidth of the data transfer path 1A from the storage device and the depth of each bank 1Q that constitutes the buffer (when the number of write ports is one). When the number of write ports is two or more, it is determined by (the depth of each bank constituting the buffer divided by the number of write ports) is the bank depth here.

Below, the bandwidth of the transfer path 1A and the bank
Describe the depth of 1Q and the required number of registers 1C. Regarding the data transferred from the storage device, the register 1C must have a number sufficient to store all the data causing the bank conflict. In the worst case where transfer data from the storage device causes a bank conflict, a case where a plurality of data transferred from the storage device in the same cycle are all stored in the same bank,
This is when it occurs in a continuous cycle. In FIG. 1, when the bandwidth of the data transfer path 1A from the storage device is 4 data / cycle and the depth of each bank 1Q constituting the buffer is 8, the data stored in the same bank is the data from the storage device. When data is continuously transferred using the full bandwidth of the transfer path 1A, the buffer receives four data per cycle, but only one of the data can be stored in the buffer. The number of cycles until all data stored in the same bank is transferred is 2 cycles (= 8 data ÷ 4 data / cycle), and only one data can be stored in the buffer during that time. There is (the stored data does not exist in the first cycle). Therefore, when data stored in the same bank is continuously transferred from the storage device, the timing shown in FIG. 2 is obtained.

If the transfer of all data stored in bank # 1 is continued after the transfer of all data stored in bank # 0 is completed, the data stored in bank # 1 In the cycle in which the data stored in the bank # 0 is transferred from the storage device, the data stored in the bank # 0 is stored in the buffer at a rate of 1 data / cycle. The number of reply data stored in the register is 12. Similarly, in a cycle in which data stored in bank # 2 is continuously transferred from the storage device, the entire data stored in bank # 0 and bank # 1 are stored in the buffer at a rate of 2 data / cycle. Therefore, when all the data stored in the bank # 2 is transferred, the number of data stored in the register becomes 15. After the transfer of the data stored in bank # 3, the data stored in register 1C spans four banks, so that the transfer data throughput from the storage device and the storage throughput to the buffer are equal. When the data stored in the register 1 is transferred, 16 data are stored in the register, but no more data is stored in the register 1C.

Generally, a data transfer path from a storage device
The bandwidth of 1A is A, and the depth of each bank 1Q constituting the buffer is B data. As described above, when data stored in the same bank is successively transferred from the storage device, one data is stored in the buffer for each cycle in which the data is transferred.
Up to B- (B / A-1) pieces are stored in 1C, and then stored in the buffer at a rate of 1 data / cycle. This occurs continuously for each bank (here, banks # 0, # 1, #
2, # 3,...), And the maximum number of data stored in the register 1C is as follows.

Time point when all data stored in bank # 0 is transferred B- (B / A-1) Time point when all data stored in bank # 1 is transferred 2 *
｛B- (B / A-1)｝-(B / A) When all data stored in bank # 2 has been transferred 3 *
｛B- (B / A-1)｝-｛2 * (B / A) + (B / A)｝ When all data stored in bank # 3 is transferred 4 *
｛B- (B / A-1)｝-｛3 * (B / A) + 2 * (B / A) + (B / A)｝ When all data stored in bank #n is transferred ( n +
1) * ｛B- (B / A-1)｝-｛(n + 1) * n / 2｝ * (B / A) (n ≦ A + A / B-1.n> A + A / B When the value is -1, the leading data stored in the register 1C sequentially changes to # 1, # 2, # 3, ....) All the data stored in the bank #n has been transferred from the storage device. At this time, the maximum number of data stored in register 1C is (n + 1) * ｛B- (B / A-1)｝-｛(n + 1) * n / 2｝ * (B / A) Therefore, the maximum value of the number of data stored in register 1C is 1 /
2 * (A + A / B-1 / 2) * (B−B / (2 * A) +1) (rounded down).

The data stored in the register 1C issues a buffer storage request to the bank conflict detection & arbitration circuit 1G in the next cycle.
The bank conflict detection & arbitration circuit 1G detects a bank conflict that stores the data stored in the register 1C, selects one of the data in which the bank conflict occurs, and selects a storage request arbitration circuit. Issues a storage request to 1I.

FIG. 3 shows a configuration example of the bank conflict detection & arbitration circuit 1G. In FIG. 3, 1D- # a is a Valid bit (request signal) of the data stored in the register 1C, and 1D- # b is a part of the identifier of the data stored in the register 1C (the data is stored). Bank number), 3A indicates a comparator related to the bank number, 1H- # indicates a storage request that has no bank contention or is given priority even if there is a bank contention (in the figure, “1” when there is no bank contention,
In this case, it becomes '0') and is transferred to the storage request arbitration circuit 1I via the path. The bank conflict detection & arbitration circuit shown in FIG. 3 employs a fixed priority scheme based on register numbers for processing when bank conflict occurs. In the logic circuit that outputs the storage request output 1H-n of the n-th register 1C, the valid bit of the data stored in the n-th register 1C and a part of the data identifier, and all of the register numbers smaller than n The valid bit of the data of the register 1C and a part of the data identifier are input. However, the logic circuit corresponding to the 0th register 1C is not provided, and the value of the Valid bit of the data stored in the 0th register 1C is 1H-0.
Is output as is. Then, the n-th logic circuit compares a part of the identifier stored in the register 1C whose register number is smaller than n and a part of the identifier stored in the n-th register 1C with the comparator 3A, In addition, Va stored in the register 1C whose register number is smaller than n
The lid bit is determined, and the comparison result, the determination result, and n
Depending on the value of the Valid bit stored in the 1st register 1C, the condition that the comparison result is not equal or the data of the comparison partner is not valid depends on the data stored in all registers whose register number is smaller than n. And Va stored in the n-th register 1C
A storage request is issued to the storage request arbitration circuit 1I only when the value of the lid bit indicates valid.

In the storage request arbitration circuit 1I,
In response to the storage request signal 1H, if the number of storage requests to the buffer exceeds the bandwidth of the data transfer path 10 to the buffer, select a number of data that matches the bandwidth of the transfer path 10 out of them. Transfer. FIG. 4 shows a configuration example of the storage request arbitration circuit 1I. In FIG. 4, 1H
Is the storage request signal transferred from the bank conflict detection & arbitration circuit 1G, and 4A is the range of the request issuing source.
4B- # is a storage request signal transferred at 1H, and 4C is a circuit for calculating the number of storage request issuances when 2 to 15 storage requests are issued.
-# Is a control signal indicating the number of storage request issuance data having a higher priority than the register, 1J is a control signal for selecting data to be stored in the buffer, 1K is a control signal transferred to the input data storage register selection circuit, 1K- # a is a signal indicating that the data of the register can be stored in the buffer, and 1K- # b is a control signal indicating the number of data having a higher priority than the data.

FIG. 5 shows 4A (0) and 4A of circuits 4A (comprising 4A (1) to 4A (28)) for calculating the number of storage requests issued.
(8) and 4A (17) are shown as examples, and truth tables of input signals and output signals in these circuits are shown. As shown in FIG.
If the bandwidth of the data transfer path from the storage device is 4 data / cycle and the depth of the buffer bank is 8 data, if the number of data to be stored from the register 1C to the buffer can be at most 4 data / cycle, Even in the worst case in which bank contention occurs, data can be stored in the buffer without suppressing data transfer from the storage device. In FIG. 1, when the bandwidth of data transfer from the register to the buffer is 4 data / cycle, in FIG. 5, it is sufficient to recognize that there are three or less pieces of data having a higher priority than itself, If there are four or more data, the selected port is invalidated by setting all output signals shown in the truth table of FIG. 5 to 0. In FIG. 5, the processing is performed by the fixed priority method using the number of the register 1C. When the data stored in the register issues a storage request, the number of storage requests from a register having a smaller register number than the register is determined. Is 0, the 4C- # 0 signal is activated, and when the number of storage requests from the register with the smaller register number is 1, the 4C- # 1 signal is activated and the 4C- # signal is activated. When the number of storage requests from the register with the smaller register number is 2, the signal 4C- # is activated, and when the number of storage requests from the register with the smaller register number is 3, the 4C- # signal is activated. 3 Activate the signal.

Although not shown in FIG. 5, the number of storage requests from a register whose register number is smaller than the register concerned is
When it is 4 or more, as described above, the output signal is 0 signal, 1 signal
Set all signals, 2 signals and 3 signals to 0. In this way, by using these signals as the control signal 1J for the data selector 1N, the data stored in the register is transferred to the buffer.

In the case of the circuit 4A (0) of FIG. 4, as shown in the truth table of FIG.
When # 0 and # 1 are 0 and 0, the number of storage requests (# 0
-# 1) is 0 signal is '1', 1 signal is '0', 2 signal is '0', and when # 0 and # 1 are 0 and 1, 0 signal is '0' and 1 signal Is '1',
When 2 signals are '0' and # 0 and # 1 are 1 and 0, 0 signal is'
0 signal, 1 signal is '1', 2 signal is '0', and when # 0 and # 1 are 1 and 1, 0 signal is '0', 1 signal is '0', 2 signal is '1''.

The output signal is 4C-0. FIG.
In the case of the circuit 4A (8), the truth table shown in FIG. In this case, the output signal of circuit 4A (0) and circuit 4A (1)
Is the input signal. Then, this output signal becomes 4C-2. In the case of the circuit 4A (17) in FIG. 4, FIG.
As shown in the truth table. In this case, the output signal of the circuit 4A (8) and the output signal of the circuit 4A (10) are input signals.
Then, this output signal becomes 4C-7.

The storage request arbitration circuit 1I generates a control signal 1J for the data selector 1N, and makes the input data storage register selection circuit 1L empty in the next cycle (register for outputting data). And the number of the selector 1N to which the register has transferred the data is transferred by the control signal 1K. data·
The data selected by the selector 1N is transferred to each bank 1Q of the buffer by the data transfer path 10. At this time, in the case where data is stored in all the registers 1C, in order not to suppress the data transfer from the storage device, the data transfer path 10 to the buffer must be the data transfer path 1A from the storage device.
It must have the above bandwidth. The data transferred to the buffer is taken into a predetermined bank by the data selector 1P by decoding the identifier,
Further, the storage address in the bank is determined by the identifier.

The input data storage register selection circuit 1L
Receives the Empty bit (Valid bit inverted) from the register 1C, and stores the register number to be vacant in the next cycle and the port number (selector number) output by the register from the storage request arbitration circuit 1I. The data transferred from the device is stored in a register available in the next cycle of the register 1C.
FIG. 6 shows a configuration example of the input data storage register selection circuit 1L. In FIG. 6, 6A is a circuit for calculating the number of empty registers having a smaller register number than the register concerned,
6B is a signal indicating the number of empty registers and the Empty
The bit 6C is a circuit for determining a register for storing input data transferred from the storage device, and 1M- # are control signals corresponding to each of the data selectors 1B.

FIG. 7 shows the configuration of the empty register number detection circuit 6A. In FIG. 7, the range 7A is detected by the register 1C.
A circuit for calculating the number of empty registers in the case of 2 to 15, 6B- # a is an Empty bit of the register, and 6B- # b is a signal indicating the number of empty registers having a smaller register number than the register. . The circuit shown in FIG. 7 is similar to the circuit shown in FIG. 4, and detects that there are three or less empty registers having smaller register numbers than the corresponding register. When 0, the 6B- # b 0 signal is activated, and when the number of empty registers with the smaller register number is 1, the 6B- # b 1 signal is activated, and the register is more activated than the corresponding register. When the number of vacant registers having a small number is two, the two signals of 6B- # b are activated.When the number of vacant registers having a register number smaller than the register is three, three signals of 6B- # b are activated. Activate. Then, the number of empty registers whose register number is smaller than the
When it is 4 or more, none of the signals of 6B- # b is activated.
In this case, the corresponding register will be
Do not store data transferred from the storage device.

The signal 6B composed of the Empty bit for each register and the empty register number signal output from the empty register number detection circuit 6A corresponds to each of the registers 1C together with the signal 1K received from the storage request arbitration circuit 1I. And input to the input data arbitration circuit 6C. The input data arbitration circuit 6C transfers the input data storage priority signal 1M of the register to the corresponding data selector 1B according to the truth table shown in FIG. At this time, if the signal 1M is used as it is as the control signal of the selector, the input data is not stored in the register 1C from the smaller register number, but as shown in the truth table shown in FIG. If the input data to be stored in the register is determined from the 1M and the valid bit of the data transfer path 1A, the register 1C
In the above, input data can be stored in an available register in ascending order of register number.

According to the above-described first embodiment of the present invention, in the access method for the storage device using the identifier addition method, the data transferred from the storage device in a random order with respect to the order in which the read requests are issued. The buffer for storing can be configured by a multi-bank system using a register file array, a RAM, or the like.
At this time, since there is no need to suppress data transfer from the storage device, the number of gates required to configure a large-capacity buffer can be reduced without lowering the performance of reading data from the storage device.

Second Embodiment As shown in FIG. 10, a second embodiment of the present invention is different from the first embodiment of the present invention shown in FIG.
It is configured by adding a path 10B for transferring them to the register 1C and a register 10C for holding a counter value when data from the storage device is stored in the register 1C. In the path 1D, the data Va of the register 1C is used.
Transfer counter value in addition to lid bit and identifier.
Hereinafter, only differences from the first embodiment will be described.

The second embodiment of the present invention constructed as described above
In the embodiment, when data is transferred from the storage device via the data transfer path 1A, the data selector 1B outputs the input data to either an empty register among the registers 1C or a register which becomes empty in the next cycle. The data is stored according to the control signal 1M from the storage register selection circuit 1L. At this time, the value of the counter 10A is transferred to the register 10C by the path 10B.

FIG. 11 shows a configuration example of the bank conflict detection & arbitration circuit 1G. In FIG. 11, 1D- # a is a Valid bit of the data of the register 1C, and 1D- # b is a register 1C.
Part of the data identifier (storage bank number), 1D- # c is the value of the counter 11A when the data is stored in the register 1C, 11A is the comparator related to the bank number, and 11B is the register of the data rather than the register of the data. A comparator 11C is a comparator relating to the counter value with the data of the register having the larger number, and 11C is a comparator relating to the counter value with the data of the register having the smaller register number than the register of the data. The bank conflict detection & arbitration circuit shown in FIG. 11 gives priority to a smaller counter value when bank conflict occurs, and gives priority to a smaller register number when the counter values are equal. Request arbitration circuit
Issues a buffer storage request to 1I.

FIG. 12 shows a storage request arbitration circuit.
An example of the configuration of 1I is shown. In FIG. 12, 1H- # a is a storage request signal transferred from the bank conflict detection & arbitration circuit 1G, 1H- # b is a counter value added to the data, and 12A is a register number which is larger than the register of the data. A comparator for the counter value with the data of the large register, 12B is a comparator for the counter value with the data of the register whose register number is smaller than the register of the data, and 12C is a register having a higher storage priority to the buffer than the register. Circuit for calculating numbers, 1J is a selector
A control signal to be transferred to 1N, 1K- # a is a signal indicating that data of the register is stored in the buffer, 1K- # b is a signal indicating the number of data having a higher priority than the data, and a signal 1K Is transferred to the storage register selection circuit 1L for input data.

The circuit 12C for calculating the number of registers having a higher storage priority in the buffer than the register can be constituted by a circuit similar to the circuit shown in FIG. FIG.
When the number of storage requests exceeds the bandwidth of the data transfer path 10 to the buffer, the storage request arbitration circuit 1I shown in (1) gives priority to the smaller counter value, and furthermore, if the counter values are equal, the register number is Transfer the data to the buffer, giving priority to the smaller one. Except for the above, the operation is basically the same as that of the first embodiment.

According to the above-described second embodiment of the present invention, in addition to the effects shown in the first embodiment, data stored in the same bank is stored in the buffer in the order transferred from the storage device. It is possible to do. further,
Since the maximum number of cycles until the data stored in the register 1C is stored in the buffer is guaranteed, it can be ensured that specific data does not sink in the output from the register 1C.

<Third Embodiment> In a third embodiment of the present invention, as shown in FIG. 13, the configuration of the first embodiment of the present invention shown in FIG. 1 is controlled by a data transfer path 1A from a storage device. Transfer path 13 to bypass to signal 1D and data transfer path 1F
It is constructed by adding A. Hereinafter, only differences from the first embodiment will be described.

In the third embodiment of the present invention configured as described above, when data is transferred through the data transfer path 1A, the data is transferred to the data selector 1B and at the same time as the bypass path 13A. Thus, the Valid signal and the storage bank number are transferred to the bank conflict detection & arbitration circuit 1G. The bank conflict detection & arbitration circuit 1G and the storage request arbitration circuit 1I add the virtual register numbers to these bypassed data, thereby performing the same processing as that shown in the first embodiment of the present invention. Do. At this time, if the data transferred from the storage device does not cause a bank conflict with other data, it is not necessary to store the data in the register 1C, so that the number of registers that must be prepared in the register 1C is reduced. It becomes possible.

As in the first embodiment, the bandwidth of the data transfer path 1A from the storage device is A data / cycle, and the depth of each bank 1Q constituting the buffer is B data. When data stored in the same bank is successively transferred from the storage device, one data can be stored in the buffer even in the first cycle in which the data is transferred. Up to (BB / A) registers are stored in register 1C, and then 1 data /
Stored in the buffer at the rate of the cycle. This occurs continuously for each bank (here, banks # 0, # 1,
# 2, # 3,...), And the maximum number of data stored in the register 1C is as follows. When all data stored in bank # 0 has been transferred B-
When all data stored in B / A bank # 1 has been transferred 2 *
(BB / A) -B / A Time point 3 * (B
-B / A)-｛2 * (B / A) + (B / A)｝ When all data stored in bank # 3 is transferred 4 * (B
-B / A)-{3 * (B / A) + 2 * (B / A) + (B / A)} When all data stored in bank #n is transferred (n +
1) * (BB / A)-｛(n + 1) * n / 2｝ * (B / A) (n ≦ A-1. When n> A-1, the top stored in register 1C The data sequentially changes to # 1, # 2, # 3, ....) When all the data stored in the bank #n has been transferred from the storage device, the data stored in the register 1C is maximum. (n + 1) * (BB / A)-｛(n + 1) * n / 2｝ * (B / A)
The maximum value of the number of data stored in register 1C is (1 /
8) * (4 * A * B-4B + B / A) (rounded down). If the bandwidth of the data transfer path 1A from the storage device is 4 data / cycle and the depth of the bank is 8 data, in the case of the first embodiment, 16 registers 1C are required in the case of the first embodiment. In some cases, register 1C may be 12 registers.

In the input data storage register selection circuit 1L, when the data transferred by the bypass path 13A is stored in the buffer, the control signal for the data selector 1B corresponding to the data must be canceled. . This is configured as shown in FIG. 14 by associating a virtual register number of bypassed data with a port number of input data on a one-to-one basis. FIG.
In 4, 14A is a circuit for calculating the number of empty registers in the register 1C, 14B is an output signal of the empty register number detection circuit 14A, and 14C is a circuit for selecting data to be stored in the register 1C. Empty register detection circuit 14A, input data
The arbitration circuit 14C is configured by a circuit similar to that of the first embodiment. Signal 1K-12a, 1K-13a, 1K-14a, 1K-15a
Are signals indicating that data 0 to 3 transferred from the storage device can be stored in the buffer. When these signals are true, the select signal of the corresponding input data is suppressed. Except for the above, the operation is basically the same as that of the first embodiment.

According to the above-described third embodiment of the present invention, in addition to the effects shown in the first embodiment, the data transferred from the storage device must cause a bank conflict with other data. For example, since such data can be directly transferred to the buffer, the latency can be reduced and the number of registers for temporarily storing transfer data from the storage device can be reduced.

[0041]

According to the present invention as described above,
An access method for a storage device in which transfer data from a storage device in response to a data read request issued by a component in a computer system is transferred in a random order, not in the order in which the requests were issued, In a storage device access method in which data is managed by an identifier addition method, a large-capacity buffer is formed by configuring a buffer for storing data in a multi-bank method using a register file array, a RAM, or the like. In this case, the number of gates can be reduced. Also, at this time, it is possible to eliminate the need to suppress data transfer from the storage device, and in accessing the storage device,
Data transfer performance can be prevented from lowering.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a buffer control method according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a worst transfer pattern that causes a bank conflict of transfer data from a storage device.

FIG. 3 is a diagram illustrating a configuration example of a bank conflict detection & arbitration circuit in FIG. 1;

FIG. 4 is a diagram illustrating a configuration example of a storage request arbitration circuit in FIG. 1;

FIG. 5 is a diagram showing a truth table in a configuration example of a part of a circuit for calculating the number of storage requests in FIG. 4;

FIG. 6 is a diagram illustrating a configuration example of an input data storage register selection circuit in FIG. 1;

FIG. 7 is a diagram illustrating a configuration example of a circuit for calculating the number of empty registers in FIG. 6;

8 is a diagram illustrating a truth table in a configuration example of the input data arbitration circuit in FIG. 6;

9 is a diagram illustrating another truth table in the configuration example of the input data arbitration circuit in FIG. 6;

FIG. 10 is a diagram showing a configuration of a buffer control system according to a second embodiment of the present invention.

11 is a diagram illustrating a configuration example of a bank conflict detection & arbitration circuit in FIG. 10;

FIG. 12 is a diagram illustrating a configuration example of a storage request arbitration circuit in FIG. 10;

FIG. 13 is a diagram showing a configuration of a buffer control system according to a third embodiment of the present invention.

14 is a diagram illustrating a configuration example of an input data storage register selection circuit in FIG. 13;

[Explanation of symbols]

1A Path for transferring data from a storage device 1B Selector for storing data transferred from a storage device in a register 1C Register for temporarily storing data transferred from a storage device 1D Stored in a register Control signal for data 1E Control signal for empty register 1F Path for transferring data stored in register 1G Bank conflict detection & arbitration circuit for data stored in register 1H Storage request signal to buffer for data in 1H register 1I buffer Arbitration circuit for data issuing a storage request to memory 1J Control signal for selecting data to be stored in buffer 1K Control signal for register vacant in next cycle 1L Input data storage register selection circuit 1M input data Control signal for storing data in the register 1N Selector for selecting data to be transferred from the data of the register to the buffer 1O Path for transferring the data of the register to the buffer 1P Selector for storing the data in each bank 1Q Buffer Bank (register file array, RAM, etc.) 3A Comparator for bank number 6A Number of empty registers detection circuit 6B Control signal for number of empty registers 6C Input data arbitration circuit 7A Circuit for calculating the number of empty registers 10A Counter 10B Counter value 10C Register for holding counter value 11A Comparator for bank number 11B, 11C Comparator for counter value 12A, 12B Comparator for counter value 12C Register with high storage priority to buffer Forwarding path for bypassing the circuit 13A data for calculating the number

Claims (3)

[Claims] 1. A buffer control method for rearranging data read from a storage device and storing the rearranged data in a buffer, wherein the buffer control system temporarily stores a plurality of data read and transferred from the storage device. A plurality of registers, a first selector for selecting and storing transfer data to be stored in the registers in accordance with a control signal, and a valid bit and an identifier of the data stored in each of the registers; A bank conflict detection and arbitration circuit for detecting and selecting one data from the data causing a bank conflict; and an output of the bank conflict detection and arbitration circuit, when a plurality of data stored in a register can be simultaneously stored in a buffer. A storage request arbitration circuit for selecting data to be stored, and transferring data from a register to a buffer in accordance with an output of the circuit. A second selector for selecting data, an input for receiving an output of the circuit and an Empty bit of each register, generating a control signal for selecting transfer data to be stored in the register, and outputting the control signal to the first selector A data storage register selection circuit; and a third selector for storing the data output from the second selector in each bank of the buffer. Even if an error occurs, the read data is stored in the buffer without suppressing the transfer of the read data from the storage device, and the buffer for rearranging the read data from the storage device is formed using a register file array, a RAM, or the like. A buffer control method comprising a multi-bank method. 2. The buffer control method according to claim 1, further comprising: a counter that is updated every cycle of a data transfer cycle from the storage device, wherein each of the registers includes a counter for transferring data transferred to the register. The bank conflict detection and arbitration circuit further receives the counter value, detects the bank conflict of data, selects one data from the data in which the bank conflict occurs, and selects the data. Including the counter value in the output, the storage request arbitration circuit inputs a data selection output including the counter value and selects data to be stored when a plurality of data stored in the register can be simultaneously stored in the buffer. The data transferred from the storage device is stored in the same bank. Buffer control method that stores data in each bank in the order in which data is transferred from the storage device, and guarantees the maximum number of cycles held in a register before data transferred from the storage device is stored in the buffer. . 3. The buffer control method according to claim 1, wherein a plurality of data transfer paths read from a storage device are connected to the register, and the bank conflict detection / arbitration circuit and the bank conflict detection / arbitration circuit are directly connected to the register. The second selector is connected to the second selector, and when it is detected in the bank conflict detection / arbitration circuit and the storage request arbitration circuit that the data transferred from the storage device does not cause bank conflict, the register is bypassed. A buffer control method, wherein data that does not cause bank contention is stored in a buffer by bypassing the register.