KR19980056135A - Synchronous DRAM with Dual Port - Google Patents

Abstract

The present invention relates to a synchronous DRAM operating as a dual port. The synchronous DRAM according to the present invention includes two different banks, and when one bank reads, the other bank operates as a dual port by simultaneously performing a write operation. Here, in the read operation, the DQ pin is used as the data output pin, and in the write operation, an unknown address pin is used as the data input pin. Therefore, the synchronous DRAM according to the present invention has an advantage that the CPU can be independently accessed at the same time for each bank independently of the CPU time by operating as a dual port when the CPU displays the data of the memory device on the CRT in the image processing system.

Description

Synchronous DRAM with Dual Port

The present invention relates to a synchronous DRAM for image processing, and more particularly, to a synchronous DRAM that operates as a single port and a dual port.

1 is a diagram briefly showing an example in which a conventional single port memory device is used for image processing. The single port memory device uses a general DRAM. As shown in FIG. 1, when the DRAM 3, which is a single port memory device, is used for image processing, the CPU 1 may not perform another operation while the CRT terminal 2 is displayed. So this would consume about 50% of CPU time.

2 is a diagram briefly showing an example in which a conventional dual port memory device is used for image processing. In this case, the dual port memory device uses a general video RAM. When the video RAM 4, which is a dual port memory device, is used for image processing as shown in FIG. 2, the CPU 1 may perform another operation while the CRT terminal 2 is displayed. In this case, it consumes about 1% of CPU time.

3 is a block diagram of the dual port memory device of FIG. 2, which will be described below with reference to the dual port memory device. All data in one row of the RAM 5 is controlled by a signal called a data transfer pulse (DTP) to be transmitted to the serial access memory (SAM) 6, and the transferred data is serialized by the SAM 6 serial. To the CRT. Although not shown in FIG. 3, the RAM port is used for graphic processing such as filling or clearing graphic data, and the SAM port is used for high-speed input / output of data to the outside.

As described above, when a general DRAM is used for image processing, about 50% of CPU time is wasted.

Accordingly, an object of the present invention is to provide a synchronous DRAM operating as a single port and dual port to solve the disadvantages of the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram schematically showing an example in which a conventional single port memory device is used for image processing.

2 is a diagram briefly showing an example in which a conventional dual port memory device is used for image processing;

FIG. 3 is a block diagram of the dual port memory device of FIG. 2.

4 is a view showing an example in which a synchronous DRAM, which is a single port memory device according to the present invention, is used for image processing;

5 is a block diagram illustrating an embodiment of a synchronous DRAM according to the present invention used in FIG. 4.

6 is an operation timing diagram of the synchronous DRAM of FIG. 5.

A synchronous DRAM according to the present invention for achieving the above object is characterized by having two different banks, and one bank operates as a dual port by simultaneously performing a write operation while the other bank performs a write operation.

According to a preferred embodiment, in the read operation, the DQ pin is used as the data output pin and in the write operation, an unknown address pin is used as the data input pin.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, the advantage of the dual port memory device developed for image processing is replaced by the synchronous DRAM, which is a single port memory device, and the same function as the dual port memory device is obtained by changing some conditions using the synchronous DRAM.

4 shows an example in which a synchronous DRAM, which is a single port memory device according to the present invention, is used for image processing. Here, the CPU 1 can perform other operations while the CRT 2 is displayed. The synchronous DRAM 7 has a hierarchical memory structure and is divided into dual banks or more banks to increase the hit ratio of data requested by the CPU 1. To implement this, there are separate paths of internal RAS chains as many as the number of banks. Because of these characteristics, the present invention can be established.

FIG. 5 is a block diagram illustrating an embodiment of a synchronous DRAM according to the present invention used in FIG. 4. Referring to FIG. 5, since the A bank 8 and the B bank 9 exist, the two banks may operate similarly to the RAM port and the SAM port of the dual port memory device. In other words, when the A bank 8 performs the read operation, the B bank 9 can perform the write operation to operate as separate ports. However, because the synchronous DRAM shares the data path, in the A bank 8, the DQ pad of the existing data path is used as the data output and the address pad in the Don't Care state is used in the B bank 9. By using it as a data input (DIN) pad, it can be used as a dual port memory device as a synchronous DRAM as a single port memory device.

FIG. 6 is an operation timing diagram of the synchronous DRAM of FIG. 5. Here, the synchronous DRAM having a dual bank, a CAS latency of 3, and a read burst length of 4 will be described as an example. First, the internal clock synchronized to the CPU clock is operated, and the low address of the bank A including the low-active command and bank information of the bank A is inputted. Then, after a predetermined time tRCD, the read command of the bank A and the bank A of the bank A are input. When the column address is input, data of the A bank is output to the existing data path of the synchronous DRAM at the time of CAS latency 3, and since the burst length is 4, four A bank data are continuously output in synchronization with the internal clock. do. In this case, therefore, it operates as a single port memory. In this case, however, in the general synchronous DRAM, the B bank performs precharge or multi-bank operation. However, in the synchronous DRAM according to the present invention, the write command of the B bank is B in the column address section where Don't Care is unknown in the general synchronous DRAM. The write command of the bank is input, and the address pin at that time is used as a data input (DIN) pad to perform a write operation having a write CAS latency of 1 in the B bank. In addition, since the burst length is 4, the input data DIN of the four B banks is continuously written in synchronization with the internal clock CLOCK by a newly added separate internal counter. In this case, since the B bank is operated at the same time as the previous A bank, the same operation as the dual port memory device is performed.

Therefore, the synchronous DRAM according to the present invention has an advantage that the CPU can be independently accessed at the same time for each bank independently of the CPU time by operating as a dual port when the CPU displays the data of the memory device on the CRT in the image processing system.

Claims (2)

An image processing memory device comprising: a synchronous DRAM having two different banks, and when one bank reads, the other bank operates as a dual port by simultaneously performing a write operation. 2. The synchronous DRAM according to claim 1, wherein the read operation uses a DQ pin as a data output pin and an unknown address pin is used as a data input pin in the write operation.